[ovmf baseline-only test] 38125: all pass

[ovmf baseline-only test] 38125: all pass

[Platform Team regression test user]

This run is configured for baseline tests only.

flight 38125 ovmf real [real]
http://osstest.xs.citrite.net/~osstest/testlogs/logs/38125/

Perfect :-)
All tests in this flight passed
version targeted for testing:
 ovmf                 63e1c23b225578efdaca714a81055eadb0a07cec
baseline version:
 ovmf                 ddd89cd50dd3a989e58a75ed38011168e3ec0954

Last test of basis    38121  2015-10-03 21:18:21 Z    1 days
Testing same since    38125  2015-10-05 16:00:56 Z    0 days    1 attempts

------------------------------------------------------------
People who touched revisions under test:
  Ard Biesheuvel <ard.biesheuvel@linaro.org>
  Laszlo Ersek <lersek@redhat.com>
  Michael Zimmermann <sigmaepsilon92@gmail.com>
  Stefano Stabellini <stefano.stabellini@eu.citrix.com>

jobs:
 build-amd64-xsm                                              pass    
 build-i386-xsm                                               pass    
 build-amd64                                                  pass    
 build-i386                                                   pass    
 build-amd64-libvirt                                          pass    
 build-i386-libvirt                                           pass    
 build-amd64-pvops                                            pass    
 build-i386-pvops                                             pass    
 test-amd64-amd64-xl-qemuu-ovmf-amd64                         pass    
 test-amd64-i386-xl-qemuu-ovmf-amd64                          pass    


------------------------------------------------------------
sg-report-flight on osstest.xs.citrite.net
logs: /home/osstest/logs
images: /home/osstest/images

Logs, config files, etc. are available at
    http://osstest.xs.citrite.net/~osstest/testlogs/logs

Test harness code can be found at
    http://xenbits.xensource.com/gitweb?p=osstest.git;a=summary


Push not applicable.

------------------------------------------------------------
commit 63e1c23b225578efdaca714a81055eadb0a07cec
Author: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Date:   Fri Oct 2 14:48:30 2015 +0000

    BaseTools/AARCH64: use large code model for GCC <= 4.8
    
    As it turns out, upstream GCC only supports the AArch64 'tiny' code
    model as of version 4.9. Since the default 'small' code model requires
    4 KB section alignment (which is undesirable for the XIP modules),
    revert GCC 4.7 and 4.8 to using the 'large' code model instead.
    
    Reported-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
    Contributed-under: TianoCore Contribution Agreement 1.0
    Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
    Tested-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
    Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
    
    git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18569 6f19259b-4bc3-4df7-8a09-765794883524

commit 54d8d4dc971d326b1272095358427cb062b6e410
Author: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Date:   Fri Oct 2 14:48:21 2015 +0000

    ArmPkg/Mmu: do not configure block translations at level 0
    
    Now that the AArch64 MMU code correctly identifies and handles
    naturally aligned regions of more than 2 MB in size, it will happily
    try to use block mappings at level 0 to map huge memory regions, such
    as the single cacheable 1:1 mapping we use for Xen domU to map the
    entire PA space. However, block mappings are not supported at level 0
    so the resulting translation tables will be incorrect, causing
    execution to fail as soon as the MMU is enabled.
    
    So use level 1 as the minimum level at which to perform block
    translations.
    
    Reported-by: Julien Grall <julien.grall@citrix.com>
    Contributed-under: TianoCore Contribution Agreement 1.0
    Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
    Tested-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
    Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
    
    git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18568 6f19259b-4bc3-4df7-8a09-765794883524

commit 3b03da4058f69bd02af21e19fc2cb037c7d93557
Author: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Date:   Thu Oct 1 14:01:24 2015 +0000

    ArmVExpressPkg: use 4 KB section alignment for ARM DXE_RUNTIME_DRIVER modules
    
    In order to support the Properties Table memory protection feature
    on 32-bit ARM, build DXE_RUNTIME_DRIVER type binaries with 4 KB section
    alignment by setting the common-page-size linker command line option.
    
    Contributed-under: TianoCore Contribution Agreement 1.0
    Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
    Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
    
    git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18567 6f19259b-4bc3-4df7-8a09-765794883524

commit 955b4946f99fb9c879df235d318a68f91f5dbf0e
Author: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Date:   Thu Oct 1 14:01:16 2015 +0000

    ArmVirtPkg: use 4 KB section alignment for ARM DXE_RUNTIME_DRIVER modules
    
    In order to support the Properties Table memory protection feature
    on 32-bit ARM, build DXE_RUNTIME_DRIVER type binaries with 4 KB section
    alignment by setting the common-page-size linker command line option.
    
    Contributed-under: TianoCore Contribution Agreement 1.0
    Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
    Acked-by: Laszlo Ersek <lersek@redhat.com>
    Tested-by: Michael Zimmermann <sigmaepsilon92@gmail.com>
    
    git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18566 6f19259b-4bc3-4df7-8a09-765794883524

commit 64a63d6942532da9d162df676f2dd9e6c576921a
Author: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Date:   Thu Oct 1 14:01:07 2015 +0000

    BaseTools/ARM: move to unified GCC linker script
    
    Instead of using the ARM builtin linker script for GNU ld, use the
    new unified one instead. This will allow us to increase the section
    alignment for DXE_RUNTIME_MODULEs, which is a prerequisite for
    enabling the UEFIv2.5 Properties Table memory protection feature.
    
    Contributed-under: TianoCore Contribution Agreement 1.0
    Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
    Tested-by: Michael Zimmermann <sigmaepsilon92@gmail.com>
    Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
    
    git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18565 6f19259b-4bc3-4df7-8a09-765794883524