* [ovmf baseline-only test] 68575: all pass
@ 2017-02-17 18:37 Platform Team regression test user
0 siblings, 0 replies; only message in thread
From: Platform Team regression test user @ 2017-02-17 18:37 UTC (permalink / raw)
To: xen-devel, osstest-admin
This run is configured for baseline tests only.
flight 68575 ovmf real [real]
http://osstest.xs.citrite.net/~osstest/testlogs/logs/68575/
Perfect :-)
All tests in this flight passed as required
version targeted for testing:
ovmf eb470e05a3c7c251cfa50863ea119ba70e9777a3
baseline version:
ovmf 958163561e9b6d8fa40ea4aac49d46cc889015ac
Last test of basis 68574 2017-02-17 09:17:33 Z 0 days
Testing same since 68575 2017-02-17 16:48:48 Z 0 days 1 attempts
------------------------------------------------------------
People who touched revisions under test:
Ruiyu Ni <ruiyu.ni@intel.com>
jobs:
build-amd64-xsm pass
build-i386-xsm pass
build-amd64 pass
build-i386 pass
build-amd64-libvirt pass
build-i386-libvirt pass
build-amd64-pvops pass
build-i386-pvops pass
test-amd64-amd64-xl-qemuu-ovmf-amd64 pass
test-amd64-i386-xl-qemuu-ovmf-amd64 pass
------------------------------------------------------------
sg-report-flight on osstest.xs.citrite.net
logs: /home/osstest/logs
images: /home/osstest/images
Logs, config files, etc. are available at
http://osstest.xs.citrite.net/~osstest/testlogs/logs
Test harness code can be found at
http://xenbits.xensource.com/gitweb?p=osstest.git;a=summary
Push not applicable.
------------------------------------------------------------
commit eb470e05a3c7c251cfa50863ea119ba70e9777a3
Author: Ruiyu Ni <ruiyu.ni@intel.com>
Date: Thu Feb 16 14:01:53 2017 +0800
MdeModulePkg/PciBusDxe: Fix IA32 build failure
Compiler calculates the PciBar[BarIndex] using
sizeof (PciBar[0]) * BarIndex, when BarIndex is type of UINT64,
the above calculation generates assembly code using _allmul.
Change BarIndex to UINTN to avoid the build failure.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Wu Jiaxin <jiaxin.wu@intel.com>
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