[ovmf baseline-only test] 68582: all pass

[ovmf baseline-only test] 68582: all pass

[Platform Team regression test user]

This run is configured for baseline tests only.

flight 68582 ovmf real [real]
http://osstest.xs.citrite.net/~osstest/testlogs/logs/68582/

Perfect :-)
All tests in this flight passed as required
version targeted for testing:
 ovmf                 c035e37335ae43229d7e68de74a65f2c01ebc0af
baseline version:
 ovmf                 eb470e05a3c7c251cfa50863ea119ba70e9777a3

Last test of basis    68575  2017-02-17 16:48:48 Z    2 days
Testing same since    68582  2017-02-20 05:19:15 Z    0 days    1 attempts

------------------------------------------------------------
People who touched revisions under test:
  Zhang Lubo <lubo.zhang@intel.com>

jobs:
 build-amd64-xsm                                              pass    
 build-i386-xsm                                               pass    
 build-amd64                                                  pass    
 build-i386                                                   pass    
 build-amd64-libvirt                                          pass    
 build-i386-libvirt                                           pass    
 build-amd64-pvops                                            pass    
 build-i386-pvops                                             pass    
 test-amd64-amd64-xl-qemuu-ovmf-amd64                         pass    
 test-amd64-i386-xl-qemuu-ovmf-amd64                          pass    


------------------------------------------------------------
sg-report-flight on osstest.xs.citrite.net
logs: /home/osstest/logs
images: /home/osstest/images

Logs, config files, etc. are available at
    http://osstest.xs.citrite.net/~osstest/testlogs/logs

Test harness code can be found at
    http://xenbits.xensource.com/gitweb?p=osstest.git;a=summary


Push not applicable.

------------------------------------------------------------
commit c035e37335ae43229d7e68de74a65f2c01ebc0af
Author: Zhang Lubo <lubo.zhang@intel.com>
Date:   Thu Jan 5 14:58:05 2017 +0800

    SecurityPkg: enhance secure boot Config Dxe & Time Based AuthVariable.
    
    V3: code clean up
    
    prohibit Image SHA-1 hash option in SecureBootConfigDxe.
    Timebased Auth Variable driver should ensure AuthAlgorithm
    is SHA256 before further verification
    
    Contributed-under: TianoCore Contribution Agreement 1.0
    Signed-off-by: Zhang Lubo <lubo.zhang@intel.com>
    Cc: Chao Zhang <chao.b.zhang@intel.com>
    Cc: Long Qin <qin.long@intel.com>
    Cc: Yao Jiewen <jiewen.yao@intel.com>
    Reviewed-by: Chao Zhang <chao.b.zhang@intel.com>
    Reviewed-by: Long Qin <qin.long@intel.com>

commit 80e63e846af4ac135da5faccead7450e956d6462
Author: Zhang Lubo <lubo.zhang@intel.com>
Date:   Fri Feb 10 11:05:34 2017 +0800

    NetworkPkg:Generate the correct operational state of the interface.
    
    Currently, When there are more than 9 Ethernet ports available,
    'ifconfig6 -l' is not listing all the ports, only show the ports 0 to 9.
    
    Contributed-under: TianoCore Contribution Agreement 1.0
    Signed-off-by: Zhang Lubo <lubo.zhang@intel.com>
    Cc: Santhapur Naveen <naveens@amiindia.co.in>
    Cc: Ye Ting <ting.ye@intel.com>
    Cc: Fu Siyuan <siyuan.fu@intel.com>
    Cc: Wu Jiaxin <jiaxin.wu@intel.com>
    Reviewed-by: Ye Ting <ting.ye@intel.com>
    Reviewed-by: Wu Jiaxin <jiaxin.wu@intel.com>

commit 770e463d063ed50309274b88a2660289eb23a2f4
Author: Zhang Lubo <lubo.zhang@intel.com>
Date:   Fri Feb 10 10:47:39 2017 +0800

    MdeModulePkg:Generate the correct operational state of the interface.
    
    Currently, When there are more than 9 Ethernet ports available,
    'ifconfig -l' is not listing all the ports, only show the ports 0 to 9.
    
    Contributed-under: TianoCore Contribution Agreement 1.0
    Signed-off-by: Zhang Lubo <lubo.zhang@intel.com>
    Cc: Santhapur Naveen <naveens@amiindia.co.in>
    Cc: Ye Ting <ting.ye@intel.com>
    Cc: Fu Siyuan <siyuan.fu@intel.com>
    Cc: Wu Jiaxin <jiaxin.wu@intel.com>
    Reviewed-by: Ye Ting <ting.ye@intel.com>
    Reviewed-by: Wu Jiaxin <jiaxin.wu@intel.com>

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