From: Platform Team regression test user <citrix-osstest@xenproject.org>
To: xen-devel@lists.xensource.com, osstest-admin@xenproject.org
Subject: [ovmf baseline-only test] 71110: tolerable trouble: blocked/broken
Date: Mon, 27 Mar 2017 21:54:50 +0100 [thread overview]
Message-ID: <osstest-71110-mainreport@xen.org> (raw)
This run is configured for baseline tests only.
flight 71110 ovmf real [real]
http://osstest.xs.citrite.net/~osstest/testlogs/logs/71110/
Failures :-/ but no regressions.
Regressions which are regarded as allowable (not blocking):
build-amd64-pvops 3 host-install(3) broken baseline untested
build-amd64-xsm 3 host-install(3) broken baseline untested
build-amd64 3 host-install(3) broken baseline untested
build-i386-pvops 3 host-install(3) broken baseline untested
build-i386 3 host-install(3) broken baseline untested
build-i386-xsm 3 host-install(3) broken baseline untested
Tests which did not succeed, but are not blocking:
test-amd64-amd64-xl-qemuu-ovmf-amd64 1 build-check(1) blocked n/a
build-amd64-libvirt 1 build-check(1) blocked n/a
test-amd64-i386-xl-qemuu-ovmf-amd64 1 build-check(1) blocked n/a
build-i386-libvirt 1 build-check(1) blocked n/a
version targeted for testing:
ovmf 0b36d8fa73072382a4ad36e6c64d26f43cb81bc6
baseline version:
ovmf d590cce5cd9b9d31848eda4fcb62d1ab3fd05dfd
Last test of basis 71107 2017-03-27 05:57:58 Z 0 days
Testing same since 71110 2017-03-27 14:46:28 Z 0 days 1 attempts
------------------------------------------------------------
People who touched revisions under test:
Jeff Fan <jeff.fan@intel.com>
Ruiyu Ni <ruiyu.ni@intel.com>
jobs:
build-amd64-xsm broken
build-i386-xsm broken
build-amd64 broken
build-i386 broken
build-amd64-libvirt blocked
build-i386-libvirt blocked
build-amd64-pvops broken
build-i386-pvops broken
test-amd64-amd64-xl-qemuu-ovmf-amd64 blocked
test-amd64-i386-xl-qemuu-ovmf-amd64 blocked
------------------------------------------------------------
sg-report-flight on osstest.xs.citrite.net
logs: /home/osstest/logs
images: /home/osstest/images
Logs, config files, etc. are available at
http://osstest.xs.citrite.net/~osstest/testlogs/logs
Test harness code can be found at
http://xenbits.xensource.com/gitweb?p=osstest.git;a=summary
broken-step build-amd64-pvops host-install(3)
broken-step build-amd64-xsm host-install(3)
broken-step build-amd64 host-install(3)
broken-step build-i386-pvops host-install(3)
broken-step build-i386 host-install(3)
broken-step build-i386-xsm host-install(3)
Push not applicable.
------------------------------------------------------------
commit 0b36d8fa73072382a4ad36e6c64d26f43cb81bc6
Author: Jeff Fan <jeff.fan@intel.com>
Date: Thu Mar 23 15:19:43 2017 +0800
UefiCpuPkg/RegisterCpuFeaturesLib: Add ASSERT on allocated memory
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
commit 30b7a50bacee2a33cf9c708169f7c872a6ef00b2
Author: Jeff Fan <jeff.fan@intel.com>
Date: Thu Mar 23 13:19:49 2017 +0800
UefiCpuPkg/AcpiCpuData.h: Support >4GB MMIO address
The current CPU_REGISTER_TABLE_ENTRY structure only defined UINT32 Index to
indicate MSR/MMIO address. It's ok for MSR because MSR address is UINT32 type
actually. But for MMIO address, UINT32 limits MMIO address exceeds 4GB.
This update on CPU_REGISTER_TABLE_ENTRY is to add additional UINT32 field
HighIndex to indicate the high 32bit MMIO address and original Index still
indicate the low 32bit MMIO address.
This update makes use of original padding space between ValidBitLength and
Value to add HighIndex.
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
commit 98387f54ae7fcdc2badb90e39be0e9d8b37855c9
Author: Jeff Fan <jeff.fan@intel.com>
Date: Thu Mar 23 12:55:26 2017 +0800
UefiCpuPkg/RegisterCpuFeaturesLib: Define Index to UINT64
The input parameter Index of PreSmmCpuRegisterTableWrite() and
CpuRegisterTableWrite() is defined as UINT32. Index is MSR/MMIO address that
will be saved in CPU register table. UINT32 blocks the MMIO address > 4GB.
This fix is to define Index to UINT64 instead of UINT32.
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
commit 0027921b1be4b41a766c982615b4ed5a4868d318
Author: Ruiyu Ni <ruiyu.ni@intel.com>
Date: Tue Mar 21 13:47:08 2017 +0800
ShellPkg/mm: Support UINT16 segment number
It's to follow the Shell 2.2 spec.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Jaben Carsey <jaben.carsey@intel.com>
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