[ovmf baseline-only test] 72131: all pass

[ovmf baseline-only test] 72131: all pass

[Platform Team regression test user]

This run is configured for baseline tests only.

flight 72131 ovmf real [real]
http://osstest.xs.citrite.net/~osstest/testlogs/logs/72131/

Perfect :-)
All tests in this flight passed as required
version targeted for testing:
 ovmf                 70dc3ec5a72e0e3fc3ea8f63baecdeafd1110db8
baseline version:
 ovmf                 424a5ec33b3d5a842bff3f4695d0bd709c91a163

Last test of basis    72129  2017-09-19 23:49:40 Z    0 days
Testing same since    72131  2017-09-20 15:47:32 Z    0 days    1 attempts

------------------------------------------------------------
People who touched revisions under test:
  Jiewen Yao <jiewen.yao@intel.com>

jobs:
 build-amd64-xsm                                              pass    
 build-i386-xsm                                               pass    
 build-amd64                                                  pass    
 build-i386                                                   pass    
 build-amd64-libvirt                                          pass    
 build-i386-libvirt                                           pass    
 build-amd64-pvops                                            pass    
 build-i386-pvops                                             pass    
 test-amd64-amd64-xl-qemuu-ovmf-amd64                         pass    
 test-amd64-i386-xl-qemuu-ovmf-amd64                          pass    


------------------------------------------------------------
sg-report-flight on osstest.xs.citrite.net
logs: /home/osstest/logs
images: /home/osstest/images

Logs, config files, etc. are available at
    http://osstest.xs.citrite.net/~osstest/testlogs/logs

Test harness code can be found at
    http://xenbits.xensource.com/gitweb?p=osstest.git;a=summary


Push not applicable.

------------------------------------------------------------
commit 70dc3ec5a72e0e3fc3ea8f63baecdeafd1110db8
Author: Jiewen Yao <jiewen.yao@intel.com>
Date:   Fri Sep 15 12:30:20 2017 +0800

    IntelSiliconPkg/VTdInfoSample: Add RMRR table.
    
    Let system report RMRR table for the platform support
    PEI graphic.
    
    Cc: Star Zeng <star.zeng@intel.com>
    Contributed-under: TianoCore Contribution Agreement 1.1
    Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
    Reviewed-by: Star Zeng <star.zeng@intel.com>

commit 8e9da4ba3c4a4eeded7651f629330df3a9e5a780
Author: Jiewen Yao <jiewen.yao@intel.com>
Date:   Fri Sep 15 12:29:10 2017 +0800

    IntelSiliconPkg/IntelVTdPmrPei: Parse RMRR table.
    
    In order to support PEI graphic, we let VTdPmrPei driver
    parse DMAR table RMRR entry and allow the UMA access.
    
    If a system has no PEI IGD, no RMRR is needed. The behavior
    is unchanged.
    
    If a system has PEI IGD, it must report RMRR in PEI phase.
    The PeiVTdPrm will program the IGD VTd engine to skip the
    RMRR region, and program the rest PCI VTd engine to skip
    the another DMA buffer allocated in PEI phase for other
    device driver.
    
    Cc: Star Zeng <star.zeng@intel.com>
    Contributed-under: TianoCore Contribution Agreement 1.1
    Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
    Reviewed-by: Star Zeng <star.zeng@intel.com>

commit f02c531967785780ad14fbc8475d8322dfd0909b
Author: Jiewen Yao <jiewen.yao@intel.com>
Date:   Fri Sep 15 11:33:42 2017 +0800

    IntelSiliconPkg/VTdInfoPpi: Let it follow DMAR table.
    
    We notice that there is real usage in PEI to show
    the graphic out. As such we need report RMRR table
    in PEI to let VTdPmrPei driver skip the IGD UMA region.
    
    Now the VTD_INFO PPI uses the same DMAR data structure.
    
    Cc: Star Zeng <star.zeng@intel.com>
    Contributed-under: TianoCore Contribution Agreement 1.1
    Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
    Reviewed-by: Star Zeng <star.zeng@intel.com>

commit 83a457840e6f903f87c1fc32c71aec26e498d2ab
Author: Jiewen Yao <jiewen.yao@intel.com>
Date:   Wed Sep 20 14:39:32 2017 +0800

    MdePkg/include: Add Acpi.h to DMAR table.
    
    Suggested-by: Star Zeng <star.zeng@intel.com>
    Cc: Star Zeng <star.zeng@intel.com>
    Contributed-under: TianoCore Contribution Agreement 1.1
    Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
    Reviewed-by: Star Zeng <star.zeng@intel.com>

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