From: Platform Team regression test user <citrix-osstest@xenproject.org>
To: xen-devel@lists.xenproject.org, osstest-admin@xenproject.org
Subject: [ovmf baseline-only test] 75044: tolerable FAIL
Date: Fri, 3 Aug 2018 12:24:06 +0100 [thread overview]
Message-ID: <osstest-75044-mainreport@xen.org> (raw)
This run is configured for baseline tests only.
flight 75044 ovmf real [real]
http://osstest.xensource.com/osstest/logs/75044/
Failures :-/ but no regressions.
Tests which did not succeed, but are not blocking:
test-amd64-i386-xl-qemuu-ovmf-amd64 10 debian-hvm-install fail like 75043
test-amd64-amd64-xl-qemuu-ovmf-amd64 10 debian-hvm-install fail like 75043
version targeted for testing:
ovmf dd4cae4d82c7477273f3da455084844db5cca0c0
baseline version:
ovmf 1d802e234e813a6726f4c6fd161ae9bd146bc552
Last test of basis 75043 2018-08-03 07:20:34 Z 0 days
Testing same since 75044 2018-08-03 09:49:57 Z 0 days 1 attempts
------------------------------------------------------------
People who touched revisions under test:
Marcin Wojtas <mw@semihalf.com>
jobs:
build-amd64-xsm pass
build-i386-xsm pass
build-amd64 pass
build-i386 pass
build-amd64-libvirt pass
build-i386-libvirt pass
build-amd64-pvops pass
build-i386-pvops pass
test-amd64-amd64-xl-qemuu-ovmf-amd64 fail
test-amd64-i386-xl-qemuu-ovmf-amd64 fail
------------------------------------------------------------
sg-report-flight on osstest.xs.citrite.net
logs: /home/osstest/logs
images: /home/osstest/images
Logs, config files, etc. are available at
http://osstest.xensource.com/osstest/logs
Test harness code can be found at
http://xenbits.xensource.com/gitweb?p=osstest.git;a=summary
Push not applicable.
------------------------------------------------------------
commit dd4cae4d82c7477273f3da455084844db5cca0c0
Author: Marcin Wojtas <mw@semihalf.com>
Date: Thu Aug 2 22:50:54 2018 +0200
ArmPkg/GenericWatchdogDxe: Split 64bit register write to 2x32bit
According to the SBSA specification the Watchdog Compare
Register is split into two separate 32bit registers.
EDK2 code uses a single 64bit transaction to update
them, which can be problematic, depending on the SoC
implementation and could result in unpredictable behavior.
Fix this by modifying WatchdogWriteCompareRegister routine to
use two consecutive 32bit writes to the Watchdog Compare Register
Low and High, using new dedicated macros.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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