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From: Philippe Gerum <rpm@xenomai.org>
To: Tobias Schaffner <tobias.schaffner@siemens.com>
Cc: xenomai@lists.linux.dev
Subject: Re: [PATCH dovetail v4 10/12] riscv: add initial dovetail co-kernel skeleton
Date: Thu, 22 Jan 2026 20:56:47 +0100	[thread overview]
Message-ID: <87a4y5ifpc.fsf@xenomai.org> (raw)
In-Reply-To: <20260122102304.421957-11-tobias.schaffner@siemens.com> (Tobias Schaffner's message of "Thu, 22 Jan 2026 11:23:02 +0100")


This patch is specific to CONFIG_DOVETAIL=y, so this should go to
"riscv: dovetail: add core support".

Tobias Schaffner <tobias.schaffner@siemens.com> writes:

> Signed-off-by: Tobias Schaffner <tobias.schaffner@siemens.com>
> ---
>  arch/riscv/Kconfig                   |  2 ++
>  arch/riscv/include/asm/dovetail.h    | 23 +++++++++++++++++++++++
>  arch/riscv/include/asm/mmu_context.h |  4 ++++
>  arch/riscv/include/asm/syscall.h     |  6 ++++++
>  arch/riscv/include/asm/thread_info.h |  8 ++++++++
>  5 files changed, 43 insertions(+)
>  create mode 100644 arch/riscv/include/asm/dovetail.h
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index e93a0b6f9f2b..abec407aced5 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -149,6 +149,7 @@ config RISCV
>  	select HAVE_ARCH_USERFAULTFD_MINOR if 64BIT && USERFAULTFD
>  	select HAVE_ARCH_VMAP_STACK if MMU && 64BIT
>  	select HAVE_IRQ_PIPELINE
> +	select HAVE_DOVETAIL
>  	select HAVE_ASM_MODVERSIONS
>  	select HAVE_CONTEXT_TRACKING_USER
>  	select HAVE_DEBUG_KMEMLEAK
> @@ -377,6 +378,7 @@ config AS_HAS_OPTION_ARCH
>  
>  source "arch/riscv/Kconfig.socs"
>  source "arch/riscv/Kconfig.errata"
> +source "kernel/Kconfig.dovetail"
>  
>  menu "Platform type"
>  
> diff --git a/arch/riscv/include/asm/dovetail.h b/arch/riscv/include/asm/dovetail.h
> new file mode 100644
> index 000000000000..bb342e9eb18a
> --- /dev/null
> +++ b/arch/riscv/include/asm/dovetail.h
> @@ -0,0 +1,23 @@
> +/*
> +* SPDX-License-Identifier: GPL-2.0
> +*
> +* Copyright (C) 2024 Tobias Schaffner
> +*/
> +#ifndef _ASM_RISCV_DOVETAIL_H
> +#define _ASM_RISCV_DOVETAIL_H
> +
> +#if !defined(__ASSEMBLY__)
> +#ifdef CONFIG_DOVETAIL
> +
> +static inline void arch_dovetail_exec_prepare(void)
> +{ }
> +
> +static inline void arch_dovetail_switch_prepare(bool leave_inband)
> +{ }
> +
> +static inline void arch_dovetail_switch_finish(bool enter_inband)
> +{ }
> +
> +#endif /* CONFIG_DOVETAIL */
> +#endif /* !__ASSEMBLY__ */
> +#endif /* _ASM_RISCV_DOVETAIL_H */
> diff --git a/arch/riscv/include/asm/mmu_context.h b/arch/riscv/include/asm/mmu_context.h
> index 8c4bc49a3a0f..444136d7b253 100644
> --- a/arch/riscv/include/asm/mmu_context.h
> +++ b/arch/riscv/include/asm/mmu_context.h
> @@ -38,6 +38,10 @@ static inline int init_new_context(struct task_struct *tsk,
>  	return 0;
>  }
>  
> +static inline void
> +switch_oob_mm(struct mm_struct *prev, struct mm_struct *next,
> +	      struct task_struct *tsk) { }
> +
>  DECLARE_STATIC_KEY_FALSE(use_asid_allocator);
>  
>  #ifdef CONFIG_RISCV_ISA_SUPM
> diff --git a/arch/riscv/include/asm/syscall.h b/arch/riscv/include/asm/syscall.h
> index 34313387f977..6ae989aafbcd 100644
> --- a/arch/riscv/include/asm/syscall.h
> +++ b/arch/riscv/include/asm/syscall.h
> @@ -117,6 +117,12 @@ static inline bool arch_syscall_is_vdso_sigreturn(struct pt_regs *regs)
>  	return false;
>  }
>  
> +static inline unsigned long syscall_get_arg0(struct task_struct *task,
> +					     struct pt_regs *regs)
> +{
> +	return regs->orig_a0;
> +}
> +
>  asmlinkage long sys_riscv_flush_icache(uintptr_t, uintptr_t, uintptr_t);
>  
>  asmlinkage long sys_riscv_hwprobe(struct riscv_hwprobe *, size_t, size_t,
> diff --git a/arch/riscv/include/asm/thread_info.h b/arch/riscv/include/asm/thread_info.h
> index 9e4c9b884b5a..6c40e29f6445 100644
> --- a/arch/riscv/include/asm/thread_info.h
> +++ b/arch/riscv/include/asm/thread_info.h
> @@ -41,6 +41,7 @@
>  
>  #include <asm/processor.h>
>  #include <asm/csr.h>
> +#include <dovetail/thread_info.h>
>  
>  /*
>   * low level task data that entry.S needs immediate access to
> @@ -77,6 +78,7 @@ struct thread_info {
>  	 */
>  	unsigned long		a0, a1, a2;
>  #endif
> +	struct oob_thread_state oob_state;      /* co-kernel thread state */
>  };
>  
>  #ifdef CONFIG_SHADOW_CALL_STACK
> @@ -120,6 +122,9 @@ int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src);
>  
>  #include <asm-generic/thread_info_tif.h>
>  
> +#define TIF_MAYDAY			14      /* emergency trap pending */
> +#define _TIF_MAYDAY			(1 << TIF_MAYDAY)
> +
>  #define TIF_32BIT			16	/* compat-mode 32bit process */
>  #define TIF_RISCV_V_DEFER_RESTORE	17	/* restore Vector before returing to user */
>  
> @@ -129,5 +134,8 @@ int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src);
>   * Local (synchronous) thread flags.
>   */
>  #define _TLF_OOB		0x0001
> +#define _TLF_DOVETAIL		0x0002
> +#define _TLF_OFFSTAGE		0x0004
> +#define _TLF_OOBTRAP		0x0008
>  
>  #endif /* _ASM_RISCV_THREAD_INFO_H */

-- 
Philippe.

  reply	other threads:[~2026-01-22 19:56 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-01-22 10:22 [PATCH dovetail v4 00/12] riscv: Add dovetail support Tobias Schaffner
2026-01-22 10:22 ` [PATCH dovetail v4 01/12] riscv: irq_pipeline: add IRQ pipelining core Tobias Schaffner
2026-01-22 19:35   ` Philippe Gerum
2026-01-22 10:22 ` [PATCH dovetail v4 02/12] riscv: irq_pipeline: fix irq stack handling Tobias Schaffner
2026-01-22 19:55   ` Philippe Gerum
2026-01-22 10:22 ` [PATCH dovetail v4 03/12] riscv: irq_pipeline: synchronize IRQs on exit to user mode Tobias Schaffner
2026-01-22 10:22 ` [PATCH dovetail v4 04/12] irqchip/riscv-aplic-direct: enable pipelined interrupt control Tobias Schaffner
2026-01-22 10:22 ` [PATCH dovetail v4 05/12] irqchip/irq-riscv-aplic-msi: " Tobias Schaffner
2026-01-22 10:22 ` [PATCH dovetail v4 06/12] irqchip/irq-riscv-imsic-platform: " Tobias Schaffner
2026-01-22 10:22 ` [PATCH dovetail v4 07/12] irqchip/irq-riscv-intc: " Tobias Schaffner
2026-01-22 10:23 ` [PATCH dovetail v4 08/12] irqchip/irq-sifive-plic: " Tobias Schaffner
2026-01-22 10:23 ` [PATCH dovetail v4 09/12] clocksource/timer-riscv: irq_pipeline: enable pipelined clock events Tobias Schaffner
2026-01-22 10:23 ` [PATCH dovetail v4 10/12] riscv: add initial dovetail co-kernel skeleton Tobias Schaffner
2026-01-22 19:56   ` Philippe Gerum [this message]
2026-01-22 10:23 ` [PATCH dovetail v4 11/12] riscv: add out-of-band aware trap handling Tobias Schaffner
2026-01-22 19:57   ` Philippe Gerum
2026-01-22 10:23 ` [PATCH dovetail v4 12/12] riscv: add dovetail-aware memory management Tobias Schaffner
2026-01-22 11:05 ` [PATCH dovetail v4 00/12] riscv: Add dovetail support Florian Bezdeka
2026-01-22 11:48   ` Tobias Schaffner

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