From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from relay6-d.mail.gandi.net (relay6-d.mail.gandi.net [217.70.183.198]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4AA2831064E for ; Tue, 17 Feb 2026 09:40:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.198 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771321251; cv=none; b=tx8+mZBUjs1Cm+ed9r34KdtHTi4xdk5ZAg9E3BjSTTAcHFRe6KEMsnt6RgJ4cSdgQjMrQZM9iZ9wmFzLjP8Bh7Obu/JlBhWoILlqlh+nvh8rTz3YUSo3H8/zc8bKMIKYXYX/Abdn+fBNdb8kExCwYLgRqjbtHyIN6PRfSOw7UGM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771321251; c=relaxed/simple; bh=fluKgCgOh35oVDxKRSb6yT95RE1lcJLWlHh1IwzIV5Q=; h=From:To:Cc:Subject:In-Reply-To:References:Date:Message-ID: MIME-Version:Content-Type; b=nLtxyVIUBytgVbDUk5wZaetcjmOJv+Qx5GbR3M8sBIcTeqNVaxYMu9sFma41N+uENnAR7F17VkmX1of/38Lxk/m2NDM1JLDfod0hbIpVPoKL9Fnd14DT0omfFODRHfGuedgNkkLQQb6tkUaI+lLMCZAyhqgvMdJoug0TCh69G+Y= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=xenomai.org; spf=pass smtp.mailfrom=xenomai.org; dkim=pass (2048-bit key) header.d=xenomai.org header.i=@xenomai.org header.b=fVeXmDcn; arc=none smtp.client-ip=217.70.183.198 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=xenomai.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=xenomai.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=xenomai.org header.i=@xenomai.org header.b="fVeXmDcn" Received: by mail.gandi.net (Postfix) with ESMTPSA id 7720041C7B; Tue, 17 Feb 2026 09:40:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=xenomai.org; s=gm1; t=1771321247; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=qOxCDSj/7W1D9YRP0Fn1wdGsZ93XVlHNvKXkp7r+UYc=; b=fVeXmDcnwHU4kC2NcgG9N/Zhjh2U6RVrneL/O4qnZcXQK5+U2jPj4/Pu7gIjW19zxpiYBg CdkB9q+1poU4yM7p2DRVviWJq7qqsLt1M4P9Wa/c6hh0R+efFpYMkJB3IbHi342jboIPfn z+qur8mp5N4niNW+wCIGfHm4wMl7kNf1CCJHGLEAHzd14PBmKckbfRAosbVsIWxfl25I/D YGl02v/SzPnD0JxVYn8KXVHRqIIfMpCbGJDXglZpWPNdIniXTsA5NXrTKgnF0+idFsx/KO kGpm88vCfVZgpfwYHRWqNPCEEWRocCW+eJKMN3tcq0B9yg8Z4Kh58e3aBIlStQ== From: Philippe Gerum To: Florian Bezdeka Cc: Xenomai , Jan Kiszka Subject: Re: [PATCH Dovetail 2/2] arm64: irq_pipeline: Fix the demotion checks for el0 and el1 IRQs In-Reply-To: <430245ce2bc8da023235e9cf1312f729d7c57494.camel@siemens.com> (Florian Bezdeka's message of "Tue, 17 Feb 2026 10:16:21 +0100") References: <20260216-wip-flo-v6-19-dovetail-rebase-v1-0-5c36863cba17@siemens.com> <20260216-wip-flo-v6-19-dovetail-rebase-v1-2-5c36863cba17@siemens.com> <87jywbajfy.fsf@xenomai.org> <505e35212b6655e0cb65e9fbc418c1171a9c916e.camel@siemens.com> <9e12c4a73df2d24dd1b39ab196b0112cb4e7e6ef.camel@siemens.com> <87ecmjahk3.fsf@xenomai.org> <430245ce2bc8da023235e9cf1312f729d7c57494.camel@siemens.com> User-Agent: mu4e 1.12.12; emacs 30.2 Date: Tue, 17 Feb 2026 10:40:46 +0100 Message-ID: <87tsvf9081.fsf@xenomai.org> Precedence: bulk X-Mailing-List: xenomai@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain X-GND-Sasl: rpm@xenomai.org X-GND-State: clean X-GND-Score: -100 X-GND-Cause: gggruggvucftvghtrhhoucdtuddrgeefgedrtddtgddvudelgeefucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuifetpfffkfdpucggtfgfnhhsuhgsshgtrhhisggvnecuuegrihhlohhuthemuceftddunecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenucfjughrpefhvfevufgjfhgffffkgggtsehttdertddtredtnecuhfhrohhmpefrhhhilhhiphhpvgcuifgvrhhumhcuoehrphhmseigvghnohhmrghirdhorhhgqeenucggtffrrghtthgvrhhnpedvlefhvdehkeduheevleegiedtueejgfekhfeijeefvdeijeekgeeigfejhfekgeenucfkphepvdgrtddumegvtdgrmedulegsmeeftggutdemleeklegrmeehtgegsgemsgejfhhfmegsrghfnecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehinhgvthepvdgrtddumegvtdgrmedulegsmeeftggutdemleeklegrmeehtgegsgemsgejfhhfmegsrghfpdhhvghlohepphihrhhopdhmrghilhhfrhhomheprhhpmhesgigvnhhomhgrihdrohhrghdpqhhiugepjeejvddttdegudevjeeupdhmohguvgepshhmthhpohhuthdpnhgspghrtghpthhtohepfedprhgtphhtthhopehjrghnrdhkihhsiihkrgesshhivghmvghnshdrtghomhdprhgtphhtthhopeigvghnohhmrghisehlihhsthhsrdhlihhnuhigrdguvghvpdhrtghpthhtohepfhhlohhrihgrnhdrsggviiguvghkrgesshhivghmvghnshdrtghomh Florian Bezdeka writes: > On Tue, 2026-02-17 at 09:41 +0100, Philippe Gerum wrote: >> > Comparing with x86 again, I think that my proposal is "correct" in terms >> > of identical to what x86 does. Do all architectures have a gap here? >> >> x86 has a single implementation for both user and kernel preemption >> paths, arm64 has two since the privilege level is explicitly stated by >> the irq handler being called, but this still must translate identically >> logically speaking. Your implementation is missing the kernel preemption >> path after demotion. >> >> i.e. when checking for running_oob() || irqs_disabled(), the cases >> covered are: >> >> (1) in-band user path on entry (implies !irqs_disabled()) >> (2) oob user path on entry (might be demoted) >> (3) (virtually) stalled in-band kernel path on entry (implies no reschedule, >> filtered out by irqentry_exit()) >> (4) oob kernel path on entry (might be demoted) >> >> Therefore, with your patch in, el1 is now missing (4). > > Right, but I'm wondering if x86 ignores this case as well. > > After demotion of a oob kernel path entry, user_mode() should still be > false - bypassing the call to irqentry_exit_to_user_mode() - No? Yes, x86 assumes that a kernel path demoted to in-band is going to cross an IRQ synchronization point shortly after on return to the preempted context. Now, with hindsight, the question is: are we 100% certain of that? Any real (hw) IRQ over the in-band stage would trigger the synchronization as expected, but a synthetic one posted from the oob stage might linger if this assumption ends up being wrong. I need to have a second look at this code. -- Philippe.