NAND flash

NAND flash

[nagaraj trivedi]

Hello,
   can I use the MTD NAND FLASH driver for smartmedia along with the jffs2? Does jffs2 work with the MTD NAND flash driver ?

 

NAND flash

[nagaraj trivedi]

Hello,
   can I use the MTD NAND FLASH driver for smartmedia along with the jffs2? Does jffs2 work with the MTD NAND flash driver ?

 

Re: NAND flash

[Steven J. Hill]

nagaraj trivedi wrote:
> 
> can I use the MTD NAND FLASH driver for smartmedia along with the jffs2? Does jffs2
> work with the MTD NAND flash driver ?
>
OK...let's break this into small pieces. First of all, the NAND FLASH driver was
written for raw NAND flash chips that were IO mapped into the address space. I
wrote
those drivers originally. Next, I got JFFS working on top of the NAND MTD driver
to the point that it could mount, read, write, delete, remove directories, etc.
I
and another person also did a fair amount of stress testing. That is where
things
currently stand.

SmartMedia is an entirely different beast in that has a some hardware between
the
CPU and the NAND flash chips inside. It is similar to Disk-On-Chip devices which
use NAND/NOR flash with wear-leveling, error correcting and other things done
transparently in the hardware. You would need to get the low-level
specifications
for SmartMedia and then write a SmartMedia driver. Once that is done, you could
then
work on the task of getting JFFS2 working. IIRC though, JFFS2 needs
modifications
to work with NAND flash. Myself and David could work out what changes need to be
in
fairly short order. Hope that helps.

-Steve

-- 
 Steven J. Hill - Embedded SW Engineer

NAND flash

[Larry Doolittle]

Steven J. Hill wrote:
> First of all, the NAND FLASH driver was written for raw NAND flash
> chips that were IO mapped into the address space.
> ...
> SmartMedia is an entirely different beast in that has a some hardware
> between the CPU and the NAND flash chips inside. It is similar to
> Disk-On-Chip devices which use NAND/NOR flash with wear-leveling,
> error correcting and other things done transparently in the hardware.

I think you should double check that assertion.  My understanding is
that the "Smart" in the name is a bug.  These are actually NAND chips,
consumer-grade packaged, standardized, and marketed, with no smarts at
all.  So you _could_ use the nand.c driver, with the right interface-
specific wrapper layer to get at the device.

Unfortunately, the result would not be content-compatible with other
SmartMedia users, because SmartMedia also has a standard for encoding
blocks on the nand chips.  I tried to read that standard, but the PDF
file is encrypted in a way that is incompatible with xpdf-0.92.  The
URL for that reference material has been posted here before, it's
 http://www.ssfdc.or.jp/spec/english/

      - Larry

Re: NAND flash

[David Woodhouse]

ldoolitt@recycle.lbl.gov said:
>  I think you should double check that assertion.  My understanding is
> that the "Smart" in the name is a bug.  These are actually NAND chips,
> consumer-grade packaged, standardized, and marketed, with no smarts at
> all.  So you _could_ use the nand.c driver, with the right interface-
> specific wrapper layer to get at the device.

Correct, with the proviso that some SmartMedia 'adapters' have 
microcontrollers built in, and the host can't actually _get_ at the raw 
flash.

> Unfortunately, the result would not be content-compatible with other
> SmartMedia users, because SmartMedia also has a standard for encoding
> blocks on the nand chips.  I tried to read that standard, but the PDF
> file is encrypted in a way that is incompatible with xpdf-0.92.  The
> URL for that reference material has been posted here before, it's
>  http://www.ssfdc.or.jp/spec/english/

Acroread can manage it. It all looks fairly simple to implement.

--
dwmw2

NAND FLASH

[Steve Tsai]

Hi,
I try to use nand flash driver to my board, but it seems fail to do some
operations. I just can get chip ID, but I can not read data or program
data. I use GPIO to control CLE and ALE and connect WE, RE and CE to
procesor. Is it right? Does anyone have sample code to test NAND flash?
Thank.

Steve TSai

Re: NAND FLASH

[Thomas Gleixner]

On Friday, 21. June 2002 11:44, Steve Tsai wrote:
> Hi,
> I try to use nand flash driver to my board, but it seems fail to do some
> operations. I just can get chip ID, but I can not read data or program
> data. I use GPIO to control CLE and ALE and connect WE, RE and CE to
> procesor. Is it right? Does anyone have sample code to test NAND flash?
1. CE should be a static signal 
2. please read http://www.linux-mtd.infradead.org/tech/nand.html 
3. Use the latest code from mtd-cvs
4. Read one of the board specific nand drivers to setup your own

-- 
Thomas
___________________________________
autronix automation GmbH
http://www.autronix.de gleixner@autronix.de

RE: NAND FLASH

[Steve Tsai]

Do I use GPIO to control CE? Because I use memory-map-io to connnect to
nand flash, if CE can not use to address the chip, I have to use other
design to address the flash chip. Thanks.

Steve Tsai

> Hi,
> I try to use nand flash driver to my board, but it seems fail to do 
> some operations. I just can get chip ID, but I can not read data or 
> program data. I use GPIO to control CLE and ALE and connect WE, RE and

> CE to procesor. Is it right? Does anyone have sample code to test NAND

> flash?
1. CE should be a static signal 
2. please read http://www.linux-mtd.infradead.org/tech/nand.html 
3. Use the latest code from mtd-cvs
4. Read one of the board specific nand drivers to setup your own

Re: NAND FLASH

[Thomas Gleixner]

On Friday, 21. June 2002 19:07, Steve Tsai wrote:
> Do I use GPIO to control CE? Because I use memory-map-io to connnect to
> nand flash, if CE can not use to address the chip, I have to use other
> design to address the flash chip. Thanks.
Yep you statically apply CE. Then the processing is done, then CE is released.
That's the way, how nand.c handles this. And it handles it correct.

> 1. CE should be a static signal
> 2. please read http://www.linux-mtd.infradead.org/tech/nand.html
> 3. Use the latest code from mtd-cvs
> 4. Read one of the board specific nand drivers to setup your own

-- 
Thomas
________________________________
Thomas Gleixner - autronix automation
http://www.autronix.de gleixner@autronix.de

NAND flash

[Eugeny Mints]

Hello,

Could anybody help me to solve such a problem with JFFS2 and NAND flash:
- the NAND flash Toshiba TC58256AFTI
- kernel 2.4.22 with latest MTD and JFFS2 
- handy-written miniport for the paticular flash chip

The device works OK almost in any case, but when I try to execute  while
true; do dd if=/dev/zero of=/dev/mnt/foo count=1000; done after 10-15
minutes the system hangs; I cannot login from console or via telnet, but
it is still ping'able. I tried to use YAFFS, perform dd to device itself
instead of file on the filesystem on top of flash - no hangs were
observed.

Could anybody help me, please? 
--
cheers, dmitry pervushin

Re: NAND flash

[David Woodhouse]

On Thu, 2003-10-09 at 19:04 +0400, Eugeny Mints wrote:
> Hello,
> 
> Could anybody help me to solve such a problem with JFFS2 and NAND flash:
> - the NAND flash Toshiba TC58256AFTI
> - kernel 2.4.22 with latest MTD and JFFS2 
> - handy-written miniport for the paticular flash chip

When you say 'latest' do you really mean that? NAND flash support in
JFFS2 has changed a _lot_ in the last weeks, and even in the last few
days.

> The device works OK almost in any case, but when I try to execute  while
> true; do dd if=/dev/zero of=/dev/mnt/foo count=1000; done after 10-15
> minutes the system hangs; I cannot login from console or via telnet, but
> it is still ping'able. I tried to use YAFFS, perform dd to device itself
> instead of file on the filesystem on top of flash - no hangs were
> observed.

Use SysRq-P and/or SysRq-T to see where the kernel is stuck. IF that
doesn't work, enable CONFIG_JFFS2_FS_DEBUG=1 and 
echo > /proc/sys/kernel/printk then watch the console, and see what the
last thing it says is.

-- 
dwmw2

RE: NAND flash

[Stephan Linke]

Hi Eugeny,

maybe some problem with the flash "ready" detection?

Stephan

> -----Original Message-----
> From: linux-mtd-bounces@lists.infradead.org
> [mailto:linux-mtd-bounces@lists.infradead.org]On Behalf Of Eugeny Mints
> Sent: Donnerstag, 9. Oktober 2003 17:04
> To: linux-mtd@lists.infradead.org
> Cc: Dmitry Pervushin
> Subject: NAND flash
> 
> 
> Hello,
> 
> Could anybody help me to solve such a problem with JFFS2 and NAND flash:
> - the NAND flash Toshiba TC58256AFTI
> - kernel 2.4.22 with latest MTD and JFFS2 
> - handy-written miniport for the paticular flash chip
> 
> The device works OK almost in any case, but when I try to execute  while
> true; do dd if=/dev/zero of=/dev/mnt/foo count=1000; done after 10-15
> minutes the system hangs; I cannot login from console or via telnet, but
> it is still ping'able. I tried to use YAFFS, perform dd to device itself
> instead of file on the filesystem on top of flash - no hangs were
> observed.
> 
> Could anybody help me, please? 
> --
> cheers, dmitry pervushin
> 
> 
> ______________________________________________________
> Linux MTD discussion mailing list
> http://lists.infradead.org/mailman/listinfo/linux-mtd/
> 
> 

Re: NAND flash

[Charles Manning]

On Friday 10 October 2003 04:21, Stephan Linke wrote:
> Hi Eugeny,
>
> maybe some problem with the flash "ready" detection?

I do not think so since this is working fine with YAFFS which makes the same 
mtd calls as JFFS2.

Try using the newly announced JFFS2 stuff - that likely addresses some of the 
issues in previous JFFS2 releases.

-- Charles

>
> Stephan
>
> > -----Original Message-----
> > From: linux-mtd-bounces@lists.infradead.org
> > [mailto:linux-mtd-bounces@lists.infradead.org]On Behalf Of Eugeny Mints
> > Sent: Donnerstag, 9. Oktober 2003 17:04
> > To: linux-mtd@lists.infradead.org
> > Cc: Dmitry Pervushin
> > Subject: NAND flash
> >
> >
> > Hello,
> >
> > Could anybody help me to solve such a problem with JFFS2 and NAND flash:
> > - the NAND flash Toshiba TC58256AFTI
> > - kernel 2.4.22 with latest MTD and JFFS2
> > - handy-written miniport for the paticular flash chip
> >
> > The device works OK almost in any case, but when I try to execute  while
> > true; do dd if=/dev/zero of=/dev/mnt/foo count=1000; done after 10-15
> > minutes the system hangs; I cannot login from console or via telnet, but
> > it is still ping'able. I tried to use YAFFS, perform dd to device itself
> > instead of file on the filesystem on top of flash - no hangs were
> > observed.
> >
> > Could anybody help me, please?
> > --
> > cheers, dmitry pervushin
> >
> >
> > ______________________________________________________
> > Linux MTD discussion mailing list
> > http://lists.infradead.org/mailman/listinfo/linux-mtd/
>
> ______________________________________________________
> Linux MTD discussion mailing list
> http://lists.infradead.org/mailman/listinfo/linux-mtd/

NAND flash

[Vanalme Filip]

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Hi,

On our own i.MX27 based boards, we have Micron NAND flash memory (MT29F2G08ABBEAH4). Besides the BI-swapping problem for 2K NAND flashes, I can see that this chip needs an initial reset command before it becomes operational. This is something that has to be done in the early boot code, so before loading the first page of bootloader code (the reset should be sent before the first page of code can be read from flash).
From Freescale doc, I found that we have to blow certain fuses to make the i.MX27 boot from internal ROM. According to the document, the ROM code takes care about the initial reset before loading the first page of code from the NAND flash.
I'm however a little concerned about this figure in the document :

[cid:image002.png@01CBE7E3.B1A2CCA0]

If I understand well, this should be the structure of the 2K NFC buffer when booting from internal ROM. I don't think this will be the structure when loading the first page of Barebox code, correct ?
Anyone familiar with this Micron specific flash problem ? And the consequences for Barebox ? Do we have to make modifications in the Barebox code to tackle this ?

(because the Freescale document is rather WinCE related, I'm not sure this also applies to Barebox/Linux based systems...)

I hope we didn't make a bad choice of NAND flash in combination with i.MX27... ? ;-)


Best Regards,

Filip


(Btw : anyone can tell me what CSF and DCD stand for... ? Did not find any explanations in the i.MX27 reference manual yet)

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Re: NAND flash

[Eric Bénard]

Hi,

On 21/03/2011 16:19, Vanalme Filip wrote:
> On our own i.MX27 based boards, we have Micron NAND flash memory
> (MT29F2G08ABBEAH4). Besides the BI-swapping problem for 2K NAND flashes, I can
> see that this chip needs an initial reset command before it becomes
> operational. This is something that has to be done in the early boot code, so
> before loading the first page of bootloader code (the reset should be sent
> before the first page of code can be read from flash).
>
>  From Freescale doc, I found that we have to blow certain fuses to make the
> i.MX27 boot from internal ROM. According to the document, the ROM code takes
> care about the initial reset before loading the first page of code from the
> NAND flash.
>
> I’m however a little concerned about this figure in the document :
>
> If I understand well, this should be the structure of the 2K NFC buffer when
> booting from internal ROM. I don’t think this will be the structure when
> loading the first page of Barebox code, correct ?
>
> Anyone familiar with this Micron specific flash problem ? And the consequences
> for Barebox ? Do we have to make modifications in the Barebox code to tackle
> this ?
>
> (because the Freescale document is rather WinCE related, I’m not sure this
> also applies to Barebox/Linux based systems…)
>
> I hope we didn’t make a bad choice of NAND flash in combination with i.MX27… ? ;-)
>
this may be the case as unless this has changed recently, flash requiring a 
reset command can't be used on i.MX27 for nand boot without extra logic as the 
internal bootrom doesn't send this reset command.

Eric

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RE: NAND flash

[Vanalme Filip]

> -----Original Message-----
> From: Eric Bénard [mailto:eric@eukrea.com]
> Sent: maandag 21 maart 2011 17:11
> To: Vanalme Filip
> Cc: barebox@lists.infradead.org
> Subject: Re: NAND flash
> 
> Hi,
> 
> On 21/03/2011 16:19, Vanalme Filip wrote:
> > On our own i.MX27 based boards, we have Micron NAND flash memory
> > (MT29F2G08ABBEAH4). Besides the BI-swapping problem for 2K NAND
> flashes, I can
> > see that this chip needs an initial reset command before it becomes
> > operational. This is something that has to be done in the early boot code, so
> > before loading the first page of bootloader code (the reset should be sent
> > before the first page of code can be read from flash).
> >
> >  From Freescale doc, I found that we have to blow certain fuses to make the
> > i.MX27 boot from internal ROM. According to the document, the ROM code takes
> > care about the initial reset before loading the first page of code from the
> > NAND flash.
> >
> > I’m however a little concerned about this figure in the document :
> >
> > If I understand well, this should be the structure of the 2K NFC buffer when
> > booting from internal ROM. I don’t think this will be the structure when
> > loading the first page of Barebox code, correct ?
> >
> > Anyone familiar with this Micron specific flash problem ? And the consequences
> > for Barebox ? Do we have to make modifications in the Barebox code to tackle
> > this ?
> >
> > (because the Freescale document is rather WinCE related, I’m not sure this
> > also applies to Barebox/Linux based systems…)
> >
> > I hope we didn’t make a bad choice of NAND flash in combination with i.MX27…
> ? ;-)
> >
> this may be the case as unless this has changed recently, flash requiring a
> reset command can't be used on i.MX27 for nand boot without extra logic as the
> internal bootrom doesn't send this reset command.
> 
> Eric
[Filip]  Hi Eric,

Are you sure about this ?
This is a fragment from a Freescale application note on NAND flashes (draft version however...).

(there's a flowchart just above this explanation - I removed it because I think it's not that important for now)

"The red dash line is the nand flash internal boot codes routine. There will be some important check points:
1:If BOOT_INT fuse is 0x1, The internal boot will be enabled.
2:If IROM_SUPPORT_EN fuse is 0x1, The ROM codes will be enabled.
3:ROM codes will read GPCR register to check the boot pin settings.
4:ROM codes will enable the Nand flash support, and get the Nand flash IO bus width by the value from boot pin settings.
5:ROM codes will read ADD_CYCLE[1:0] to get the right Nand flash access cycle.
6:ROM codes will send Nand flash reset command to Nand flash.
   Note: Micron flash(and the same alliance Nand flash manufacture need the reset command before operation the flash, Our external will not send out the command, Enable internal boot will enable this type of flash)
7:ROM codes will read the first 2K page datum from flash to Nand flash controller buffer(Address 0xd8000000).
8:ROM codes will check the CSF/DCD segment, but if the chipset HAB type is engineer version, It will just log the error message and jump to load address directly, Please check details in the follow section."

Remark item 6...

Fragment from another Freescale doc : 

"►Option 1: Connect POR_B reset signal to NAND_Init
• Only available on NAND Flash devices that have the NAND_Init pin.
►Option 2: Use Internal Boot Mode
• Requires eFuses to be programmed to enable Internal Boot Mode,
select NAND Flash address cycles and iROM support enable.
• Add NAND Flash Header to NAND to support iROM Boot.
►Option 3: Double POR_B reset to i.MX27
• Initial POR_B will generate a hidden Reset in the NAND Flash when
i.MX27 performs initial NAND Flash read cycle.
• Reassert then deassert POR_B to re-generate the initial NAND Flash
read cycle.
• Hidden NAND Flash reset will NOT occur since power was not removed
from the NAND Flash.
• Small uC can be used to generate the timing."

See option 2...

At the moment, we are working on i.MX27PDK boards. I just checked the version id : 2. Title of the application note : "iMx27 TO2 Internal Boot". So, I guess this is intended for our version.

If I'm right, your company is also manufacturer of i.MX27 based boards. Therefore, I tend to rely on your experience with that processor. Moreover, the application note is still a "draft" version... On the other hand, Freescale confirmed that we could use that kind of Micron NAND flashes without any problem. They even reviewed our own board design and made no remarks with respect to the NAND flash (no remarks on adding extra logic to support that type of NAND)...
This is a very confusing situation and it might result in a redesign of our board... 

Other forum members with i.MX27/Micron NAND experience ?
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Re: NAND flash

[Eric Bénard]

Hi Filip,

On 22/03/2011 09:41, Vanalme Filip wrote:
> Are you sure about this ?
> This is a fragment from a Freescale application note on NAND flashes (draft version however...).
>
> (there's a flowchart just above this explanation - I removed it because I think it's not that important for now)
>
> "The red dash line is the nand flash internal boot codes routine. There will be some important check points:
> 1:If BOOT_INT fuse is 0x1, The internal boot will be enabled.
> 2:If IROM_SUPPORT_EN fuse is 0x1, The ROM codes will be enabled.
> 3:ROM codes will read GPCR register to check the boot pin settings.
> 4:ROM codes will enable the Nand flash support, and get the Nand flash IO bus width by the value from boot pin settings.
> 5:ROM codes will read ADD_CYCLE[1:0] to get the right Nand flash access cycle.
> 6:ROM codes will send Nand flash reset command to Nand flash.
>     Note: Micron flash(and the same alliance Nand flash manufacture need the reset command before operation the flash, Our external will not send out the command, Enable internal boot will enable this type of flash)
> 7:ROM codes will read the first 2K page datum from flash to Nand flash controller buffer(Address 0xd8000000).
> 8:ROM codes will check the CSF/DCD segment, but if the chipset HAB type is engineer version, It will just log the error message and jump to load address directly, Please check details in the follow section."
>
> Remark item 6...
>
yes I also saw this document, but Freescale told us several times that nand 
boot on Micron flash is not working so I didn't investigate more as we have 
NOR boot as a default on this platform ... and have switched to i.MX25 & 35 
for new applications.

> Fragment from another Freescale doc :
>
> "►Option 1: Connect POR_B reset signal to NAND_Init
> • Only available on NAND Flash devices that have the NAND_Init pin.
> ►Option 2: Use Internal Boot Mode
> • Requires eFuses to be programmed to enable Internal Boot Mode,
> select NAND Flash address cycles and iROM support enable.
> • Add NAND Flash Header to NAND to support iROM Boot.
> ►Option 3: Double POR_B reset to i.MX27
> • Initial POR_B will generate a hidden Reset in the NAND Flash when
> i.MX27 performs initial NAND Flash read cycle.
> • Reassert then deassert POR_B to re-generate the initial NAND Flash
> read cycle.
> • Hidden NAND Flash reset will NOT occur since power was not removed
> from the NAND Flash.
> • Small uC can be used to generate the timing."
>
> See option 2...
>
> At the moment, we are working on i.MX27PDK boards. I just checked the version id : 2. Title of the application note : "iMx27 TO2 Internal Boot". So, I guess this is intended for our version.
>
> If I'm right, your company is also manufacturer of i.MX27 based boards. Therefore, I tend to rely on your experience with that processor. Moreover, the application note is still a "draft" version... On the other hand, Freescale confirmed that we could use that kind of Micron NAND flashes without any problem. They even reviewed our own board design and made no remarks with respect to the NAND flash (no remarks on adding extra logic to support that type of NAND)...
> This is a very confusing situation and it might result in a redesign of our board...
>
I've not worked enough on nand boot on i.MX27 to provide more feedback but FSL 
& Micron recommended us the workaround implying a double POR for nand boot.

The problem is that sometime workaround sent by support that are not even 
tested and sometime there are things in the documentation which are also not 
tested or even not present in the CPU so it's difficult to know where is the 
truth without spending time on this problem ...

Eric

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RE: NAND flash

[Vanalme Filip]

> -----Original Message-----
> From: Eric Bénard [mailto:eric@eukrea.com]
> Sent: dinsdag 22 maart 2011 10:05
> To: Vanalme Filip
> Cc: barebox@lists.infradead.org
> Subject: Re: NAND flash
> 
> Hi Filip,
> 
> On 22/03/2011 09:41, Vanalme Filip wrote:
> > Are you sure about this ?
> > This is a fragment from a Freescale application note on NAND flashes (draft
> version however...).
> >
> > (there's a flowchart just above this explanation - I removed it because I think it's
> not that important for now)
> >
> > "The red dash line is the nand flash internal boot codes routine. There will be
> some important check points:
> > 1:If BOOT_INT fuse is 0x1, The internal boot will be enabled.
> > 2:If IROM_SUPPORT_EN fuse is 0x1, The ROM codes will be enabled.
> > 3:ROM codes will read GPCR register to check the boot pin settings.
> > 4:ROM codes will enable the Nand flash support, and get the Nand flash IO bus
> width by the value from boot pin settings.
> > 5:ROM codes will read ADD_CYCLE[1:0] to get the right Nand flash access
> cycle.
> > 6:ROM codes will send Nand flash reset command to Nand flash.
> >     Note: Micron flash(and the same alliance Nand flash manufacture need the
> reset command before operation the flash, Our external will not send out the
> command, Enable internal boot will enable this type of flash)
> > 7:ROM codes will read the first 2K page datum from flash to Nand flash controller
> buffer(Address 0xd8000000).
> > 8:ROM codes will check the CSF/DCD segment, but if the chipset HAB type is
> engineer version, It will just log the error message and jump to load address
> directly, Please check details in the follow section."
> >
> > Remark item 6...
> >
> yes I also saw this document, but Freescale told us several times that nand
> boot on Micron flash is not working so I didn't investigate more as we have
> NOR boot as a default on this platform ... and have switched to i.MX25 & 35
> for new applications.
> 
> > Fragment from another Freescale doc :
> >
> > "►Option 1: Connect POR_B reset signal to NAND_Init
> > • Only available on NAND Flash devices that have the NAND_Init pin.
> > ►Option 2: Use Internal Boot Mode
> > • Requires eFuses to be programmed to enable Internal Boot Mode,
> > select NAND Flash address cycles and iROM support enable.
> > • Add NAND Flash Header to NAND to support iROM Boot.
> > ►Option 3: Double POR_B reset to i.MX27
> > • Initial POR_B will generate a hidden Reset in the NAND Flash when
> > i.MX27 performs initial NAND Flash read cycle.
> > • Reassert then deassert POR_B to re-generate the initial NAND Flash
> > read cycle.
> > • Hidden NAND Flash reset will NOT occur since power was not removed
> > from the NAND Flash.
> > • Small uC can be used to generate the timing."
> >
> > See option 2...
> >
> > At the moment, we are working on i.MX27PDK boards. I just checked the version
> id : 2. Title of the application note : "iMx27 TO2 Internal Boot". So, I guess this is
> intended for our version.
> >
> > If I'm right, your company is also manufacturer of i.MX27 based boards.
> Therefore, I tend to rely on your experience with that processor. Moreover, the
> application note is still a "draft" version... On the other hand, Freescale confirmed
> that we could use that kind of Micron NAND flashes without any problem. They
> even reviewed our own board design and made no remarks with respect to the
> NAND flash (no remarks on adding extra logic to support that type of NAND)...
> > This is a very confusing situation and it might result in a redesign of our board...
> >
> I've not worked enough on nand boot on i.MX27 to provide more feedback but FSL
> & Micron recommended us the workaround implying a double POR for nand boot.
> 
> The problem is that sometime workaround sent by support that are not even
> tested and sometime there are things in the documentation which are also not
> tested or even not present in the CPU so it's difficult to know where is the
> truth without spending time on this problem ...
> 
> Eric
[Filip] Thanks Eric for your input !
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