Re: [GIT PULL] ASoC: Samsung: Updates for v3.8

[Sangbeom Kim <sbkim73@samsung.com>]

Hi,
Thanks for review.

> There's some problems with this binding.  The main one is the gpios
> property the format of which isn't specified at all.  
All of above gpio property is i2s.
That is, 
+	gpios = <&gpz 0 2 0 0>, -> SCLK
+		<&gpz 1 2 0 0>,   ->  CDCLK
+		<&gpz 2 2 0 0>,   -> LRCK
+		<&gpz 3 2 0 0>,   -> SDI
+		<&gpz 4 2 0 0>,   -> SDO[0]
+		<&gpz 5 2 0 0>,   -> SDO[1]
+		<&gpz 6 2 0 0>;   -> SDO[2]

Do you want like a below one?
+sclk-gpios = <&gpz 0 2 0 0>, 
+cdclk-gpios = <&gpz 1 2 0 0>, ...


> The requirement for an alias is also very odd, where does that come from?

I don't know that Which one is odd. Please let me know.
 
> Some of the code also looks very peculiar, like the fact that it's
> generating a clock name i2s_opclk%d rather than hard coding the clock,
> the physical clock would normally be resolved based on the struct
> device.

This is to handle all of Samsung SOCs i2c clock mux.
Please look at below clk_lookup table

In case of 6410, clk_lookup
+	CLKDEV_INIT("samsung-i2s.0", "i2s_opclk0", &clk_i2s0),
+	CLKDEV_INIT("samsung-i2s.0", "i2s_opclk1", &clk_audio_bus0.clk),
+	CLKDEV_INIT("samsung-i2s.1", "i2s_opclk0", &clk_i2s1),
+	CLKDEV_INIT("samsung-i2s.1", "i2s_opclk1", &clk_audio_bus1.clk),
+#ifdef CONFIG_CPU_S3C6410
+	CLKDEV_INIT("samsung-i2s.2", "i2s_opclk0", &clk_i2s2),
+	CLKDEV_INIT("samsung-i2s.2", "i2s_opclk1", &clk_audio_bus2.clk),

In case of exynos5, clk_lookup
+	CLKDEV_INIT("samsung-i2s.0", "i2s_opclk0", &exynos5_clk_sclk_i2s.clk),
+	CLKDEV_INIT("samsung-i2s.0", "i2s_opclk1", &exynos5_clk_i2s_bus.clk),

We try to handle clock source of i2s by only i2s_opclk0 and i2s_opclk1.
Each SOCs have different clock source.
Is this wrong approach?

Thanks,
Sangbeom.