RE: [PATCH v3 3/9] arm64: dts: exynos: ExynosAutov920: add USB and USB-phy nodes

["Pritam Manohar Sutar" <pritam.sutar@samsung.com>]

Hi Krzysztof,

> -----Original Message-----
> From: Krzysztof Kozlowski <krzk@kernel.org>
> Sent: 16 June 2025 01:43 PM
> To: Pritam Manohar Sutar <pritam.sutar@samsung.com>
> Cc: vkoul@kernel.org; kishon@kernel.org; robh@kernel.org;
> krzk+dt@kernel.org; conor+dt@kernel.org; alim.akhtar@samsung.com;
> andre.draszik@linaro.org; peter.griffin@linaro.org; kauschluss@disroot.org;
> ivo.ivanov.ivanov1@gmail.com; m.szyprowski@samsung.com;
> s.nawrocki@samsung.com; linux-phy@lists.infradead.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; linux-samsung-soc@vger.kernel.org;
> rosa.pila@samsung.com; dev.tailor@samsung.com;
> faraz.ata@samsung.com; muhammed.ali@samsung.com;
> selvarasu.g@samsung.com
> Subject: Re: [PATCH v3 3/9] arm64: dts: exynos: ExynosAutov920: add USB
> and USB-phy nodes
> 
> On Fri, Jun 13, 2025 at 11:26:07AM GMT, Pritam Manohar Sutar wrote:
> > Add USB controller and USB PHY controller nodes for this SoC.
> >
> > The USB controller has following features:
> > * Dual Role Device (DRD) controller
> > * DWC3 compatible
> > * Supports USB 3.0 host and USB 3.0 device interfaces but phy
> >   controller capability is limited to USB 2.0.
> > * Supports  full-speed (12 Mbps) and high-speed (480 Mbps) modes with
> >   USB device 2.0 interface
> > * Supports on-chip USB PHY transceiver
> > * Supports up to 16 bi-directional endpoints (that includes control
> >   endpoint 0)
> > * Complies with xHCI 1.1 specification
> >
> > Signed-off-by: Pritam Manohar Sutar <pritam.sutar@samsung.com>
> > ---
> >  .../boot/dts/exynos/exynosautov920-sadk.dts   |  37 ++++++
> >  .../arm64/boot/dts/exynos/exynosautov920.dtsi | 108
> > ++++++++++++++++++
> >  2 files changed, 145 insertions(+)
> 
> DTS cannot be a dependency for driver changes. Organize your patchset
> correctly or fix the dependency.
> 

ExynosAutov920 has three types of the phy controllers (please check block diagram mentioned in cover-letter https://lore.kernel.org/linux-phy/20250613055613.866909-1-pritam.sutar@samsung.com/)
1. HS phy (synopsys phy version v303), similar as existing exynos850.
2. SS phy in combo that that suppors only SS+, SS
3. HS phy (synopsys phy version v400) in 'Add-on' HS phy in combo phy (with 2nd phy). Different from 1st phy in case of  reg offsets and bits.

This implementation follows below sequence to post patches for above phys
1. schema 
2. driver changes
3. DTS changes 

Please elaborate your comment. Do you want these DTS related patches in separate patch-set series (not with this patch-set)?

> Best regards,
> Krzysztof


Thank you.

Regards,
Pritam