From: colin.tuckley@arm.com (Colin Tuckley)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH] ARM: Improve the L2 cache performance when PL310 is used
Date: Tue, 9 Mar 2010 10:30:01 -0000 [thread overview]
Message-ID: <000401cabf73$79a19fa0$6ce4dee0$@tuckley@arm.com> (raw)
In-Reply-To: <20100309101248.7359.60873.stgit@e102109-lin.cambridge.arm.com>
> -----Original Message-----
> From: linux-arm-kernel-bounces at lists.infradead.org [mailto:linux-arm-
> kernel-bounces at lists.infradead.org] On Behalf Of Catalin Marinas
> With this L2 cache controller, the cache maintenance by PA and sync
> operations are atomic and do not require a "wait" loop or spinlocks.
> This patch conditionally defines the cache_wait() function and locking
> primitives (rather than duplicating the functions or file).
>
> Since L2x0 cache controllers do not work with ARMv7 CPUs, the patch
> automatically enables CACHE_PL310 when CPU_V7 is defined.
That will cause a problem with A8 CPUs which are V7 but which do *not* use a
PL310 for the L2 cache.
Colin
next prev parent reply other threads:[~2010-03-09 10:30 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-03-09 10:14 [PATCH] ARM: Improve the L2 cache performance when PL310 is used Catalin Marinas
2010-03-09 10:30 ` Colin Tuckley [this message]
2010-03-09 10:52 ` Catalin Marinas
2010-03-09 11:07 ` Colin Tuckley
2010-03-09 11:28 ` Shilimkar, Santosh
2010-03-13 13:34 ` Shilimkar, Santosh
2011-02-15 11:29 ` Srinidhi Kasagar
2011-02-15 16:43 ` Catalin Marinas
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