From: colin.tuckley@arm.com (Colin Tuckley)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH] ARM: Improve the L2 cache performance when PL310 is used
Date: Tue, 9 Mar 2010 11:07:41 -0000 [thread overview]
Message-ID: <000501cabf78$bceab6c0$36c02440$@tuckley@arm.com> (raw)
In-Reply-To: <1268131959.3239.11.camel@e102109-lin.cambridge.arm.com>
> -----Original Message-----
> From: Catalin Marinas
> But do they use an L220? Or they don't use anything?
The A8 has it's own L2 cache design, the chip used on the PBA8 has a bit tacked on that makes it look a bit like a 220. I'm also told that it's possible to implement an A8 without a level two cache.
I think this is a case of reading the docs or maybe raising an Arm-support ticket.
Colin
--
Colin Tuckley - ARM Ltd.
110 Fulbourn Rd
Cambridge, CB1 9NJ
Tel: +44 1223 400536
next prev parent reply other threads:[~2010-03-09 11:07 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-03-09 10:14 [PATCH] ARM: Improve the L2 cache performance when PL310 is used Catalin Marinas
2010-03-09 10:30 ` Colin Tuckley
2010-03-09 10:52 ` Catalin Marinas
2010-03-09 11:07 ` Colin Tuckley [this message]
2010-03-09 11:28 ` Shilimkar, Santosh
2010-03-13 13:34 ` Shilimkar, Santosh
2011-02-15 11:29 ` Srinidhi Kasagar
2011-02-15 16:43 ` Catalin Marinas
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