[PATCH v2 00/10] Multiple fixes in PCIe qcom driver

[PATCH v2 00/10] Multiple fixes in PCIe qcom driver

[Ansuel Smith]

This contains multiple fix for PCIe qcom driver.
Some optional reset and clocks were missing.
Fix a problem with no PARF programming that cause kernel lock on load.
Add support to force gen 1 speed if needed. (due to hardware limitation)
Add ipq8064 rev 2 support that use a different tx termination offset.

v2:
* Drop iATU programming (already done in pcie init)
* Use max-link-speed instead of force-gen1 custom definition
* Drop MRRS to 256B (Can't find a realy reason why this was suggested)
* Introduce a new variant for different revision of ipq8064

Abhishek Sahu (1):
  PCIe: qcom: change duplicate PCI reset to phy reset

Ansuel Smith (7):
  PCIe: qcom: add missing ipq806x clocks in PCIe driver
  devicetree: bindings: pci: add missing clks to qcom,pcie
  PCIe: qcom: Fixed pcie_phy_clk branch issue
  PCIe: qcom: add missing reset for ipq806x
  devicetree: bindings: pci: add ext reset to qcom,pcie
  PCIe: qcom: fix init problem with missing PARF programming
  devicetree: bindings: pci: add ipq8064 rev 2 variant to qcom,pcie

Sham Muthayyan (2):
  PCIe: qcom: add ipq8064 rev2 variant and set tx term offset
  PCIe: qcom: add Force GEN1 support

 .../devicetree/bindings/pci/qcom,pcie.txt     |  56 +++++++-
 drivers/pci/controller/dwc/pcie-qcom.c        | 134 +++++++++++++++---
 2 files changed, 167 insertions(+), 23 deletions(-)

-- 
2.25.1

[PATCH v2 01/10] PCIe: qcom: add missing ipq806x clocks in PCIe driver

[Ansuel Smith]

Aux and Ref clk are missing in pcie qcom driver.
Add support in the driver to fix pcie inizialization in ipq806x.

Fixes: 82a82383 PCI: qcom: Add Qualcomm PCIe controller driver
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
 drivers/pci/controller/dwc/pcie-qcom.c | 38 ++++++++++++++++++++++----
 1 file changed, 33 insertions(+), 5 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 5ea527a6bd9f..f958c535de6e 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -88,6 +88,8 @@ struct qcom_pcie_resources_2_1_0 {
 	struct clk *iface_clk;
 	struct clk *core_clk;
 	struct clk *phy_clk;
+	struct clk *aux_clk;
+	struct clk *ref_clk;
 	struct reset_control *pci_reset;
 	struct reset_control *axi_reset;
 	struct reset_control *ahb_reset;
@@ -246,6 +248,14 @@ static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie)
 	if (IS_ERR(res->phy_clk))
 		return PTR_ERR(res->phy_clk);
 
+	res->aux_clk = devm_clk_get(dev, "aux");
+	if (IS_ERR(res->aux_clk))
+		return PTR_ERR(res->aux_clk);
+
+	res->ref_clk = devm_clk_get(dev, "ref");
+	if (IS_ERR(res->ref_clk))
+		return PTR_ERR(res->ref_clk);
+
 	res->pci_reset = devm_reset_control_get_exclusive(dev, "pci");
 	if (IS_ERR(res->pci_reset))
 		return PTR_ERR(res->pci_reset);
@@ -278,6 +288,8 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie)
 	clk_disable_unprepare(res->iface_clk);
 	clk_disable_unprepare(res->core_clk);
 	clk_disable_unprepare(res->phy_clk);
+	clk_disable_unprepare(res->aux_clk);
+	clk_disable_unprepare(res->ref_clk);
 	regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
 }
 
@@ -307,16 +319,28 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
 		goto err_assert_ahb;
 	}
 
+	ret = clk_prepare_enable(res->core_clk);
+	if (ret) {
+		dev_err(dev, "cannot prepare/enable core clock\n");
+		goto err_clk_core;
+	}
+
 	ret = clk_prepare_enable(res->phy_clk);
 	if (ret) {
 		dev_err(dev, "cannot prepare/enable phy clock\n");
 		goto err_clk_phy;
 	}
 
-	ret = clk_prepare_enable(res->core_clk);
+	ret = clk_prepare_enable(res->aux_clk);
 	if (ret) {
-		dev_err(dev, "cannot prepare/enable core clock\n");
-		goto err_clk_core;
+		dev_err(dev, "cannot prepare/enable aux clock\n");
+		goto err_clk_aux;
+	}
+
+	ret = clk_prepare_enable(res->ref_clk);
+	if (ret) {
+		dev_err(dev, "cannot prepare/enable ref clock\n");
+		goto err_clk_ref;
 	}
 
 	ret = reset_control_deassert(res->ahb_reset);
@@ -372,10 +396,14 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
 	return 0;
 
 err_deassert_ahb:
-	clk_disable_unprepare(res->core_clk);
-err_clk_core:
+	clk_disable_unprepare(res->ref_clk);
+err_clk_ref:
+	clk_disable_unprepare(res->aux_clk);
+err_clk_aux:
 	clk_disable_unprepare(res->phy_clk);
 err_clk_phy:
+	clk_disable_unprepare(res->core_clk);
+err_clk_core:
 	clk_disable_unprepare(res->iface_clk);
 err_assert_ahb:
 	regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
-- 
2.25.1

Re: [PATCH v2 01/10] PCIe: qcom: add missing ipq806x clocks in PCIe driver

[Stanimir Varbanov]

Ansuel,

On 4/2/20 3:11 PM, Ansuel Smith wrote:
> Aux and Ref clk are missing in pcie qcom driver.
> Add support in the driver to fix pcie inizialization in ipq806x.
> 
> Fixes: 82a82383 PCI: qcom: Add Qualcomm PCIe controller driver

this should be:

Fixes: 82a823833f4e PCI: qcom: Add Qualcomm PCIe controller driver

and add:

Cc: stable@vger.kernel.org # v4.5+

But, I wonder, as apq8064 shares the same ops_2_1_0 how it worked until
now. Something more I cannot find such clocks for apq8064, which means
that this patch will break it.

One option is to use those new clocks only for ipq806x.

> Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> ---
>  drivers/pci/controller/dwc/pcie-qcom.c | 38 ++++++++++++++++++++++----
>  1 file changed, 33 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index 5ea527a6bd9f..f958c535de6e 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -88,6 +88,8 @@ struct qcom_pcie_resources_2_1_0 {
>  	struct clk *iface_clk;
>  	struct clk *core_clk;
>  	struct clk *phy_clk;
> +	struct clk *aux_clk;
> +	struct clk *ref_clk;
>  	struct reset_control *pci_reset;
>  	struct reset_control *axi_reset;
>  	struct reset_control *ahb_reset;
> @@ -246,6 +248,14 @@ static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie)
>  	if (IS_ERR(res->phy_clk))
>  		return PTR_ERR(res->phy_clk);
>  
> +	res->aux_clk = devm_clk_get(dev, "aux");
> +	if (IS_ERR(res->aux_clk))
> +		return PTR_ERR(res->aux_clk);
> +
> +	res->ref_clk = devm_clk_get(dev, "ref");
> +	if (IS_ERR(res->ref_clk))
> +		return PTR_ERR(res->ref_clk);
> +
>  	res->pci_reset = devm_reset_control_get_exclusive(dev, "pci");
>  	if (IS_ERR(res->pci_reset))
>  		return PTR_ERR(res->pci_reset);
> @@ -278,6 +288,8 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie)
>  	clk_disable_unprepare(res->iface_clk);
>  	clk_disable_unprepare(res->core_clk);
>  	clk_disable_unprepare(res->phy_clk);
> +	clk_disable_unprepare(res->aux_clk);
> +	clk_disable_unprepare(res->ref_clk);
>  	regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
>  }
>  
> @@ -307,16 +319,28 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
>  		goto err_assert_ahb;
>  	}
>  
> +	ret = clk_prepare_enable(res->core_clk);
> +	if (ret) {
> +		dev_err(dev, "cannot prepare/enable core clock\n");
> +		goto err_clk_core;
> +	}
> +
>  	ret = clk_prepare_enable(res->phy_clk);
>  	if (ret) {
>  		dev_err(dev, "cannot prepare/enable phy clock\n");
>  		goto err_clk_phy;
>  	}
>  
> -	ret = clk_prepare_enable(res->core_clk);
> +	ret = clk_prepare_enable(res->aux_clk);
>  	if (ret) {
> -		dev_err(dev, "cannot prepare/enable core clock\n");
> -		goto err_clk_core;
> +		dev_err(dev, "cannot prepare/enable aux clock\n");
> +		goto err_clk_aux;
> +	}
> +
> +	ret = clk_prepare_enable(res->ref_clk);
> +	if (ret) {
> +		dev_err(dev, "cannot prepare/enable ref clock\n");
> +		goto err_clk_ref;
>  	}
>  
>  	ret = reset_control_deassert(res->ahb_reset);
> @@ -372,10 +396,14 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
>  	return 0;
>  
>  err_deassert_ahb:
> -	clk_disable_unprepare(res->core_clk);
> -err_clk_core:
> +	clk_disable_unprepare(res->ref_clk);
> +err_clk_ref:
> +	clk_disable_unprepare(res->aux_clk);
> +err_clk_aux:
>  	clk_disable_unprepare(res->phy_clk);
>  err_clk_phy:
> +	clk_disable_unprepare(res->core_clk);
> +err_clk_core:
>  	clk_disable_unprepare(res->iface_clk);
>  err_assert_ahb:
>  	regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
> 

-- 
regards,
Stan

R: [PATCH v2 01/10] PCIe: qcom: add missing ipq806x clocks in PCIe driver

[ansuelsmth]

> PCIe driver
> 
> Ansuel,
> 
> On 4/2/20 3:11 PM, Ansuel Smith wrote:
> > Aux and Ref clk are missing in pcie qcom driver.
> > Add support in the driver to fix pcie inizialization in ipq806x.
> >
> > Fixes: 82a82383 PCI: qcom: Add Qualcomm PCIe controller driver
> 
> this should be:
> 
> Fixes: 82a823833f4e PCI: qcom: Add Qualcomm PCIe controller driver
> 
> and add:
> 
> Cc: stable@vger.kernel.org # v4.5+
> 
> But, I wonder, as apq8064 shares the same ops_2_1_0 how it worked until
> now. Something more I cannot find such clocks for apq8064, which means
> that this patch will break it.
> 
> One option is to use those new clocks only for ipq806x.
> 

How to add this new clocks only for ipq806x? Check the compatible and add
them accordingly? 

> > Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
> > Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> > ---
> >  drivers/pci/controller/dwc/pcie-qcom.c | 38
> ++++++++++++++++++++++----
> >  1 file changed, 33 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c
> b/drivers/pci/controller/dwc/pcie-qcom.c
> > index 5ea527a6bd9f..f958c535de6e 100644
> > --- a/drivers/pci/controller/dwc/pcie-qcom.c
> > +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> > @@ -88,6 +88,8 @@ struct qcom_pcie_resources_2_1_0 {
> >  	struct clk *iface_clk;
> >  	struct clk *core_clk;
> >  	struct clk *phy_clk;
> > +	struct clk *aux_clk;
> > +	struct clk *ref_clk;
> >  	struct reset_control *pci_reset;
> >  	struct reset_control *axi_reset;
> >  	struct reset_control *ahb_reset;
> > @@ -246,6 +248,14 @@ static int
> qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie)
> >  	if (IS_ERR(res->phy_clk))
> >  		return PTR_ERR(res->phy_clk);
> >
> > +	res->aux_clk = devm_clk_get(dev, "aux");
> > +	if (IS_ERR(res->aux_clk))
> > +		return PTR_ERR(res->aux_clk);
> > +
> > +	res->ref_clk = devm_clk_get(dev, "ref");
> > +	if (IS_ERR(res->ref_clk))
> > +		return PTR_ERR(res->ref_clk);
> > +
> >  	res->pci_reset = devm_reset_control_get_exclusive(dev, "pci");
> >  	if (IS_ERR(res->pci_reset))
> >  		return PTR_ERR(res->pci_reset);
> > @@ -278,6 +288,8 @@ static void qcom_pcie_deinit_2_1_0(struct
> qcom_pcie *pcie)
> >  	clk_disable_unprepare(res->iface_clk);
> >  	clk_disable_unprepare(res->core_clk);
> >  	clk_disable_unprepare(res->phy_clk);
> > +	clk_disable_unprepare(res->aux_clk);
> > +	clk_disable_unprepare(res->ref_clk);
> >  	regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
> >  }
> >
> > @@ -307,16 +319,28 @@ static int qcom_pcie_init_2_1_0(struct
> qcom_pcie *pcie)
> >  		goto err_assert_ahb;
> >  	}
> >
> > +	ret = clk_prepare_enable(res->core_clk);
> > +	if (ret) {
> > +		dev_err(dev, "cannot prepare/enable core clock\n");
> > +		goto err_clk_core;
> > +	}
> > +
> >  	ret = clk_prepare_enable(res->phy_clk);
> >  	if (ret) {
> >  		dev_err(dev, "cannot prepare/enable phy clock\n");
> >  		goto err_clk_phy;
> >  	}
> >
> > -	ret = clk_prepare_enable(res->core_clk);
> > +	ret = clk_prepare_enable(res->aux_clk);
> >  	if (ret) {
> > -		dev_err(dev, "cannot prepare/enable core clock\n");
> > -		goto err_clk_core;
> > +		dev_err(dev, "cannot prepare/enable aux clock\n");
> > +		goto err_clk_aux;
> > +	}
> > +
> > +	ret = clk_prepare_enable(res->ref_clk);
> > +	if (ret) {
> > +		dev_err(dev, "cannot prepare/enable ref clock\n");
> > +		goto err_clk_ref;
> >  	}
> >
> >  	ret = reset_control_deassert(res->ahb_reset);
> > @@ -372,10 +396,14 @@ static int qcom_pcie_init_2_1_0(struct
> qcom_pcie *pcie)
> >  	return 0;
> >
> >  err_deassert_ahb:
> > -	clk_disable_unprepare(res->core_clk);
> > -err_clk_core:
> > +	clk_disable_unprepare(res->ref_clk);
> > +err_clk_ref:
> > +	clk_disable_unprepare(res->aux_clk);
> > +err_clk_aux:
> >  	clk_disable_unprepare(res->phy_clk);
> >  err_clk_phy:
> > +	clk_disable_unprepare(res->core_clk);
> > +err_clk_core:
> >  	clk_disable_unprepare(res->iface_clk);
> >  err_assert_ahb:
> >  	regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
> >
> 
> --
> regards,
> Stan

Re: R: [PATCH v2 01/10] PCIe: qcom: add missing ipq806x clocks in PCIe driver

[Stanimir Varbanov]

Hi Ansuel,

On 4/8/20 3:36 PM, ansuelsmth@gmail.com wrote:
>> PCIe driver
>>
>> Ansuel,
>>
>> On 4/2/20 3:11 PM, Ansuel Smith wrote:
>>> Aux and Ref clk are missing in pcie qcom driver.
>>> Add support in the driver to fix pcie inizialization in ipq806x.
>>>
>>> Fixes: 82a82383 PCI: qcom: Add Qualcomm PCIe controller driver
>>
>> this should be:
>>
>> Fixes: 82a823833f4e PCI: qcom: Add Qualcomm PCIe controller driver
>>
>> and add:
>>
>> Cc: stable@vger.kernel.org # v4.5+
>>
>> But, I wonder, as apq8064 shares the same ops_2_1_0 how it worked until
>> now. Something more I cannot find such clocks for apq8064, which means
>> that this patch will break it.
>>
>> One option is to use those new clocks only for ipq806x.
>>
> 
> How to add this new clocks only for ipq806x? Check the compatible and add
> them accordingly? 
> 

Yes, through of_device_is_compatible(). See how we done this in
qcom_pcie_get_resources_2_4_0.

I thought about second option though - encoder what clocks we have for
any SoC but if you take into that direction you have to change the whole
driver :)

Another option is to use clk_get_optional() for the clocks which you
have on ipq806x (and don't have on apq8064). Please research this one
first.

-- 
regards,
Stan

R: R: [PATCH v2 01/10] PCIe: qcom: add missing ipq806x clocks in PCIe driver

[ansuelsmth]

> in PCIe driver
> 
> Hi Ansuel,
> 
> On 4/8/20 3:36 PM, ansuelsmth@gmail.com wrote:
> >> PCIe driver
> >>
> >> Ansuel,
> >>
> >> On 4/2/20 3:11 PM, Ansuel Smith wrote:
> >>> Aux and Ref clk are missing in pcie qcom driver.
> >>> Add support in the driver to fix pcie inizialization in ipq806x.
> >>>
> >>> Fixes: 82a82383 PCI: qcom: Add Qualcomm PCIe controller driver
> >>
> >> this should be:
> >>
> >> Fixes: 82a823833f4e PCI: qcom: Add Qualcomm PCIe controller driver
> >>
> >> and add:
> >>
> >> Cc: stable@vger.kernel.org # v4.5+
> >>
> >> But, I wonder, as apq8064 shares the same ops_2_1_0 how it worked
> until
> >> now. Something more I cannot find such clocks for apq8064, which
> means
> >> that this patch will break it.
> >>
> >> One option is to use those new clocks only for ipq806x.
> >>
> >
> > How to add this new clocks only for ipq806x? Check the compatible and
> add
> > them accordingly?
> >
> 
> Yes, through of_device_is_compatible(). See how we done this in
> qcom_pcie_get_resources_2_4_0.
> 
> I thought about second option though - encoder what clocks we have for
> any SoC but if you take into that direction you have to change the whole
> driver :)
> 
> Another option is to use clk_get_optional() for the clocks which you
> have on ipq806x (and don't have on apq8064). Please research this one
> first.
> 
> --
> regards,
> Stan

Ok I will use get optional for the extra clocks. Should I add a warning if they 
are not present? Also what about the extra reset? Should I follow the same
approach? 
Thx for the suggestions. 

Re: R: R: [PATCH v2 01/10] PCIe: qcom: add missing ipq806x clocks in PCIe driver

[Stanimir Varbanov]

On 4/8/20 3:55 PM, ansuelsmth@gmail.com wrote:
>> in PCIe driver
>>
>> Hi Ansuel,
>>
>> On 4/8/20 3:36 PM, ansuelsmth@gmail.com wrote:
>>>> PCIe driver
>>>>
>>>> Ansuel,
>>>>
>>>> On 4/2/20 3:11 PM, Ansuel Smith wrote:
>>>>> Aux and Ref clk are missing in pcie qcom driver.
>>>>> Add support in the driver to fix pcie inizialization in ipq806x.
>>>>>
>>>>> Fixes: 82a82383 PCI: qcom: Add Qualcomm PCIe controller driver
>>>>
>>>> this should be:
>>>>
>>>> Fixes: 82a823833f4e PCI: qcom: Add Qualcomm PCIe controller driver
>>>>
>>>> and add:
>>>>
>>>> Cc: stable@vger.kernel.org # v4.5+
>>>>
>>>> But, I wonder, as apq8064 shares the same ops_2_1_0 how it worked
>> until
>>>> now. Something more I cannot find such clocks for apq8064, which
>> means
>>>> that this patch will break it.
>>>>
>>>> One option is to use those new clocks only for ipq806x.
>>>>
>>>
>>> How to add this new clocks only for ipq806x? Check the compatible and
>> add
>>> them accordingly?
>>>
>>
>> Yes, through of_device_is_compatible(). See how we done this in
>> qcom_pcie_get_resources_2_4_0.
>>
>> I thought about second option though - encoder what clocks we have for
>> any SoC but if you take into that direction you have to change the whole
>> driver :)
>>
>> Another option is to use clk_get_optional() for the clocks which you
>> have on ipq806x (and don't have on apq8064). Please research this one
>> first.
>>
>> --
>> regards,
>> Stan
> 
> Ok I will use get optional for the extra clocks. Should I add a warning if they 
> are not present? Also what about the extra reset? Should I follow the same
> approach? 
> Thx for the suggestions. 
> 

No warnings please. You should follow the same rules for resets.

-- 
regards,
Stan

[PATCH v2 02/10] devicetree: bindings: pci: add missing clks to qcom,pcie

[Ansuel Smith]

Document missing clks used in ipq806x soc.

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
---
 Documentation/devicetree/bindings/pci/qcom,pcie.txt | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
index 981b4de12807..becdbdc0fffa 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
@@ -90,6 +90,8 @@
 	Definition: Should contain the following entries
 			- "core"	Clocks the pcie hw block
 			- "phy"		Clocks the pcie PHY block
+			- "aux" 	Clocks the pcie AUX block
+			- "ref" 	Clocks the pcie ref block
 - clock-names:
 	Usage: required for apq8084/ipq4019
 	Value type: <stringlist>
@@ -277,8 +279,10 @@
 				<0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 		clocks = <&gcc PCIE_A_CLK>,
 			 <&gcc PCIE_H_CLK>,
-			 <&gcc PCIE_PHY_CLK>;
-		clock-names = "core", "iface", "phy";
+			 <&gcc PCIE_PHY_CLK>,
+			 <&gcc PCIE_AUX_CLK>,
+			 <&gcc PCIE_ALT_REF_CLK>;
+		clock-names = "core", "iface", "phy", "aux", "ref";
 		resets = <&gcc PCIE_ACLK_RESET>,
 			 <&gcc PCIE_HCLK_RESET>,
 			 <&gcc PCIE_POR_RESET>,
-- 
2.25.1

[PATCH v2 03/10] PCIe: qcom: change duplicate PCI reset to phy reset

[Ansuel Smith]

From: Abhishek Sahu <absahu@codeaurora.org>

The deinit issues reset_control_assert for pci twice and does not contain
phy reset.

Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
 drivers/pci/controller/dwc/pcie-qcom.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index f958c535de6e..1fcc7fed8443 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -284,7 +284,7 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie)
 	reset_control_assert(res->axi_reset);
 	reset_control_assert(res->ahb_reset);
 	reset_control_assert(res->por_reset);
-	reset_control_assert(res->pci_reset);
+	reset_control_assert(res->phy_reset);
 	clk_disable_unprepare(res->iface_clk);
 	clk_disable_unprepare(res->core_clk);
 	clk_disable_unprepare(res->phy_clk);
-- 
2.25.1

[PATCH v2 04/10] PCIe: qcom: Fixed pcie_phy_clk branch issue

[Ansuel Smith]

Following backtraces are observed in PCIe deinit operation.

 Hardware name: Qualcomm (Flattened Device Tree)
 (unwind_backtrace) from [] (show_stack+0x10/0x14)
 (show_stack) from [] (dump_stack+0x84/0x98)
 (dump_stack) from [] (warn_slowpath_common+0x9c/0xb8)
 (warn_slowpath_common) from [] (warn_slowpath_fmt+0x30/0x40)
 (warn_slowpath_fmt) from [] (clk_branch_wait+0x114/0x120)
 (clk_branch_wait) from [] (clk_core_disable+0xd0/0x1f4)
 (clk_core_disable) from [] (clk_disable+0x24/0x30)
 (clk_disable) from [] (qcom_pcie_deinit_v0+0x6c/0xb8)
 (qcom_pcie_deinit_v0) from [] (qcom_pcie_host_init+0xe0/0xe8)
 (qcom_pcie_host_init) from [] (dw_pcie_host_init+0x3b0/0x538)
 (dw_pcie_host_init) from [] (qcom_pcie_probe+0x20c/0x2e4)

pcie_phy_clk is generated for PCIe controller itself and the
GCC controls its branch operation. This error is coming since
the assert operations turn off the parent clock before branch
clock. Now this patch moves clk_disable_unprepare before assert
operations.

Similarly, during probe function, the clock branch operation
should be done after dessert operation. Currently, it does not
generate any error since bootloader enables the pcie_phy_clk
but the same error is coming during probe, if bootloader
disables pcie_phy_clk.

Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
 drivers/pci/controller/dwc/pcie-qcom.c | 16 +++++++---------
 1 file changed, 7 insertions(+), 9 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 1fcc7fed8443..596731b54728 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -280,6 +280,7 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie)
 {
 	struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
 
+	clk_disable_unprepare(res->phy_clk);
 	reset_control_assert(res->pci_reset);
 	reset_control_assert(res->axi_reset);
 	reset_control_assert(res->ahb_reset);
@@ -287,7 +288,6 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie)
 	reset_control_assert(res->phy_reset);
 	clk_disable_unprepare(res->iface_clk);
 	clk_disable_unprepare(res->core_clk);
-	clk_disable_unprepare(res->phy_clk);
 	clk_disable_unprepare(res->aux_clk);
 	clk_disable_unprepare(res->ref_clk);
 	regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
@@ -325,12 +325,6 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
 		goto err_clk_core;
 	}
 
-	ret = clk_prepare_enable(res->phy_clk);
-	if (ret) {
-		dev_err(dev, "cannot prepare/enable phy clock\n");
-		goto err_clk_phy;
-	}
-
 	ret = clk_prepare_enable(res->aux_clk);
 	if (ret) {
 		dev_err(dev, "cannot prepare/enable aux clock\n");
@@ -383,6 +377,12 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
 		return ret;
 	}
 
+	ret = clk_prepare_enable(res->phy_clk);
+	if (ret) {
+		dev_err(dev, "cannot prepare/enable phy clock\n");
+		goto err_deassert_ahb;
+	}
+
 	/* wait for clock acquisition */
 	usleep_range(1000, 1500);
 
@@ -400,8 +400,6 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
 err_clk_ref:
 	clk_disable_unprepare(res->aux_clk);
 err_clk_aux:
-	clk_disable_unprepare(res->phy_clk);
-err_clk_phy:
 	clk_disable_unprepare(res->core_clk);
 err_clk_core:
 	clk_disable_unprepare(res->iface_clk);
-- 
2.25.1

[PATCH v2 05/10] PCIe: qcom: add missing reset for ipq806x

[Ansuel Smith]

Add missing ext reset used by ipq806x SoC in PCIe qcom driver.

Fixes: 82a82383 PCI: qcom: Add Qualcomm PCIe controller driver
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
 drivers/pci/controller/dwc/pcie-qcom.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 596731b54728..211a1aa7d0f1 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -95,6 +95,7 @@ struct qcom_pcie_resources_2_1_0 {
 	struct reset_control *ahb_reset;
 	struct reset_control *por_reset;
 	struct reset_control *phy_reset;
+	struct reset_control *ext_reset;
 	struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY];
 };
 
@@ -272,6 +273,10 @@ static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie)
 	if (IS_ERR(res->por_reset))
 		return PTR_ERR(res->por_reset);
 
+	res->ext_reset = devm_reset_control_get_exclusive(dev, "ext");
+	if (IS_ERR(res->ext_reset))
+		return PTR_ERR(res->ext_reset);
+
 	res->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
 	return PTR_ERR_OR_ZERO(res->phy_reset);
 }
@@ -285,6 +290,7 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie)
 	reset_control_assert(res->axi_reset);
 	reset_control_assert(res->ahb_reset);
 	reset_control_assert(res->por_reset);
+	reset_control_assert(res->ext_reset);
 	reset_control_assert(res->phy_reset);
 	clk_disable_unprepare(res->iface_clk);
 	clk_disable_unprepare(res->core_clk);
@@ -343,6 +349,12 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
 		goto err_deassert_ahb;
 	}
 
+	ret = reset_control_deassert(res->ext_reset);
+	if (ret) {
+		dev_err(dev, "cannot assert ext reset\n");
+		goto err_deassert_ahb;
+	}
+
 	/* enable PCIe clocks and resets */
 	val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
 	val &= ~BIT(0);
-- 
2.25.1

[PATCH v2 06/10] devicetree: bindings: pci: add ext reset to qcom,pcie

[Ansuel Smith]

Document ext reset used in ipq806x soc by qcom pcie driver

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
---
 Documentation/devicetree/bindings/pci/qcom,pcie.txt | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
index becdbdc0fffa..6efcef040741 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
@@ -179,6 +179,7 @@
 			- "pwr"			PWR reset
 			- "ahb"			AHB reset
 			- "phy_ahb"		PHY AHB reset
+			- "ext"			EXT reset
 
 - reset-names:
 	Usage: required for ipq8074
@@ -287,8 +288,9 @@
 			 <&gcc PCIE_HCLK_RESET>,
 			 <&gcc PCIE_POR_RESET>,
 			 <&gcc PCIE_PCI_RESET>,
-			 <&gcc PCIE_PHY_RESET>;
-		reset-names = "axi", "ahb", "por", "pci", "phy";
+			 <&gcc PCIE_PHY_RESET>,
+			 <&gcc PCIE_EXT_RESET>;
+		reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
 		pinctrl-0 = <&pcie_pins_default>;
 		pinctrl-names = "default";
 	};
-- 
2.25.1

[PATCH v2 07/10] PCIe: qcom: fix init problem with missing PARF programming

[Ansuel Smith]

PARF programming was missing and this cause initilizzation problem on
some ipq806x based device (Netgear R7800 for example). This cause a
total lock of the system on kernel load.

Fixes: 82a82383 PCI: qcom: Add Qualcomm PCIe controller driver
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
 drivers/pci/controller/dwc/pcie-qcom.c | 48 +++++++++++++++++++++-----
 1 file changed, 39 insertions(+), 9 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 211a1aa7d0f1..77b1ab7e23a3 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -46,6 +46,9 @@
 
 #define PCIE20_PARF_PHY_CTRL			0x40
 #define PCIE20_PARF_PHY_REFCLK			0x4C
+#define REF_SSP_EN				BIT(16)
+#define REF_USE_PAD				BIT(12)
+
 #define PCIE20_PARF_DBI_BASE_ADDR		0x168
 #define PCIE20_PARF_SLV_ADDR_SPACE_SIZE		0x16C
 #define PCIE20_PARF_MHI_CLOCK_RESET_CTRL	0x174
@@ -77,6 +80,18 @@
 #define DBI_RO_WR_EN				1
 
 #define PERST_DELAY_US				1000
+/* PARF registers */
+#define PCIE20_PARF_PCS_DEEMPH			0x34
+#define PCS_DEEMPH_TX_DEEMPH_GEN1(x)		(x << 16)
+#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x)	(x << 8)
+#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x)	(x << 0)
+
+#define PCIE20_PARF_PCS_SWING			0x38
+#define PCS_SWING_TX_SWING_FULL(x)		(x << 8)
+#define PCS_SWING_TX_SWING_LOW(x)		(x << 0)
+
+#define PCIE20_PARF_CONFIG_BITS		0x50
+#define PHY_RX0_EQ(x)				(x << 24)
 
 #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE	0x358
 #define SLV_ADDR_SPACE_SZ			0x10000000
@@ -184,6 +199,16 @@ struct qcom_pcie {
 
 #define to_qcom_pcie(x)		dev_get_drvdata((x)->dev)
 
+static inline void qcom_clear_and_set_dword(void __iomem *addr,
+				 u32 clear_mask, u32 set_mask)
+{
+	u32 val = readl(addr);
+
+	val &= ~clear_mask;
+	val |= set_mask;
+	writel(val, addr);
+}
+
 static void qcom_ep_reset_assert(struct qcom_pcie *pcie)
 {
 	gpiod_set_value_cansleep(pcie->reset, 1);
@@ -304,7 +329,6 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
 	struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
 	struct dw_pcie *pci = pcie->pci;
 	struct device *dev = pci->dev;
-	u32 val;
 	int ret;
 
 	ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies);
@@ -355,15 +379,21 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
 		goto err_deassert_ahb;
 	}
 
-	/* enable PCIe clocks and resets */
-	val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
-	val &= ~BIT(0);
-	writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
+	qcom_clear_and_set_dword(pcie->parf + PCIE20_PARF_PHY_CTRL, BIT(0), 0);
+
+	/* PARF programming */
+	writel(PCS_DEEMPH_TX_DEEMPH_GEN1(0x18) |
+	       PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(0x18) |
+	       PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(0x22),
+	       pcie->parf + PCIE20_PARF_PCS_DEEMPH);
+	writel(PCS_SWING_TX_SWING_FULL(0x78) |
+	       PCS_SWING_TX_SWING_LOW(0x78),
+	       pcie->parf + PCIE20_PARF_PCS_SWING);
+	writel(PHY_RX0_EQ(0x4), pcie->parf + PCIE20_PARF_CONFIG_BITS);
 
-	/* enable external reference clock */
-	val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK);
-	val |= BIT(16);
-	writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK);
+	/* enable reference clock */
+	qcom_clear_and_set_dword(pcie->parf + PCIE20_PARF_PHY_REFCLK,
+		      REF_USE_PAD, REF_SSP_EN);
 
 	ret = reset_control_deassert(res->phy_reset);
 	if (ret) {
-- 
2.25.1

Re: [PATCH v2 07/10] PCIe: qcom: fix init problem with missing PARF programming

[Stanimir Varbanov]

Hi Ansuel,

Please fix the patch subject for all patches in the series per Bjorn H.
request.

PCI: qcom: Fix init problem with missing PARF programming

Also the patch subject is misleading to me. Actually you change few phy
parameters: Tx De-Emphasis, Tx Swing and Rx equalization. On the other
side I guess those parameters are board specific and I'm not sure how
this change will reflect on apq8064 boards.

On 4/2/20 3:11 PM, Ansuel Smith wrote:
> PARF programming was missing and this cause initilizzation problem on
> some ipq806x based device (Netgear R7800 for example). This cause a
> total lock of the system on kernel load.
> 
> Fixes: 82a82383 PCI: qcom: Add Qualcomm PCIe controller driver
> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> ---
>  drivers/pci/controller/dwc/pcie-qcom.c | 48 +++++++++++++++++++++-----
>  1 file changed, 39 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index 211a1aa7d0f1..77b1ab7e23a3 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -46,6 +46,9 @@
>  
>  #define PCIE20_PARF_PHY_CTRL			0x40
>  #define PCIE20_PARF_PHY_REFCLK			0x4C
> +#define REF_SSP_EN				BIT(16)
> +#define REF_USE_PAD				BIT(12)

Could you rename this to:

PHY_REFCLK_SSP_EN
PHY_REFCLK_USE_PAD

> +
>  #define PCIE20_PARF_DBI_BASE_ADDR		0x168
>  #define PCIE20_PARF_SLV_ADDR_SPACE_SIZE		0x16C
>  #define PCIE20_PARF_MHI_CLOCK_RESET_CTRL	0x174
> @@ -77,6 +80,18 @@
>  #define DBI_RO_WR_EN				1
>  
>  #define PERST_DELAY_US				1000
> +/* PARF registers */
> +#define PCIE20_PARF_PCS_DEEMPH			0x34
> +#define PCS_DEEMPH_TX_DEEMPH_GEN1(x)		(x << 16)
> +#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x)	(x << 8)
> +#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x)	(x << 0)
> +
> +#define PCIE20_PARF_PCS_SWING			0x38
> +#define PCS_SWING_TX_SWING_FULL(x)		(x << 8)
> +#define PCS_SWING_TX_SWING_LOW(x)		(x << 0)
> +
> +#define PCIE20_PARF_CONFIG_BITS		0x50
> +#define PHY_RX0_EQ(x)				(x << 24)
>  
>  #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE	0x358
>  #define SLV_ADDR_SPACE_SZ			0x10000000
> @@ -184,6 +199,16 @@ struct qcom_pcie {
>  
>  #define to_qcom_pcie(x)		dev_get_drvdata((x)->dev)
>  
> +static inline void qcom_clear_and_set_dword(void __iomem *addr,

drop 'inline' the compiler is smart enough to decide.

> +				 u32 clear_mask, u32 set_mask)
> +{
> +	u32 val = readl(addr);
> +
> +	val &= ~clear_mask;
> +	val |= set_mask;
> +	writel(val, addr);
> +}
> +

If you add such function you should introduce it in a separate patch and
use it in the whole driver where it is applicable. After that we can see
what is the benefit of it.

>  static void qcom_ep_reset_assert(struct qcom_pcie *pcie)
>  {
>  	gpiod_set_value_cansleep(pcie->reset, 1);
> @@ -304,7 +329,6 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
>  	struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
>  	struct dw_pcie *pci = pcie->pci;
>  	struct device *dev = pci->dev;
> -	u32 val;
>  	int ret;
>  
>  	ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies);
> @@ -355,15 +379,21 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
>  		goto err_deassert_ahb;
>  	}
>  
> -	/* enable PCIe clocks and resets */
> -	val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
> -	val &= ~BIT(0);
> -	writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
> +	qcom_clear_and_set_dword(pcie->parf + PCIE20_PARF_PHY_CTRL, BIT(0), 0);

please keep the comment.

> +
> +	/* PARF programming */

pointless comment, please drop it.

> +	writel(PCS_DEEMPH_TX_DEEMPH_GEN1(0x18) |
> +	       PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(0x18) |
> +	       PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(0x22),
> +	       pcie->parf + PCIE20_PARF_PCS_DEEMPH);
> +	writel(PCS_SWING_TX_SWING_FULL(0x78) |
> +	       PCS_SWING_TX_SWING_LOW(0x78),
> +	       pcie->parf + PCIE20_PARF_PCS_SWING);
> +	writel(PHY_RX0_EQ(0x4), pcie->parf + PCIE20_PARF_CONFIG_BITS);
>  
> -	/* enable external reference clock */
> -	val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK);
> -	val |= BIT(16);
> -	writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK);
> +	/* enable reference clock */

Why you dropped 'external' ?

> +	qcom_clear_and_set_dword(pcie->parf + PCIE20_PARF_PHY_REFCLK,
> +		      REF_USE_PAD, REF_SSP_EN);
>  
>  	ret = reset_control_deassert(res->phy_reset);
>  	if (ret) {
> 

-- 
regards,
Stan

R: [PATCH v2 07/10] PCIe: qcom: fix init problem with missing PARF programming

[ansuelsmth]

> PARF programming
> 
> Hi Ansuel,
> 
> Please fix the patch subject for all patches in the series per Bjorn H.
> request.
> 
> PCI: qcom: Fix init problem with missing PARF programming
> 
> Also the patch subject is misleading to me. Actually you change few phy
> parameters: Tx De-Emphasis, Tx Swing and Rx equalization. On the other
> side I guess those parameters are board specific and I'm not sure how
> this change will reflect on apq8064 boards.
> 

I also think that this would brake apq8064, on ipq8064 this is needed or 
the system doesn't boot. 
Should I move this to the dts and set this params only if they are present
in dts or also here check for compatible and set accordingly? 

> On 4/2/20 3:11 PM, Ansuel Smith wrote:
> > PARF programming was missing and this cause initilizzation problem on
> > some ipq806x based device (Netgear R7800 for example). This cause a
> > total lock of the system on kernel load.
> >
> > Fixes: 82a82383 PCI: qcom: Add Qualcomm PCIe controller driver
> > Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> > ---
> >  drivers/pci/controller/dwc/pcie-qcom.c | 48 +++++++++++++++++++++--
> ---
> >  1 file changed, 39 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c
> b/drivers/pci/controller/dwc/pcie-qcom.c
> > index 211a1aa7d0f1..77b1ab7e23a3 100644
> > --- a/drivers/pci/controller/dwc/pcie-qcom.c
> > +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> > @@ -46,6 +46,9 @@
> >
> >  #define PCIE20_PARF_PHY_CTRL			0x40
> >  #define PCIE20_PARF_PHY_REFCLK			0x4C
> > +#define REF_SSP_EN				BIT(16)
> > +#define REF_USE_PAD				BIT(12)
> 
> Could you rename this to:
> 
> PHY_REFCLK_SSP_EN
> PHY_REFCLK_USE_PAD
> 
> > +
> >  #define PCIE20_PARF_DBI_BASE_ADDR		0x168
> >  #define PCIE20_PARF_SLV_ADDR_SPACE_SIZE		0x16C
> >  #define PCIE20_PARF_MHI_CLOCK_RESET_CTRL	0x174
> > @@ -77,6 +80,18 @@
> >  #define DBI_RO_WR_EN				1
> >
> >  #define PERST_DELAY_US				1000
> > +/* PARF registers */
> > +#define PCIE20_PARF_PCS_DEEMPH			0x34
> > +#define PCS_DEEMPH_TX_DEEMPH_GEN1(x)		(x << 16)
> > +#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x)	(x << 8)
> > +#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x)	(x << 0)
> > +
> > +#define PCIE20_PARF_PCS_SWING			0x38
> > +#define PCS_SWING_TX_SWING_FULL(x)		(x << 8)
> > +#define PCS_SWING_TX_SWING_LOW(x)		(x << 0)
> > +
> > +#define PCIE20_PARF_CONFIG_BITS		0x50
> > +#define PHY_RX0_EQ(x)				(x << 24)
> >
> >  #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE	0x358
> >  #define SLV_ADDR_SPACE_SZ			0x10000000
> > @@ -184,6 +199,16 @@ struct qcom_pcie {
> >
> >  #define to_qcom_pcie(x)		dev_get_drvdata((x)->dev)
> >
> > +static inline void qcom_clear_and_set_dword(void __iomem *addr,
> 
> drop 'inline' the compiler is smart enough to decide.
> 
> > +				 u32 clear_mask, u32 set_mask)
> > +{
> > +	u32 val = readl(addr);
> > +
> > +	val &= ~clear_mask;
> > +	val |= set_mask;
> > +	writel(val, addr);
> > +}
> > +
> 
> If you add such function you should introduce it in a separate patch and
> use it in the whole driver where it is applicable. After that we can see
> what is the benefit of it.
> 
> >  static void qcom_ep_reset_assert(struct qcom_pcie *pcie)
> >  {
> >  	gpiod_set_value_cansleep(pcie->reset, 1);
> > @@ -304,7 +329,6 @@ static int qcom_pcie_init_2_1_0(struct
> qcom_pcie *pcie)
> >  	struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
> >  	struct dw_pcie *pci = pcie->pci;
> >  	struct device *dev = pci->dev;
> > -	u32 val;
> >  	int ret;
> >
> >  	ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res-
> >supplies);
> > @@ -355,15 +379,21 @@ static int qcom_pcie_init_2_1_0(struct
> qcom_pcie *pcie)
> >  		goto err_deassert_ahb;
> >  	}
> >
> > -	/* enable PCIe clocks and resets */
> > -	val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
> > -	val &= ~BIT(0);
> > -	writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
> > +	qcom_clear_and_set_dword(pcie->parf + PCIE20_PARF_PHY_CTRL,
> BIT(0), 0);
> 
> please keep the comment.
> 
> > +
> > +	/* PARF programming */
> 
> pointless comment, please drop it.
> 
> > +	writel(PCS_DEEMPH_TX_DEEMPH_GEN1(0x18) |
> > +	       PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(0x18) |
> > +	       PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(0x22),
> > +	       pcie->parf + PCIE20_PARF_PCS_DEEMPH);
> > +	writel(PCS_SWING_TX_SWING_FULL(0x78) |
> > +	       PCS_SWING_TX_SWING_LOW(0x78),
> > +	       pcie->parf + PCIE20_PARF_PCS_SWING);
> > +	writel(PHY_RX0_EQ(0x4), pcie->parf + PCIE20_PARF_CONFIG_BITS);
> >
> > -	/* enable external reference clock */
> > -	val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK);
> > -	val |= BIT(16);
> > -	writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK);
> > +	/* enable reference clock */
> 
> Why you dropped 'external' ?
> 
> > +	qcom_clear_and_set_dword(pcie->parf +
> PCIE20_PARF_PHY_REFCLK,
> > +		      REF_USE_PAD, REF_SSP_EN);
> >
> >  	ret = reset_control_deassert(res->phy_reset);
> >  	if (ret) {
> >
> 
> --
> regards,
> Stan

Re: R: [PATCH v2 07/10] PCIe: qcom: fix init problem with missing PARF programming

[Stanimir Varbanov]

Hi Ansuel,

On 4/8/20 3:38 PM, ansuelsmth@gmail.com wrote:
>> PARF programming
>>
>> Hi Ansuel,
>>
>> Please fix the patch subject for all patches in the series per Bjorn H.
>> request.
>>
>> PCI: qcom: Fix init problem with missing PARF programming
>>
>> Also the patch subject is misleading to me. Actually you change few phy
>> parameters: Tx De-Emphasis, Tx Swing and Rx equalization. On the other
>> side I guess those parameters are board specific and I'm not sure how
>> this change will reflect on apq8064 boards.
>>
> 
> I also think that this would brake apq8064, on ipq8064 this is needed or 
> the system doesn't boot. 
> Should I move this to the dts and set this params only if they are present
> in dts or also here check for compatible and set accordingly? 
> 

I also think that these phy params should be per board (and they are
tunable).

Maybe you can propose those as generic phy params in pci.txt binding
document and then we can ask DT maintainers for opinion. If they refuse
such generic bindings, we could switch to custom qcom,phy properties.

-- 
regards,
Stan

[PATCH v2 08/10] PCIe: qcom: add ipq8064 rev2 variant and set tx term offset

[Ansuel Smith]

From: Sham Muthayyan <smuthayy@codeaurora.org>

Add tx term offset support to pcie qcom driver need in some revision of
the ipq806x SoC.
Ipq8064 have tx term offset set to 7.
Ipq8064 v2 revision and ipq8065 have the tx term offset set to 0.

Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
 drivers/pci/controller/dwc/pcie-qcom.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 77b1ab7e23a3..8047ac7dc8c7 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -45,6 +45,9 @@
 #define PCIE_CAP_CPL_TIMEOUT_DISABLE		0x10
 
 #define PCIE20_PARF_PHY_CTRL			0x40
+#define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK	GENMASK(12, 16)
+#define PHY_CTRL_PHY_TX0_TERM_OFFSET(x)	(x << 16)
+
 #define PCIE20_PARF_PHY_REFCLK			0x4C
 #define REF_SSP_EN				BIT(16)
 #define REF_USE_PAD				BIT(12)
@@ -112,6 +115,7 @@ struct qcom_pcie_resources_2_1_0 {
 	struct reset_control *phy_reset;
 	struct reset_control *ext_reset;
 	struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY];
+	uint8_t phy_tx0_term_offset;
 };
 
 struct qcom_pcie_resources_1_0_0 {
@@ -302,6 +306,11 @@ static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie)
 	if (IS_ERR(res->ext_reset))
 		return PTR_ERR(res->ext_reset);
 
+	if (of_device_is_compatible(dev->of_node, "qcom,pcie-ipq8064"))
+		res->phy_tx0_term_offset = 7;
+	else
+		res->phy_tx0_term_offset = 0;
+
 	res->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
 	return PTR_ERR_OR_ZERO(res->phy_reset);
 }
@@ -381,6 +390,11 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
 
 	qcom_clear_and_set_dword(pcie->parf + PCIE20_PARF_PHY_CTRL, BIT(0), 0);
 
+	/* set TX termination offset */
+	qcom_clear_and_set_dword(pcie->parf + PCIE20_PARF_PHY_CTRL,
+			PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK,
+			PHY_CTRL_PHY_TX0_TERM_OFFSET(res->phy_tx0_term_offset));
+
 	/* PARF programming */
 	writel(PCS_DEEMPH_TX_DEEMPH_GEN1(0x18) |
 	       PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(0x18) |
@@ -1494,6 +1508,7 @@ static int qcom_pcie_probe(struct platform_device *pdev)
 static const struct of_device_id qcom_pcie_match[] = {
 	{ .compatible = "qcom,pcie-apq8084", .data = &ops_1_0_0 },
 	{ .compatible = "qcom,pcie-ipq8064", .data = &ops_2_1_0 },
+	{ .compatible = "qcom,pcie-ipq8064-v2", .data = &ops_2_1_0 },
 	{ .compatible = "qcom,pcie-apq8064", .data = &ops_2_1_0 },
 	{ .compatible = "qcom,pcie-msm8996", .data = &ops_2_3_2 },
 	{ .compatible = "qcom,pcie-ipq8074", .data = &ops_2_3_3 },
-- 
2.25.1

[PATCH v2 09/10] devicetree: bindings: pci: add ipq8064 rev 2 variant to qcom,pcie

[Ansuel Smith]

Document qcom,pcie-ipq8064-v2 needed to use different phy_tx0_term_offset.
In ipq8064 phy_tx0_term_offset is 7, in rev 2, ipq8065 and other SoC it's
set to 0 by default.

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
 .../devicetree/bindings/pci/qcom,pcie.txt     | 42 +++++++++++++++++++
 1 file changed, 42 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
index 6efcef040741..b699f126ea29 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
@@ -5,6 +5,7 @@
 	Value type: <stringlist>
 	Definition: Value should contain
 			- "qcom,pcie-ipq8064" for ipq8064
+			- "qcom,pcie-ipq8064-v2" for ipq8064 rev 2 or ipq8065
 			- "qcom,pcie-apq8064" for apq8064
 			- "qcom,pcie-apq8084" for apq8084
 			- "qcom,pcie-msm8996" for msm8996 or apq8096
@@ -295,6 +296,47 @@
 		pinctrl-names = "default";
 	};
 
+* Example for ipq8064 rev 2 or ipq8065
+	pcie@1b500000 {
+		compatible = "qcom,pcie-ipq8064-v2", "snps,dw-pcie";
+		reg = <0x1b500000 0x1000
+		       0x1b502000 0x80
+		       0x1b600000 0x100
+		       0x0ff00000 0x100000>;
+		reg-names = "dbi", "elbi", "parf", "config";
+		device_type = "pci";
+		linux,pci-domain = <0>;
+		bus-range = <0x00 0xff>;
+		num-lanes = <1>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000   /* I/O */
+			  0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */
+		interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
+		interrupt-names = "msi";
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 0x7>;
+		interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+				<0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+				<0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+				<0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+		clocks = <&gcc PCIE_A_CLK>,
+			 <&gcc PCIE_H_CLK>,
+			 <&gcc PCIE_PHY_CLK>,
+			 <&gcc PCIE_AUX_CLK>,
+			 <&gcc PCIE_ALT_REF_CLK>;
+		clock-names = "core", "iface", "phy", "aux", "ref";
+		resets = <&gcc PCIE_ACLK_RESET>,
+			 <&gcc PCIE_HCLK_RESET>,
+			 <&gcc PCIE_POR_RESET>,
+			 <&gcc PCIE_PCI_RESET>,
+			 <&gcc PCIE_PHY_RESET>,
+			 <&gcc PCIE_EXT_RESET>;
+		reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
+		pinctrl-0 = <&pcie_pins_default>;
+		pinctrl-names = "default";
+	};
+
 * Example for apq8084
 	pcie0@fc520000 {
 		compatible = "qcom,pcie-apq8084", "snps,dw-pcie";
-- 
2.25.1

Re: [PATCH v2 09/10] devicetree: bindings: pci: add ipq8064 rev 2 variant to qcom,pcie

[Rob Herring]

On Thu, Apr 02, 2020 at 02:11:46PM +0200, Ansuel Smith wrote:
> Document qcom,pcie-ipq8064-v2 needed to use different phy_tx0_term_offset.
> In ipq8064 phy_tx0_term_offset is 7, in rev 2, ipq8065 and other SoC it's
> set to 0 by default.
> 
> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> ---
>  .../devicetree/bindings/pci/qcom,pcie.txt     | 42 +++++++++++++++++++
>  1 file changed, 42 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
> index 6efcef040741..b699f126ea29 100644
> --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt
> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
> @@ -5,6 +5,7 @@
>  	Value type: <stringlist>
>  	Definition: Value should contain
>  			- "qcom,pcie-ipq8064" for ipq8064
> +			- "qcom,pcie-ipq8064-v2" for ipq8064 rev 2 or ipq8065
>  			- "qcom,pcie-apq8064" for apq8064
>  			- "qcom,pcie-apq8084" for apq8084
>  			- "qcom,pcie-msm8996" for msm8996 or apq8096
> @@ -295,6 +296,47 @@
>  		pinctrl-names = "default";
>  	};
>  
> +* Example for ipq8064 rev 2 or ipq8065

Just a new compatible string doesn't warrant a whole new example.

> +	pcie@1b500000 {
> +		compatible = "qcom,pcie-ipq8064-v2", "snps,dw-pcie";
> +		reg = <0x1b500000 0x1000
> +		       0x1b502000 0x80
> +		       0x1b600000 0x100
> +		       0x0ff00000 0x100000>;
> +		reg-names = "dbi", "elbi", "parf", "config";
> +		device_type = "pci";
> +		linux,pci-domain = <0>;
> +		bus-range = <0x00 0xff>;
> +		num-lanes = <1>;
> +		#address-cells = <3>;
> +		#size-cells = <2>;
> +		ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000   /* I/O */
> +			  0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */
> +		interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
> +		interrupt-names = "msi";
> +		#interrupt-cells = <1>;
> +		interrupt-map-mask = <0 0 0 0x7>;
> +		interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
> +				<0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
> +				<0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
> +				<0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
> +		clocks = <&gcc PCIE_A_CLK>,
> +			 <&gcc PCIE_H_CLK>,
> +			 <&gcc PCIE_PHY_CLK>,
> +			 <&gcc PCIE_AUX_CLK>,
> +			 <&gcc PCIE_ALT_REF_CLK>;
> +		clock-names = "core", "iface", "phy", "aux", "ref";
> +		resets = <&gcc PCIE_ACLK_RESET>,
> +			 <&gcc PCIE_HCLK_RESET>,
> +			 <&gcc PCIE_POR_RESET>,
> +			 <&gcc PCIE_PCI_RESET>,
> +			 <&gcc PCIE_PHY_RESET>,
> +			 <&gcc PCIE_EXT_RESET>;
> +		reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
> +		pinctrl-0 = <&pcie_pins_default>;
> +		pinctrl-names = "default";
> +	};
> +
>  * Example for apq8084
>  	pcie0@fc520000 {
>  		compatible = "qcom,pcie-apq8084", "snps,dw-pcie";
> -- 
> 2.25.1
> 

[PATCH v2 10/10] PCIe: qcom: add Force GEN1 support

[Ansuel Smith]

From: Sham Muthayyan <smuthayy@codeaurora.org>

Add Force GEN1 support needed in some ipq806x board
that needs to limit some pcie line to gen1 for some
hardware limitation.
This is set by the max-link-speed dts entry and needed
by some soc based on ipq806x. (for example Netgear R7800
router)

Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
 drivers/pci/controller/dwc/pcie-qcom.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 8047ac7dc8c7..2212e9498b91 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -27,6 +27,7 @@
 #include <linux/slab.h>
 #include <linux/types.h>
 
+#include "../../pci.h"
 #include "pcie-designware.h"
 
 #define PCIE20_PARF_SYS_CTRL			0x00
@@ -99,6 +100,8 @@
 #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE	0x358
 #define SLV_ADDR_SPACE_SZ			0x10000000
 
+#define PCIE20_LNK_CONTROL2_LINK_STATUS2        0xA0
+
 #define DEVICE_TYPE_RC				0x4
 
 #define QCOM_PCIE_2_1_0_MAX_SUPPLY	3
@@ -199,6 +202,7 @@ struct qcom_pcie {
 	struct phy *phy;
 	struct gpio_desc *reset;
 	const struct qcom_pcie_ops *ops;
+	bool force_gen1;
 };
 
 #define to_qcom_pcie(x)		dev_get_drvdata((x)->dev)
@@ -441,6 +445,11 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
 
 	/* wait for clock acquisition */
 	usleep_range(1000, 1500);
+	if (pcie->force_gen1) {
+		writel_relaxed((readl_relaxed(
+		  pcie->pci->dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2) | 1),
+		  pcie->pci->dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2);
+	}
 
 
 	/* Set the Max TLP size to 2K, instead of using default of 4K */
@@ -1440,6 +1449,10 @@ static int qcom_pcie_probe(struct platform_device *pdev)
 		goto err_pm_runtime_put;
 	}
 
+	ret = of_pci_get_max_link_speed(pdev->dev.of_node);
+	if (ret == 1)
+		pcie->force_gen1 = true;
+
 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "parf");
 	pcie->parf = devm_ioremap_resource(dev, res);
 	if (IS_ERR(pcie->parf)) {
-- 
2.25.1

Re: [PATCH v2 10/10] PCIe: qcom: add Force GEN1 support

[Stanimir Varbanov]

Hi Ansuel,

On 4/2/20 3:11 PM, Ansuel Smith wrote:
> From: Sham Muthayyan <smuthayy@codeaurora.org>
> 
> Add Force GEN1 support needed in some ipq806x board
> that needs to limit some pcie line to gen1 for some
> hardware limitation.
> This is set by the max-link-speed dts entry and needed
> by some soc based on ipq806x. (for example Netgear R7800
> router)
> 
> Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> ---
>  drivers/pci/controller/dwc/pcie-qcom.c | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index 8047ac7dc8c7..2212e9498b91 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -27,6 +27,7 @@
>  #include <linux/slab.h>
>  #include <linux/types.h>
>  
> +#include "../../pci.h"

This looks suspiciously (even ugly), but I saw that the other users of
of_pci_get_max_link_speed is doing the same.

Bjorn H. : do you know why the prototype is there? Perhaps it must be in
linux/of_pci.h.

>  #include "pcie-designware.h"
>  
>  #define PCIE20_PARF_SYS_CTRL			0x00
> @@ -99,6 +100,8 @@
>  #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE	0x358
>  #define SLV_ADDR_SPACE_SZ			0x10000000
>  
> +#define PCIE20_LNK_CONTROL2_LINK_STATUS2        0xA0

tabs instead of spaces and hex numbers should be lower-case

> +
>  #define DEVICE_TYPE_RC				0x4
>  
>  #define QCOM_PCIE_2_1_0_MAX_SUPPLY	3
> @@ -199,6 +202,7 @@ struct qcom_pcie {
>  	struct phy *phy;
>  	struct gpio_desc *reset;
>  	const struct qcom_pcie_ops *ops;
> +	bool force_gen1;

could you rename this and make it int:

	int gen;

>  };
>  
>  #define to_qcom_pcie(x)		dev_get_drvdata((x)->dev)
> @@ -441,6 +445,11 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
>  
>  	/* wait for clock acquisition */
>  	usleep_range(1000, 1500);

add a blank line here

> +	if (pcie->force_gen1) {

	if (pcie->gen == 1) {

> +		writel_relaxed((readl_relaxed(
> +		  pcie->pci->dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2) | 1),
> +		  pcie->pci->dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2);
> +	}

why you are using writel/readl_relaxed ?

Also could you split the line to two:

	val = read()
	write(val | 1, address)

>  
>  
>  	/* Set the Max TLP size to 2K, instead of using default of 4K */
> @@ -1440,6 +1449,10 @@ static int qcom_pcie_probe(struct platform_device *pdev)
>  		goto err_pm_runtime_put;
>  	}
>  
> +	ret = of_pci_get_max_link_speed(pdev->dev.of_node);> +	if (ret == 1)
> +		pcie->force_gen1 = true;

drop this, handle ret < 0 and default to generation 2

	pcie->gen = of_pci_get_max_link_speed(pdev->dev.of_node);
	if (pcie->gen < 0)
		pcie->gen = 2;

> +
>  	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "parf");
>  	pcie->parf = devm_ioremap_resource(dev, res);
>  	if (IS_ERR(pcie->parf)) {
> 

-- 
regards,
Stan

Re: [PATCH v2 10/10] PCIe: qcom: add Force GEN1 support

[Rob Herring]

On Fri, Apr 03, 2020 at 12:01:01PM +0300, Stanimir Varbanov wrote:
> Hi Ansuel,
> 
> On 4/2/20 3:11 PM, Ansuel Smith wrote:
> > From: Sham Muthayyan <smuthayy@codeaurora.org>
> > 
> > Add Force GEN1 support needed in some ipq806x board
> > that needs to limit some pcie line to gen1 for some
> > hardware limitation.
> > This is set by the max-link-speed dts entry and needed
> > by some soc based on ipq806x. (for example Netgear R7800
> > router)
> > 
> > Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
> > Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
> > ---
> >  drivers/pci/controller/dwc/pcie-qcom.c | 13 +++++++++++++
> >  1 file changed, 13 insertions(+)
> > 
> > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> > index 8047ac7dc8c7..2212e9498b91 100644
> > --- a/drivers/pci/controller/dwc/pcie-qcom.c
> > +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> > @@ -27,6 +27,7 @@
> >  #include <linux/slab.h>
> >  #include <linux/types.h>
> >  
> > +#include "../../pci.h"
> 
> This looks suspiciously (even ugly), but I saw that the other users of
> of_pci_get_max_link_speed is doing the same.
> 
> Bjorn H. : do you know why the prototype is there? Perhaps it must be in
> linux/of_pci.h.

No, because the function should not be used outside of drivers/pci/.

Rob

Re: [PATCH v2 00/10] Multiple fixes in PCIe qcom driver

[Stanimir Varbanov]

Hi Ansuel,

Please run "checkpatch --strict" for the next version.

On 4/2/20 3:11 PM, Ansuel Smith wrote:
> This contains multiple fix for PCIe qcom driver.
> Some optional reset and clocks were missing.
> Fix a problem with no PARF programming that cause kernel lock on load.
> Add support to force gen 1 speed if needed. (due to hardware limitation)
> Add ipq8064 rev 2 support that use a different tx termination offset.
> 
> v2:
> * Drop iATU programming (already done in pcie init)
> * Use max-link-speed instead of force-gen1 custom definition
> * Drop MRRS to 256B (Can't find a realy reason why this was suggested)
> * Introduce a new variant for different revision of ipq8064
> 
> Abhishek Sahu (1):
>   PCIe: qcom: change duplicate PCI reset to phy reset
> 
> Ansuel Smith (7):
>   PCIe: qcom: add missing ipq806x clocks in PCIe driver
>   devicetree: bindings: pci: add missing clks to qcom,pcie
>   PCIe: qcom: Fixed pcie_phy_clk branch issue
>   PCIe: qcom: add missing reset for ipq806x
>   devicetree: bindings: pci: add ext reset to qcom,pcie
>   PCIe: qcom: fix init problem with missing PARF programming
>   devicetree: bindings: pci: add ipq8064 rev 2 variant to qcom,pcie
> 
> Sham Muthayyan (2):
>   PCIe: qcom: add ipq8064 rev2 variant and set tx term offset
>   PCIe: qcom: add Force GEN1 support
> 
>  .../devicetree/bindings/pci/qcom,pcie.txt     |  56 +++++++-
>  drivers/pci/controller/dwc/pcie-qcom.c        | 134 +++++++++++++++---
>  2 files changed, 167 insertions(+), 23 deletions(-)
> 

-- 
regards,
Stan