From: "Sanghoon Bae" <sh86.bae@samsung.com>
To: "'Krzysztof Kozlowski'" <krzk@kernel.org>, <robh@kernel.org>,
<conor+dt@kernel.org>, <vkoul@kernel.org>,
<alim.akhtar@samsung.com>, <kishon@kernel.org>,
<m.szyprowski@samsung.com>, <jh80.chung@samsung.com>,
<shradha.t@samsung.com>
Cc: <krzk+dt@kernel.org>, <linux-kernel@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-samsung-soc@vger.kernel.org>,
<linux-phy@lists.infradead.org>,
<linux-arm-kernel@lists.infradead.org>
Subject: RE: [PATCH 2/4] dt-bindings: phy: Add PCIe PHY support for ExynosAutov920 SoC
Date: Fri, 14 Nov 2025 15:05:16 +0900 [thread overview]
Message-ID: <000601dc552c$a63e6060$f2bb2120$@samsung.com> (raw)
In-Reply-To: <649f8e90-d99b-401a-bb0f-ef0cf9c4fe7f@kernel.org>
> > Since the Exynosautov920 SoC uses the Samsung PCIe PHY, add support
> > for it in the Exynosautov920 PCIe PHY bindings.
> >
> > The Exynosautov920 SoC includes two PHY instances: one for a 4-lane
> > PHY and another for a 2-lane PHY. Each PHY can be used by separate
> > controllers through the bifurcation option. Therefore, from 2 up to 4
> > PCIe controllers can be supported and connected with this PHY driver.
>
>
> Describe hardware, not driver.
I will describe about the Exynosautov920 SoC PCIe hardware.
> > PCIe lane number is used to distinguish each PHY instance.
> > This is required since two PHY instances on ExynosAutov920 is not
> > identical.
> > On PHY driver code, need to check each instance and different settings.
>
>
> Describe hardware, not driver.
I will describe about the Exynosautov920 SoC PCIe hardware.
> > @@ -19,6 +19,7 @@ properties:
> > - samsung,exynos5433-pcie-phy
> > - tesla,fsd-pcie-phy0
> > - tesla,fsd-pcie-phy1
> > + - samsung,exynosautov920-pcie-phy
>
> Messed order.
Will fix the order
> > @@ -42,6 +47,7 @@ allOf:
> > enum:
> > - tesla,fsd-pcie-phy0
> > - tesla,fsd-pcie-phy1
> > + - samsung,exynosautov920-pcie-phy
>
> Messed order.
Will fix the order
WARNING: multiple messages have this Message-ID (diff)
From: "Sanghoon Bae" <sh86.bae@samsung.com>
To: "'Krzysztof Kozlowski'" <krzk@kernel.org>, <robh@kernel.org>,
<conor+dt@kernel.org>, <vkoul@kernel.org>,
<alim.akhtar@samsung.com>, <kishon@kernel.org>,
<m.szyprowski@samsung.com>, <jh80.chung@samsung.com>,
<shradha.t@samsung.com>
Cc: <krzk+dt@kernel.org>, <linux-kernel@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-samsung-soc@vger.kernel.org>,
<linux-phy@lists.infradead.org>,
<linux-arm-kernel@lists.infradead.org>
Subject: RE: [PATCH 2/4] dt-bindings: phy: Add PCIe PHY support for ExynosAutov920 SoC
Date: Fri, 14 Nov 2025 15:05:16 +0900 [thread overview]
Message-ID: <000601dc552c$a63e6060$f2bb2120$@samsung.com> (raw)
In-Reply-To: <649f8e90-d99b-401a-bb0f-ef0cf9c4fe7f@kernel.org>
> > Since the Exynosautov920 SoC uses the Samsung PCIe PHY, add support
> > for it in the Exynosautov920 PCIe PHY bindings.
> >
> > The Exynosautov920 SoC includes two PHY instances: one for a 4-lane
> > PHY and another for a 2-lane PHY. Each PHY can be used by separate
> > controllers through the bifurcation option. Therefore, from 2 up to 4
> > PCIe controllers can be supported and connected with this PHY driver.
>
>
> Describe hardware, not driver.
I will describe about the Exynosautov920 SoC PCIe hardware.
> > PCIe lane number is used to distinguish each PHY instance.
> > This is required since two PHY instances on ExynosAutov920 is not
> > identical.
> > On PHY driver code, need to check each instance and different settings.
>
>
> Describe hardware, not driver.
I will describe about the Exynosautov920 SoC PCIe hardware.
> > @@ -19,6 +19,7 @@ properties:
> > - samsung,exynos5433-pcie-phy
> > - tesla,fsd-pcie-phy0
> > - tesla,fsd-pcie-phy1
> > + - samsung,exynosautov920-pcie-phy
>
> Messed order.
Will fix the order
> > @@ -42,6 +47,7 @@ allOf:
> > enum:
> > - tesla,fsd-pcie-phy0
> > - tesla,fsd-pcie-phy1
> > + - samsung,exynosautov920-pcie-phy
>
> Messed order.
Will fix the order
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
next prev parent reply other threads:[~2025-11-14 6:05 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20250926073954epcas2p4b8bb4206e526b7d7860ed4378ed75f78@epcas2p4.samsung.com>
2025-09-26 7:39 ` [PATCH 0/4] Add support for ExynosAutov920 PCIe PHY Sanghoon Bae
2025-09-26 7:39 ` Sanghoon Bae
2025-09-26 7:39 ` [PATCH 1/4] dt-bindings: soc: samsung: exynos-sysreg: add hsi0 for ExynosAutov920 Sanghoon Bae
2025-09-26 7:39 ` Sanghoon Bae
2025-10-07 6:28 ` Krzysztof Kozlowski
2025-10-07 6:28 ` Krzysztof Kozlowski
2025-11-14 5:36 ` 배상훈/Sanghoon Bae
2025-11-14 5:36 ` 배상훈/Sanghoon Bae
2025-09-26 7:39 ` [PATCH 2/4] dt-bindings: phy: Add PCIe PHY support for ExynosAutov920 SoC Sanghoon Bae
2025-09-26 7:39 ` Sanghoon Bae
2025-10-07 6:29 ` Krzysztof Kozlowski
2025-10-07 6:29 ` Krzysztof Kozlowski
2025-11-14 6:05 ` Sanghoon Bae [this message]
2025-11-14 6:05 ` Sanghoon Bae
2025-09-26 7:39 ` [PATCH 3/4] arm64: dts: ExynosAutov920: add PCIe PHY DT nodes Sanghoon Bae
2025-09-26 7:39 ` Sanghoon Bae
2025-10-07 6:32 ` Krzysztof Kozlowski
2025-10-07 6:32 ` Krzysztof Kozlowski
2025-11-14 6:57 ` SanghoonBae
2025-11-14 6:57 ` SanghoonBae
2025-09-26 7:39 ` [PATCH 4/4] phy: exynos: Add PCIe PHY support for ExynosAutov920 SoC Sanghoon Bae
2025-09-26 7:39 ` Sanghoon Bae
2025-09-26 7:39 ` [PATCH 0/4] Add support for ExynosAutov920 PCIe PHY Sanghoon Bae
2025-09-26 7:39 ` Sanghoon Bae
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