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From: "Sricharan" <sricharan@codeaurora.org>
To: 'Rajendra Nayak' <rnayak@codeaurora.org>,
	'Stephen Boyd' <sboyd@codeaurora.org>
Cc: mturquette@baylibre.com, linux-clk@vger.kernel.org,
	linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
	stanimir.varbanov@linaro.org
Subject: RE: [PATCH 3/3] clk: qcom: Set BRANCH_HALT_DELAY flags for venus core0/1 clks
Date: Thu, 10 Nov 2016 08:58:13 +0530	[thread overview]
Message-ID: <001701d23b02$7bf7daa0$73e78fe0$@codeaurora.org> (raw)
In-Reply-To: <5823DC3E.2060106@codeaurora.org>

Hi Rajendra,
>
>>>
>>> The proper sequence sounds like it should be:
>>>
>>> 	1. Enable GDSC for main domain
>>> 	2. Enable clocks for main domain (video_{core,maxi,ahb,axi}_clk)
>>> 	3. Write the two registers to assert hw signal for subdomains
>>> 	4. Enable GDSCs for two subdomains
>>> 	5. Enable clocks for subdomains (video_subcore{0,1}_clk)
>>>
>[]..
>
>>
>> So the above is the sequence which is actually carried out on the
>> firmware side. The same can be done in host as well.
>
>By the 'above sequence is done on firmware side', I hope you don;t mean *all* 5 steps.
>I guess you mean only step 3 is done by firmware?
>

Yes, only step 3.

Regards,
 Sricharan

WARNING: multiple messages have this Message-ID (diff)
From: "Sricharan" <sricharan@codeaurora.org>
To: "'Rajendra Nayak'" <rnayak@codeaurora.org>,
	"'Stephen Boyd'" <sboyd@codeaurora.org>
Cc: <mturquette@baylibre.com>, <linux-clk@vger.kernel.org>,
	<linux-arm-msm@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<stanimir.varbanov@linaro.org>
Subject: RE: [PATCH 3/3] clk: qcom: Set BRANCH_HALT_DELAY flags for venus core0/1 clks
Date: Thu, 10 Nov 2016 08:58:13 +0530	[thread overview]
Message-ID: <001701d23b02$7bf7daa0$73e78fe0$@codeaurora.org> (raw)
In-Reply-To: <5823DC3E.2060106@codeaurora.org>

Hi Rajendra,
>
>>>
>>> The proper sequence sounds like it should be:
>>>
>>> 	1. Enable GDSC for main domain
>>> 	2. Enable clocks for main domain (video_{core,maxi,ahb,axi}_clk)
>>> 	3. Write the two registers to assert hw signal for subdomains
>>> 	4. Enable GDSCs for two subdomains
>>> 	5. Enable clocks for subdomains (video_subcore{0,1}_clk)
>>>
>[]..
>
>>
>> So the above is the sequence which is actually carried out on the
>> firmware side. The same can be done in host as well.
>
>By the 'above sequence is done on firmware side', I hope you don;t mean *all* 5 steps.
>I guess you mean only step 3 is done by firmware?
>

Yes, only step 3.

Regards,
 Sricharan

  reply	other threads:[~2016-11-10  3:28 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-10-24 10:18 [PATCH 0/3] clk: qcom: Add support for hw controlled gdscs/clocks Sricharan R
2016-10-24 10:18 ` [PATCH 1/3] clk: qcom: gdsc: Add support for gdscs with HW control Sricharan R
2016-10-25 13:01   ` Stanimir Varbanov
2016-10-26  4:12     ` Sricharan
2016-10-26  4:12       ` Sricharan
2016-11-02  0:18   ` Stephen Boyd
2016-11-02  6:50     ` Sricharan
2016-11-02  6:50       ` Sricharan
2016-11-02  6:53       ` Sricharan
2016-11-02  6:53         ` Sricharan
2016-11-02 17:59       ` 'Stephen Boyd'
2016-11-03 13:30         ` Sricharan
2016-11-03 13:30           ` Sricharan
2016-11-03 20:05           ` 'Stephen Boyd'
2016-10-24 10:18 ` [PATCH 2/3] clk: qcom: Put venus core0/1 gdscs to hw control mode Sricharan R
2016-10-24 10:18 ` [PATCH 3/3] clk: qcom: Set BRANCH_HALT_DELAY flags for venus core0/1 clks Sricharan R
2016-11-03 20:34   ` Stephen Boyd
2016-11-04  9:09     ` Sricharan
2016-11-04  9:09       ` Sricharan
2016-11-04 20:18       ` 'Stephen Boyd'
2016-11-07  5:48         ` Rajendra Nayak
2016-11-08 22:33           ` 'Stephen Boyd'
2016-11-09 16:56             ` Sricharan
2016-11-09 16:56               ` Sricharan
2016-11-10  2:32               ` Rajendra Nayak
2016-11-10  3:28                 ` Sricharan [this message]
2016-11-10  3:28                   ` Sricharan
2016-11-10 23:30               ` 'Stephen Boyd'
2016-11-14  3:51                 ` Sricharan
2016-11-14  3:51                   ` Sricharan
2016-12-12 15:40             ` Stanimir Varbanov

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