* [PATCH v4 0/2] Add support for sc7280 WPSS PIL loading @ 2021-09-17 10:35 Rakesh Pillai 2021-09-17 10:35 ` [PATCH v4 1/2] dt-bindings: remoteproc: qcom: Add SC7280 WPSS support Rakesh Pillai 2021-09-17 10:35 ` [PATCH v4 2/2] remoteproc: qcom: q6v5_wpss: Add support for sc7280 WPSS Rakesh Pillai 0 siblings, 2 replies; 6+ messages in thread From: Rakesh Pillai @ 2021-09-17 10:35 UTC (permalink / raw) To: agross, bjorn.andersson, ohad, mathieu.poirier, robh+dt, p.zabel Cc: swboyd, linux-arm-msm, devicetree, linux-kernel, sibis, mpubbise, kuabhs, Rakesh Pillai Add support for PIL loading of WPSS co-processor for SC7280 SOCs. Changes from v3: - Add separate dt-bindings file for sc7280-wpss-pil - Fix the handling of single power domains for adsp/cdsp from v3 Rakesh Pillai (2): dt-bindings: remoteproc: qcom: Add SC7280 WPSS support remoteproc: qcom: q6v5_wpss: Add support for sc7280 WPSS .../bindings/remoteproc/qcom,sc7280-wpss-pil.yaml | 198 +++++++++++++++++++ drivers/remoteproc/qcom_q6v5_adsp.c | 209 +++++++++++++++++++-- 2 files changed, 392 insertions(+), 15 deletions(-) create mode 100644 Documentation/devicetree/bindings/remoteproc/qcom,sc7280-wpss-pil.yaml -- 2.7.4 ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v4 1/2] dt-bindings: remoteproc: qcom: Add SC7280 WPSS support 2021-09-17 10:35 [PATCH v4 0/2] Add support for sc7280 WPSS PIL loading Rakesh Pillai @ 2021-09-17 10:35 ` Rakesh Pillai 2021-09-20 19:58 ` Stephen Boyd 2021-09-22 17:28 ` Rob Herring 2021-09-17 10:35 ` [PATCH v4 2/2] remoteproc: qcom: q6v5_wpss: Add support for sc7280 WPSS Rakesh Pillai 1 sibling, 2 replies; 6+ messages in thread From: Rakesh Pillai @ 2021-09-17 10:35 UTC (permalink / raw) To: agross, bjorn.andersson, ohad, mathieu.poirier, robh+dt, p.zabel Cc: swboyd, linux-arm-msm, devicetree, linux-kernel, sibis, mpubbise, kuabhs, Rakesh Pillai Add WPSS PIL loading support for SC7280 SoCs. Signed-off-by: Rakesh Pillai <pillair@codeaurora.org> --- .../bindings/remoteproc/qcom,sc7280-wpss-pil.yaml | 198 +++++++++++++++++++++ 1 file changed, 198 insertions(+) create mode 100644 Documentation/devicetree/bindings/remoteproc/qcom,sc7280-wpss-pil.yaml diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-wpss-pil.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-wpss-pil.yaml new file mode 100644 index 0000000..896d5f47 --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-wpss-pil.yaml @@ -0,0 +1,198 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/qcom,sc7280-wpss-pil.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SC7280 WPSS Peripheral Image Loader + +maintainers: + - Bjorn Andersson <bjorn.andersson@linaro.org> + +description: + This document defines the binding for a component that loads and boots firmware + on the Qualcomm Technology Inc. WPSS. + +properties: + compatible: + enum: + - qcom,sc7280-wpss-pil + + reg: + maxItems: 1 + description: + The base address and size of the qdsp6ss register + + interrupts-extended: + minItems: 6 + items: + - description: Watchdog interrupt + - description: Fatal interrupt + - description: Ready interrupt + - description: Handover interrupt + - description: Stop acknowledge interrupt + - description: Shutdown acknowledge interrupt + + interrupt-names: + minItems: 6 + items: + - const: wdog + - const: fatal + - const: ready + - const: handover + - const: stop-ack + - const: shutdown-ack + + clocks: + minItems: 4 + items: + - description: GCC WPSS AHB BDG Master clock + - description: GCC WPSS AHB clock + - description: GCC WPSS RSCP clock + - description: XO clock + + clock-names: + minItems: 4 + items: + - const: gcc_wpss_ahb_bdg_mst_clk + - const: gcc_wpss_ahb_clk + - const: gcc_wpss_rscp_clk + - const: xo + + power-domains: + minItems: 2 + items: + - description: CX power domain + - description: MX power domain + + power-domain-names: + minItems: 2 + items: + - const: cx + - const: mx + + resets: + minItems: 2 + items: + - description: AOSS restart + - description: PDC SYNC + + reset-names: + minItems: 2 + items: + - const: restart + - const: pdc_sync + + memory-region: + maxItems: 1 + description: Reference to the reserved-memory for the Hexagon core + + qcom,halt-regs: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + Phandle reference to a syscon representing TCSR followed by the + three offsets within syscon for q6, modem and nc halt registers. + + qcom,qmp: + $ref: /schemas/types.yaml#/definitions/phandle + description: Reference to the AOSS side-channel message RAM. + + qcom,smem-states: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: States used by the AP to signal the Hexagon core + items: + - description: Stop the modem + + qcom,smem-state-names: + $ref: /schemas/types.yaml#/definitions/string-array + description: The names of the state bits used for SMP2P output + items: + - const: stop + + glink-edge: + type: object + description: + Qualcomm G-Link subnode which represents communication edge, channels + and devices related to the ADSP. + +required: + - compatible + - reg + - interrupts-extended + - interrupt-names + - clocks + - clock-names + - power-domains + - power-domain-names + - reset + - reset-names + - qcom,halt-regs + - memory-region + - qcom,qmp + - qcom,smem-states + - qcom,smem-state-names + - glink-edge + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/qcom,gcc-sc7280.h> + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/power/qcom-rpmpd.h> + #include <dt-bindings/reset/qcom,sdm845-aoss.h> + #include <dt-bindings/reset/qcom,sdm845-pdc.h> + #include <dt-bindings/mailbox/qcom-ipcc.h> + remoteproc@8a00000 { + compatible = "qcom,sc7280-wpss-pil"; + reg = <0x08a00000 0x10000>; + + interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>, + <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", "handover", + "stop-ack", "shutdown-ack"; + + clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>, + <&gcc GCC_WPSS_AHB_CLK>, + <&gcc GCC_WPSS_RSCP_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "gcc_wpss_ahb_bdg_mst_clk", + "gcc_wpss_ahb_clk", + "gcc_wpss_rscp_clk", + "xo"; + + power-domains = <&rpmhpd SC7280_CX>, + <&rpmhpd SC7280_MX>; + power-domain-names = "cx", "mx"; + + memory-region = <&wpss_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&wpss_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + resets = <&aoss_reset AOSS_CC_WCSS_RESTART>, + <&pdc_reset PDC_WPSS_SYNC_RESET>; + reset-names = "restart", "pdc_sync"; + + qcom,halt-regs = <&tcsr_mutex 0x37000>; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_WPSS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_WPSS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "wpss"; + qcom,remote-pid = <13>; + }; + }; -- 2.7.4 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v4 1/2] dt-bindings: remoteproc: qcom: Add SC7280 WPSS support 2021-09-17 10:35 ` [PATCH v4 1/2] dt-bindings: remoteproc: qcom: Add SC7280 WPSS support Rakesh Pillai @ 2021-09-20 19:58 ` Stephen Boyd 2021-09-22 17:28 ` Rob Herring 1 sibling, 0 replies; 6+ messages in thread From: Stephen Boyd @ 2021-09-20 19:58 UTC (permalink / raw) To: Rakesh Pillai, agross, bjorn.andersson, mathieu.poirier, ohad, p.zabel, robh+dt Cc: linux-arm-msm, devicetree, linux-kernel, sibis, mpubbise, kuabhs Quoting Rakesh Pillai (2021-09-17 03:35:40) > Add WPSS PIL loading support for SC7280 SoCs. > > Signed-off-by: Rakesh Pillai <pillair@codeaurora.org> > --- > .../bindings/remoteproc/qcom,sc7280-wpss-pil.yaml | 198 +++++++++++++++++++++ > 1 file changed, 198 insertions(+) > create mode 100644 Documentation/devicetree/bindings/remoteproc/qcom,sc7280-wpss-pil.yaml > > diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-wpss-pil.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-wpss-pil.yaml > new file mode 100644 > index 0000000..896d5f47 > --- /dev/null > +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-wpss-pil.yaml > @@ -0,0 +1,198 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/remoteproc/qcom,sc7280-wpss-pil.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm SC7280 WPSS Peripheral Image Loader Maybe spell out WPSS so we know what the acronym means? > + > +maintainers: > + - Bjorn Andersson <bjorn.andersson@linaro.org> > + > +description: > + This document defines the binding for a component that loads and boots firmware > + on the Qualcomm Technology Inc. WPSS. > + > +properties: > + compatible: > + enum: > + - qcom,sc7280-wpss-pil > + > + reg: > + maxItems: 1 > + description: > + The base address and size of the qdsp6ss register > + > + interrupts-extended: > + minItems: 6 > + items: > + - description: Watchdog interrupt > + - description: Fatal interrupt > + - description: Ready interrupt > + - description: Handover interrupt > + - description: Stop acknowledge interrupt > + - description: Shutdown acknowledge interrupt > + > + interrupt-names: > + minItems: 6 > + items: > + - const: wdog > + - const: fatal > + - const: ready > + - const: handover > + - const: stop-ack > + - const: shutdown-ack > + > + clocks: > + minItems: 4 > + items: > + - description: GCC WPSS AHB BDG Master clock > + - description: GCC WPSS AHB clock > + - description: GCC WPSS RSCP clock > + - description: XO clock > + > + clock-names: > + minItems: 4 > + items: > + - const: gcc_wpss_ahb_bdg_mst_clk > + - const: gcc_wpss_ahb_clk > + - const: gcc_wpss_rscp_clk > + - const: xo > + > + power-domains: > + minItems: 2 > + items: > + - description: CX power domain > + - description: MX power domain > + > + power-domain-names: > + minItems: 2 > + items: > + - const: cx > + - const: mx > + > + resets: > + minItems: 2 > + items: > + - description: AOSS restart > + - description: PDC SYNC > + > + reset-names: > + minItems: 2 > + items: > + - const: restart > + - const: pdc_sync > + > + memory-region: > + maxItems: 1 > + description: Reference to the reserved-memory for the Hexagon core > + > + qcom,halt-regs: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + description: > + Phandle reference to a syscon representing TCSR followed by the > + three offsets within syscon for q6, modem and nc halt registers. > + > + qcom,qmp: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: Reference to the AOSS side-channel message RAM. > + > + qcom,smem-states: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + description: States used by the AP to signal the Hexagon core > + items: > + - description: Stop the modem > + > + qcom,smem-state-names: > + $ref: /schemas/types.yaml#/definitions/string-array > + description: The names of the state bits used for SMP2P output > + items: > + - const: stop > + > + glink-edge: > + type: object > + description: > + Qualcomm G-Link subnode which represents communication edge, channels > + and devices related to the ADSP. Are there any required properties of glink-edge? Or an empty node is all that's required? Maybe there's a binding that can be referenced here that describes the required properties? > + > +required: > + - compatible > + - reg > + - interrupts-extended > + - interrupt-names Why is interrupt-names required? > + - clocks > + - clock-names > + - power-domains > + - power-domain-names > + - reset > + - reset-names > + - qcom,halt-regs > + - memory-region > + - qcom,qmp > + - qcom,smem-states > + - qcom,smem-state-names > + - glink-edge > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/clock/qcom,gcc-sc7280.h> > + #include <dt-bindings/clock/qcom,rpmh.h> > + #include <dt-bindings/power/qcom-rpmpd.h> > + #include <dt-bindings/reset/qcom,sdm845-aoss.h> > + #include <dt-bindings/reset/qcom,sdm845-pdc.h> > + #include <dt-bindings/mailbox/qcom-ipcc.h> > + remoteproc@8a00000 { > + compatible = "qcom,sc7280-wpss-pil"; > + reg = <0x08a00000 0x10000>; > + > + interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>, > + <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, > + <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, > + <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, > + <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, > + <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; > + interrupt-names = "wdog", "fatal", "ready", "handover", > + "stop-ack", "shutdown-ack"; > + > + clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>, > + <&gcc GCC_WPSS_AHB_CLK>, > + <&gcc GCC_WPSS_RSCP_CLK>, > + <&rpmhcc RPMH_CXO_CLK>; > + clock-names = "gcc_wpss_ahb_bdg_mst_clk", > + "gcc_wpss_ahb_clk", > + "gcc_wpss_rscp_clk", > + "xo"; > + > + power-domains = <&rpmhpd SC7280_CX>, > + <&rpmhpd SC7280_MX>; > + power-domain-names = "cx", "mx"; > + > + memory-region = <&wpss_mem>; > + > + qcom,qmp = <&aoss_qmp>; > + > + qcom,smem-states = <&wpss_smp2p_out 0>; > + qcom,smem-state-names = "stop"; > + > + resets = <&aoss_reset AOSS_CC_WCSS_RESTART>, > + <&pdc_reset PDC_WPSS_SYNC_RESET>; > + reset-names = "restart", "pdc_sync"; > + > + qcom,halt-regs = <&tcsr_mutex 0x37000>; > + > + status = "disabled"; Can we remove status = "disabled" from the example? It provides no value. > + > + glink-edge { > + interrupts-extended = <&ipcc IPCC_CLIENT_WPSS > + IPCC_MPROC_SIGNAL_GLINK_QMP > + IRQ_TYPE_EDGE_RISING>; > + mboxes = <&ipcc IPCC_CLIENT_WPSS > + IPCC_MPROC_SIGNAL_GLINK_QMP>; > + > + label = "wpss"; > + qcom,remote-pid = <13>; > + }; > + }; > -- > 2.7.4 > ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v4 1/2] dt-bindings: remoteproc: qcom: Add SC7280 WPSS support 2021-09-17 10:35 ` [PATCH v4 1/2] dt-bindings: remoteproc: qcom: Add SC7280 WPSS support Rakesh Pillai 2021-09-20 19:58 ` Stephen Boyd @ 2021-09-22 17:28 ` Rob Herring 2021-09-23 17:12 ` pillair 1 sibling, 1 reply; 6+ messages in thread From: Rob Herring @ 2021-09-22 17:28 UTC (permalink / raw) To: Rakesh Pillai Cc: Gross, Andy, Bjorn Andersson, Ohad Ben-Cohen, Mathieu Poirier, Philipp Zabel, Stephen Boyd, linux-arm-msm, devicetree, linux-kernel@vger.kernel.org, sibis, mpubbise, kuabhs On Fri, Sep 17, 2021 at 5:36 AM Rakesh Pillai <pillair@codeaurora.org> wrote: > > Add WPSS PIL loading support for SC7280 SoCs. > > Signed-off-by: Rakesh Pillai <pillair@codeaurora.org> > --- > .../bindings/remoteproc/qcom,sc7280-wpss-pil.yaml | 198 +++++++++++++++++++++ > 1 file changed, 198 insertions(+) > create mode 100644 Documentation/devicetree/bindings/remoteproc/qcom,sc7280-wpss-pil.yaml What happened to converting the existing binding? Given you already did that, please don't drop it. > > diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-wpss-pil.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-wpss-pil.yaml > new file mode 100644 > index 0000000..896d5f47 > --- /dev/null > +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-wpss-pil.yaml > @@ -0,0 +1,198 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/remoteproc/qcom,sc7280-wpss-pil.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm SC7280 WPSS Peripheral Image Loader > + > +maintainers: > + - Bjorn Andersson <bjorn.andersson@linaro.org> > + > +description: > + This document defines the binding for a component that loads and boots firmware > + on the Qualcomm Technology Inc. WPSS. > + > +properties: > + compatible: > + enum: > + - qcom,sc7280-wpss-pil > + > + reg: > + maxItems: 1 > + description: > + The base address and size of the qdsp6ss register > + > + interrupts-extended: Use 'interrupts'. The tooling supports either. > + minItems: 6 Don't need minItems unless it is less than 'items' length. > + items: > + - description: Watchdog interrupt > + - description: Fatal interrupt > + - description: Ready interrupt > + - description: Handover interrupt > + - description: Stop acknowledge interrupt > + - description: Shutdown acknowledge interrupt > + > + interrupt-names: > + minItems: 6 > + items: > + - const: wdog > + - const: fatal > + - const: ready > + - const: handover > + - const: stop-ack > + - const: shutdown-ack > + > + clocks: > + minItems: 4 > + items: > + - description: GCC WPSS AHB BDG Master clock > + - description: GCC WPSS AHB clock > + - description: GCC WPSS RSCP clock > + - description: XO clock > + > + clock-names: > + minItems: 4 > + items: > + - const: gcc_wpss_ahb_bdg_mst_clk > + - const: gcc_wpss_ahb_clk > + - const: gcc_wpss_rscp_clk ahb_bdg, ahb, rscp is sufficient. Or use the same names as prior versions (did the h/w clocks change?). > + - const: xo > + > + power-domains: > + minItems: 2 > + items: > + - description: CX power domain > + - description: MX power domain > + > + power-domain-names: > + minItems: 2 > + items: > + - const: cx > + - const: mx > + > + resets: > + minItems: 2 > + items: > + - description: AOSS restart > + - description: PDC SYNC > + > + reset-names: > + minItems: 2 > + items: > + - const: restart > + - const: pdc_sync > + > + memory-region: > + maxItems: 1 > + description: Reference to the reserved-memory for the Hexagon core > + > + qcom,halt-regs: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + description: > + Phandle reference to a syscon representing TCSR followed by the > + three offsets within syscon for q6, modem and nc halt registers. > + > + qcom,qmp: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: Reference to the AOSS side-channel message RAM. > + > + qcom,smem-states: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + description: States used by the AP to signal the Hexagon core > + items: > + - description: Stop the modem > + > + qcom,smem-state-names: > + $ref: /schemas/types.yaml#/definitions/string-array string or string-array? > + description: The names of the state bits used for SMP2P output > + items: > + - const: stop This says only 1 entry, so 'string'. > + > + glink-edge: > + type: object > + description: > + Qualcomm G-Link subnode which represents communication edge, channels > + and devices related to the ADSP. > + > +required: > + - compatible > + - reg > + - interrupts-extended > + - interrupt-names > + - clocks > + - clock-names > + - power-domains > + - power-domain-names > + - reset > + - reset-names > + - qcom,halt-regs > + - memory-region > + - qcom,qmp > + - qcom,smem-states > + - qcom,smem-state-names > + - glink-edge > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/clock/qcom,gcc-sc7280.h> > + #include <dt-bindings/clock/qcom,rpmh.h> > + #include <dt-bindings/power/qcom-rpmpd.h> > + #include <dt-bindings/reset/qcom,sdm845-aoss.h> > + #include <dt-bindings/reset/qcom,sdm845-pdc.h> > + #include <dt-bindings/mailbox/qcom-ipcc.h> > + remoteproc@8a00000 { > + compatible = "qcom,sc7280-wpss-pil"; > + reg = <0x08a00000 0x10000>; > + > + interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>, > + <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, > + <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, > + <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, > + <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, > + <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; > + interrupt-names = "wdog", "fatal", "ready", "handover", > + "stop-ack", "shutdown-ack"; > + > + clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>, > + <&gcc GCC_WPSS_AHB_CLK>, > + <&gcc GCC_WPSS_RSCP_CLK>, > + <&rpmhcc RPMH_CXO_CLK>; > + clock-names = "gcc_wpss_ahb_bdg_mst_clk", > + "gcc_wpss_ahb_clk", > + "gcc_wpss_rscp_clk", > + "xo"; > + > + power-domains = <&rpmhpd SC7280_CX>, > + <&rpmhpd SC7280_MX>; > + power-domain-names = "cx", "mx"; > + > + memory-region = <&wpss_mem>; > + > + qcom,qmp = <&aoss_qmp>; > + > + qcom,smem-states = <&wpss_smp2p_out 0>; > + qcom,smem-state-names = "stop"; > + > + resets = <&aoss_reset AOSS_CC_WCSS_RESTART>, > + <&pdc_reset PDC_WPSS_SYNC_RESET>; > + reset-names = "restart", "pdc_sync"; > + > + qcom,halt-regs = <&tcsr_mutex 0x37000>; > + > + status = "disabled"; > + > + glink-edge { > + interrupts-extended = <&ipcc IPCC_CLIENT_WPSS > + IPCC_MPROC_SIGNAL_GLINK_QMP > + IRQ_TYPE_EDGE_RISING>; > + mboxes = <&ipcc IPCC_CLIENT_WPSS > + IPCC_MPROC_SIGNAL_GLINK_QMP>; > + > + label = "wpss"; > + qcom,remote-pid = <13>; > + }; > + }; > -- > 2.7.4 > ^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: [PATCH v4 1/2] dt-bindings: remoteproc: qcom: Add SC7280 WPSS support 2021-09-22 17:28 ` Rob Herring @ 2021-09-23 17:12 ` pillair 0 siblings, 0 replies; 6+ messages in thread From: pillair @ 2021-09-23 17:12 UTC (permalink / raw) To: 'Rob Herring' Cc: 'Gross, Andy', 'Bjorn Andersson', 'Ohad Ben-Cohen', 'Mathieu Poirier', 'Philipp Zabel', 'Stephen Boyd', 'linux-arm-msm', devicetree, linux-kernel, 'sibis', mpubbise, kuabhs > -----Original Message----- > From: Rob Herring <robh+dt@kernel.org> > Sent: Wednesday, September 22, 2021 10:59 PM > To: Rakesh Pillai <pillair@codeaurora.org> > Cc: Gross, Andy <agross@kernel.org>; Bjorn Andersson > <bjorn.andersson@linaro.org>; Ohad Ben-Cohen <ohad@wizery.com>; > Mathieu Poirier <mathieu.poirier@linaro.org>; Philipp Zabel > <p.zabel@pengutronix.de>; Stephen Boyd <swboyd@chromium.org>; linux- > arm-msm <linux-arm-msm@vger.kernel.org>; devicetree@vger.kernel.org; > linux-kernel@vger.kernel.org; sibis <sibis@codeaurora.org>; > mpubbise@codeaurora.org; kuabhs@chromium.org > Subject: Re: [PATCH v4 1/2] dt-bindings: remoteproc: qcom: Add SC7280 > WPSS support > > On Fri, Sep 17, 2021 at 5:36 AM Rakesh Pillai <pillair@codeaurora.org> wrote: > > > > Add WPSS PIL loading support for SC7280 SoCs. > > > > Signed-off-by: Rakesh Pillai <pillair@codeaurora.org> > > --- > > .../bindings/remoteproc/qcom,sc7280-wpss-pil.yaml | 198 > > +++++++++++++++++++++ > > 1 file changed, 198 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/remoteproc/qcom,sc7280-wpss- > pil.yaml > > What happened to converting the existing binding? Given you already did > that, please don't drop it. Hi Rob, Thanks for the review. Sure, let me post v5 with other comments on this patch-series addressed. I will also include the yaml conversion for existing dt-bindings. Thanks, Rakesh Pillai. > > > > > diff --git > > a/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-wpss- > pil.ya > > ml > > b/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-wpss- > pil.ya > > ml > > new file mode 100644 > > index 0000000..896d5f47 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sc7280- > wpss-pi > > +++ l.yaml > > @@ -0,0 +1,198 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 > > +--- > > +$id: > > +http://devicetree.org/schemas/remoteproc/qcom,sc7280-wpss-pil.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Qualcomm SC7280 WPSS Peripheral Image Loader > > + > > +maintainers: > > + - Bjorn Andersson <bjorn.andersson@linaro.org> > > + > > +description: > > + This document defines the binding for a component that loads and > > +boots firmware > > + on the Qualcomm Technology Inc. WPSS. > > + > > +properties: > > + compatible: > > + enum: > > + - qcom,sc7280-wpss-pil > > + > > + reg: > > + maxItems: 1 > > + description: > > + The base address and size of the qdsp6ss register > > + > > + interrupts-extended: > > Use 'interrupts'. The tooling supports either. > > > + minItems: 6 > > Don't need minItems unless it is less than 'items' length. > > > + items: > > + - description: Watchdog interrupt > > + - description: Fatal interrupt > > + - description: Ready interrupt > > + - description: Handover interrupt > > + - description: Stop acknowledge interrupt > > + - description: Shutdown acknowledge interrupt > > + > > + interrupt-names: > > + minItems: 6 > > + items: > > + - const: wdog > > + - const: fatal > > + - const: ready > > + - const: handover > > + - const: stop-ack > > + - const: shutdown-ack > > + > > + clocks: > > + minItems: 4 > > + items: > > + - description: GCC WPSS AHB BDG Master clock > > + - description: GCC WPSS AHB clock > > + - description: GCC WPSS RSCP clock > > + - description: XO clock > > + > > + clock-names: > > + minItems: 4 > > + items: > > + - const: gcc_wpss_ahb_bdg_mst_clk > > + - const: gcc_wpss_ahb_clk > > + - const: gcc_wpss_rscp_clk > > ahb_bdg, ahb, rscp is sufficient. Or use the same names as prior versions (did > the h/w clocks change?). > > > + - const: xo > > + > > + power-domains: > > + minItems: 2 > > + items: > > + - description: CX power domain > > + - description: MX power domain > > + > > + power-domain-names: > > + minItems: 2 > > + items: > > + - const: cx > > + - const: mx > > + > > + resets: > > + minItems: 2 > > + items: > > + - description: AOSS restart > > + - description: PDC SYNC > > + > > + reset-names: > > + minItems: 2 > > + items: > > + - const: restart > > + - const: pdc_sync > > + > > + memory-region: > > + maxItems: 1 > > + description: Reference to the reserved-memory for the Hexagon > > + core > > + > > + qcom,halt-regs: > > + $ref: /schemas/types.yaml#/definitions/phandle-array > > + description: > > + Phandle reference to a syscon representing TCSR followed by the > > + three offsets within syscon for q6, modem and nc halt registers. > > + > > + qcom,qmp: > > + $ref: /schemas/types.yaml#/definitions/phandle > > + description: Reference to the AOSS side-channel message RAM. > > + > > + qcom,smem-states: > > + $ref: /schemas/types.yaml#/definitions/phandle-array > > + description: States used by the AP to signal the Hexagon core > > + items: > > + - description: Stop the modem > > + > > + qcom,smem-state-names: > > + $ref: /schemas/types.yaml#/definitions/string-array > > string or string-array? > > > + description: The names of the state bits used for SMP2P output > > + items: > > + - const: stop > > This says only 1 entry, so 'string'. > > > + > > + glink-edge: > > + type: object > > + description: > > + Qualcomm G-Link subnode which represents communication edge, > channels > > + and devices related to the ADSP. > > + > > +required: > > + - compatible > > + - reg > > + - interrupts-extended > > + - interrupt-names > > + - clocks > > + - clock-names > > + - power-domains > > + - power-domain-names > > + - reset > > + - reset-names > > + - qcom,halt-regs > > + - memory-region > > + - qcom,qmp > > + - qcom,smem-states > > + - qcom,smem-state-names > > + - glink-edge > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include <dt-bindings/interrupt-controller/arm-gic.h> > > + #include <dt-bindings/clock/qcom,gcc-sc7280.h> > > + #include <dt-bindings/clock/qcom,rpmh.h> > > + #include <dt-bindings/power/qcom-rpmpd.h> > > + #include <dt-bindings/reset/qcom,sdm845-aoss.h> > > + #include <dt-bindings/reset/qcom,sdm845-pdc.h> > > + #include <dt-bindings/mailbox/qcom-ipcc.h> > > + remoteproc@8a00000 { > > + compatible = "qcom,sc7280-wpss-pil"; > > + reg = <0x08a00000 0x10000>; > > + > > + interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>, > > + <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, > > + <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, > > + <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, > > + <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, > > + <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; > > + interrupt-names = "wdog", "fatal", "ready", "handover", > > + "stop-ack", "shutdown-ack"; > > + > > + clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>, > > + <&gcc GCC_WPSS_AHB_CLK>, > > + <&gcc GCC_WPSS_RSCP_CLK>, > > + <&rpmhcc RPMH_CXO_CLK>; > > + clock-names = "gcc_wpss_ahb_bdg_mst_clk", > > + "gcc_wpss_ahb_clk", > > + "gcc_wpss_rscp_clk", > > + "xo"; > > + > > + power-domains = <&rpmhpd SC7280_CX>, > > + <&rpmhpd SC7280_MX>; > > + power-domain-names = "cx", "mx"; > > + > > + memory-region = <&wpss_mem>; > > + > > + qcom,qmp = <&aoss_qmp>; > > + > > + qcom,smem-states = <&wpss_smp2p_out 0>; > > + qcom,smem-state-names = "stop"; > > + > > + resets = <&aoss_reset AOSS_CC_WCSS_RESTART>, > > + <&pdc_reset PDC_WPSS_SYNC_RESET>; > > + reset-names = "restart", "pdc_sync"; > > + > > + qcom,halt-regs = <&tcsr_mutex 0x37000>; > > + > > + status = "disabled"; > > + > > + glink-edge { > > + interrupts-extended = <&ipcc IPCC_CLIENT_WPSS > > + IPCC_MPROC_SIGNAL_GLINK_QMP > > + IRQ_TYPE_EDGE_RISING>; > > + mboxes = <&ipcc IPCC_CLIENT_WPSS > > + IPCC_MPROC_SIGNAL_GLINK_QMP>; > > + > > + label = "wpss"; > > + qcom,remote-pid = <13>; > > + }; > > + }; > > -- > > 2.7.4 > > ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v4 2/2] remoteproc: qcom: q6v5_wpss: Add support for sc7280 WPSS 2021-09-17 10:35 [PATCH v4 0/2] Add support for sc7280 WPSS PIL loading Rakesh Pillai 2021-09-17 10:35 ` [PATCH v4 1/2] dt-bindings: remoteproc: qcom: Add SC7280 WPSS support Rakesh Pillai @ 2021-09-17 10:35 ` Rakesh Pillai 1 sibling, 0 replies; 6+ messages in thread From: Rakesh Pillai @ 2021-09-17 10:35 UTC (permalink / raw) To: agross, bjorn.andersson, ohad, mathieu.poirier, robh+dt, p.zabel Cc: swboyd, linux-arm-msm, devicetree, linux-kernel, sibis, mpubbise, kuabhs, Rakesh Pillai Add support for PIL loading of WPSS processor for SC7280 - WPSS boot will be requested by the wifi driver and hence disable auto-boot for WPSS. - Add a separate shutdown sequence handler for WPSS. - Add multiple power-domain voting support Signed-off-by: Rakesh Pillai <pillair@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> --- drivers/remoteproc/qcom_q6v5_adsp.c | 209 +++++++++++++++++++++++++++++++++--- 1 file changed, 194 insertions(+), 15 deletions(-) diff --git a/drivers/remoteproc/qcom_q6v5_adsp.c b/drivers/remoteproc/qcom_q6v5_adsp.c index 098362e6..b6d3c3d 100644 --- a/drivers/remoteproc/qcom_q6v5_adsp.c +++ b/drivers/remoteproc/qcom_q6v5_adsp.c @@ -32,6 +32,7 @@ /* time out value */ #define ACK_TIMEOUT 1000 +#define ACK_TIMEOUT_US 1000000 #define BOOT_FSM_TIMEOUT 10000 /* mask values */ #define EVB_MASK GENMASK(27, 4) @@ -51,6 +52,8 @@ #define QDSP6SS_CORE_CBCR 0x20 #define QDSP6SS_SLEEP_CBCR 0x3c +#define QCOM_Q6V5_RPROC_PROXY_PD_MAX 3 + struct adsp_pil_data { int crash_reason_smem; const char *firmware_name; @@ -58,9 +61,13 @@ struct adsp_pil_data { const char *ssr_name; const char *sysmon_name; int ssctl_id; + bool is_wpss; + bool auto_boot; const char **clk_ids; int num_clks; + const char **proxy_pd_names; + const char *load_state; }; struct qcom_adsp { @@ -93,11 +100,143 @@ struct qcom_adsp { void *mem_region; size_t mem_size; + struct device *proxy_pds[QCOM_Q6V5_RPROC_PROXY_PD_MAX]; + int proxy_pd_count; + struct qcom_rproc_glink glink_subdev; struct qcom_rproc_ssr ssr_subdev; struct qcom_sysmon *sysmon; + + int (*shutdown)(struct qcom_adsp *adsp); }; +static int qcom_rproc_pds_attach(struct device *dev, struct device **devs, + const char **pd_names) +{ + size_t num_pds = 0; + int ret; + int i; + + if (!pd_names) + return 0; + + /* Handle single power domain */ + if (dev->pm_domain) { + devs[0] = dev; + pm_runtime_enable(dev); + return 1; + } + + while (pd_names[num_pds]) + num_pds++; + + for (i = 0; i < num_pds; i++) { + devs[i] = dev_pm_domain_attach_by_name(dev, pd_names[i]); + if (IS_ERR_OR_NULL(devs[i])) { + ret = PTR_ERR(devs[i]) ? : -ENODATA; + goto unroll_attach; + } + } + + return num_pds; + +unroll_attach: + for (i--; i >= 0; i--) + dev_pm_domain_detach(devs[i], false); + + return ret; +} + +static void qcom_rproc_pds_detach(struct qcom_adsp *adsp, struct device **pds, + size_t pd_count) +{ + struct device *dev = adsp->dev; + int i; + + /* Handle single power domain */ + if (dev->pm_domain && pd_count) { + pm_runtime_disable(dev); + return; + } + + for (i = 0; i < pd_count; i++) + dev_pm_domain_detach(pds[i], false); +} + +static int qcom_rproc_pds_enable(struct qcom_adsp *adsp, struct device **pds, + size_t pd_count) +{ + int ret; + int i; + + for (i = 0; i < pd_count; i++) { + dev_pm_genpd_set_performance_state(pds[i], INT_MAX); + ret = pm_runtime_get_sync(pds[i]); + if (ret < 0) { + pm_runtime_put_noidle(pds[i]); + dev_pm_genpd_set_performance_state(pds[i], 0); + goto unroll_pd_votes; + } + } + + return 0; + +unroll_pd_votes: + for (i--; i >= 0; i--) { + dev_pm_genpd_set_performance_state(pds[i], 0); + pm_runtime_put(pds[i]); + } + + return ret; +} + +static void qcom_rproc_pds_disable(struct qcom_adsp *adsp, struct device **pds, + size_t pd_count) +{ + int i; + + for (i = 0; i < pd_count; i++) { + dev_pm_genpd_set_performance_state(pds[i], 0); + pm_runtime_put(pds[i]); + } +} + +static int qcom_wpss_shutdown(struct qcom_adsp *adsp) +{ + unsigned int val; + + regmap_write(adsp->halt_map, adsp->halt_lpass + LPASS_HALTREQ_REG, 1); + + /* Wait for halt ACK from QDSP6 */ + regmap_read_poll_timeout(adsp->halt_map, + adsp->halt_lpass + LPASS_HALTACK_REG, val, + val, 1000, ACK_TIMEOUT_US); + + /* Assert the WPSS PDC Reset */ + reset_control_assert(adsp->pdc_sync_reset); + /* Place the WPSS processor into reset */ + reset_control_assert(adsp->restart); + /* wait after asserting subsystem restart from AOSS */ + usleep_range(200, 205); + /* Remove the WPSS reset */ + reset_control_deassert(adsp->restart); + /* De-assert the WPSS PDC Reset */ + reset_control_deassert(adsp->pdc_sync_reset); + + usleep_range(100, 105); + + clk_bulk_disable_unprepare(adsp->num_clks, adsp->clks); + + regmap_write(adsp->halt_map, adsp->halt_lpass + LPASS_HALTREQ_REG, 0); + + /* Wait for halt ACK from QDSP6 */ + regmap_read_poll_timeout(adsp->halt_map, + adsp->halt_lpass + LPASS_HALTACK_REG, val, + !val, 1000, ACK_TIMEOUT_US); + + return 0; +} + static int qcom_adsp_shutdown(struct qcom_adsp *adsp) { unsigned long timeout; @@ -193,12 +332,10 @@ static int adsp_start(struct rproc *rproc) if (ret) goto disable_irqs; - dev_pm_genpd_set_performance_state(adsp->dev, INT_MAX); - ret = pm_runtime_get_sync(adsp->dev); - if (ret) { - pm_runtime_put_noidle(adsp->dev); + ret = qcom_rproc_pds_enable(adsp, adsp->proxy_pds, + adsp->proxy_pd_count); + if (ret < 0) goto disable_xo_clk; - } ret = clk_bulk_prepare_enable(adsp->num_clks, adsp->clks); if (ret) { @@ -243,8 +380,7 @@ static int adsp_start(struct rproc *rproc) disable_adsp_clks: clk_bulk_disable_unprepare(adsp->num_clks, adsp->clks); disable_power_domain: - dev_pm_genpd_set_performance_state(adsp->dev, 0); - pm_runtime_put(adsp->dev); + qcom_rproc_pds_disable(adsp, adsp->proxy_pds, adsp->proxy_pd_count); disable_xo_clk: clk_disable_unprepare(adsp->xo); disable_irqs: @@ -258,8 +394,7 @@ static void qcom_adsp_pil_handover(struct qcom_q6v5 *q6v5) struct qcom_adsp *adsp = container_of(q6v5, struct qcom_adsp, q6v5); clk_disable_unprepare(adsp->xo); - dev_pm_genpd_set_performance_state(adsp->dev, 0); - pm_runtime_put(adsp->dev); + qcom_rproc_pds_disable(adsp, adsp->proxy_pds, adsp->proxy_pd_count); } static int adsp_stop(struct rproc *rproc) @@ -272,7 +407,7 @@ static int adsp_stop(struct rproc *rproc) if (ret == -ETIMEDOUT) dev_err(adsp->dev, "timed out on wait\n"); - ret = qcom_adsp_shutdown(adsp); + ret = adsp->shutdown(adsp); if (ret) dev_err(adsp->dev, "failed to shutdown: %d\n", ret); @@ -441,6 +576,8 @@ static int adsp_probe(struct platform_device *pdev) dev_err(&pdev->dev, "unable to allocate remoteproc\n"); return -ENOMEM; } + + rproc->auto_boot = desc->auto_boot; rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE); adsp = (struct qcom_adsp *)rproc->priv; @@ -449,6 +586,11 @@ static int adsp_probe(struct platform_device *pdev) adsp->info_name = desc->sysmon_name; platform_set_drvdata(pdev, adsp); + if (desc->is_wpss) + adsp->shutdown = qcom_wpss_shutdown; + else + adsp->shutdown = qcom_adsp_shutdown; + ret = adsp_alloc_memory_region(adsp); if (ret) goto free_rproc; @@ -457,7 +599,13 @@ static int adsp_probe(struct platform_device *pdev) if (ret) goto free_rproc; - pm_runtime_enable(adsp->dev); + ret = qcom_rproc_pds_attach(adsp->dev, adsp->proxy_pds, + desc->proxy_pd_names); + if (ret < 0) { + dev_err(&pdev->dev, "Failed to attach proxy power domains\n"); + goto free_rproc; + } + adsp->proxy_pd_count = ret; ret = adsp_init_reset(adsp); if (ret) @@ -467,8 +615,8 @@ static int adsp_probe(struct platform_device *pdev) if (ret) goto disable_pm; - ret = qcom_q6v5_init(&adsp->q6v5, pdev, rproc, desc->crash_reason_smem, NULL, - qcom_adsp_pil_handover); + ret = qcom_q6v5_init(&adsp->q6v5, pdev, rproc, desc->crash_reason_smem, + desc->load_state, qcom_adsp_pil_handover); if (ret) goto disable_pm; @@ -489,7 +637,8 @@ static int adsp_probe(struct platform_device *pdev) return 0; disable_pm: - pm_runtime_disable(adsp->dev); + qcom_rproc_pds_detach(adsp, adsp->proxy_pds, adsp->proxy_pd_count); + free_rproc: rproc_free(rproc); @@ -506,7 +655,7 @@ static int adsp_remove(struct platform_device *pdev) qcom_remove_glink_subdev(adsp->rproc, &adsp->glink_subdev); qcom_remove_sysmon_subdev(adsp->sysmon); qcom_remove_ssr_subdev(adsp->rproc, &adsp->ssr_subdev); - pm_runtime_disable(adsp->dev); + qcom_rproc_pds_detach(adsp, adsp->proxy_pds, adsp->proxy_pd_count); rproc_free(adsp->rproc); return 0; @@ -518,11 +667,16 @@ static const struct adsp_pil_data adsp_resource_init = { .ssr_name = "lpass", .sysmon_name = "adsp", .ssctl_id = 0x14, + .is_wpss = false, + .auto_boot = true, .clk_ids = (const char*[]) { "sway_cbcr", "lpass_ahbs_aon_cbcr", "lpass_ahbm_aon_cbcr", "qdsp6ss_xo", "qdsp6ss_sleep", "qdsp6ss_core", NULL }, .num_clks = 7, + .proxy_pd_names = (const char*[]) { + "cx", NULL + }, }; static const struct adsp_pil_data cdsp_resource_init = { @@ -531,15 +685,40 @@ static const struct adsp_pil_data cdsp_resource_init = { .ssr_name = "cdsp", .sysmon_name = "cdsp", .ssctl_id = 0x17, + .is_wpss = false, + .auto_boot = true, .clk_ids = (const char*[]) { "sway", "tbu", "bimc", "ahb_aon", "q6ss_slave", "q6ss_master", "q6_axim", NULL }, .num_clks = 7, + .proxy_pd_names = (const char*[]) { + "cx", NULL + }, +}; + +static const struct adsp_pil_data wpss_resource_init = { + .crash_reason_smem = 626, + .firmware_name = "wpss.mdt", + .ssr_name = "wpss", + .sysmon_name = "wpss", + .ssctl_id = 0x19, + .is_wpss = true, + .auto_boot = false, + .load_state = "wpss", + .clk_ids = (const char*[]) { + "gcc_wpss_ahb_bdg_mst_clk", "gcc_wpss_ahb_clk", + "gcc_wpss_rscp_clk", NULL + }, + .num_clks = 3, + .proxy_pd_names = (const char*[]) { + "cx", "mx", NULL + }, }; static const struct of_device_id adsp_of_match[] = { { .compatible = "qcom,qcs404-cdsp-pil", .data = &cdsp_resource_init }, + { .compatible = "qcom,sc7280-wpss-pil", .data = &wpss_resource_init }, { .compatible = "qcom,sdm845-adsp-pil", .data = &adsp_resource_init }, { }, }; -- 2.7.4 ^ permalink raw reply related [flat|nested] 6+ messages in thread
end of thread, other threads:[~2021-09-23 17:13 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2021-09-17 10:35 [PATCH v4 0/2] Add support for sc7280 WPSS PIL loading Rakesh Pillai 2021-09-17 10:35 ` [PATCH v4 1/2] dt-bindings: remoteproc: qcom: Add SC7280 WPSS support Rakesh Pillai 2021-09-20 19:58 ` Stephen Boyd 2021-09-22 17:28 ` Rob Herring 2021-09-23 17:12 ` pillair 2021-09-17 10:35 ` [PATCH v4 2/2] remoteproc: qcom: q6v5_wpss: Add support for sc7280 WPSS Rakesh Pillai
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