From: "Kevin D. Kissell" <kevink@mips.com>
To: "Kim, Jong-Sung" <jsungkim@lge.com>, "Thiemo Seufer" <ths@networkno.de>
Cc: <linux-mips@linux-mips.org>
Subject: Re: Reading an entire cacheline
Date: Wed, 26 Apr 2006 13:24:32 +0200 [thread overview]
Message-ID: <005701c66924$00a74860$10eca8c0@grendel> (raw)
In-Reply-To: 20060426101603.GB29550@networkno.de
> [snip]
> > //" bne %0, %9, 2b\n"
> > " .set mips0\n"
> > " .set reorder"
> > : "=r" (tag[1][way][0]), "=r" (datalo[1][way][0]),
> > "=r" (datahi[1][way][0]),
> > "=r" (tag[1][way][1]), "=r" (datalo[1][way][1]),
> > "=r" (datahi[1][way][1]),
> > "=r" (tag[1][way][2]), "=r" (datalo[1][way][2]),
> > "=r" (datahi[1][way][2]),
> > "=r" (tag[1][way][3]), "=r" (datalo[1][way][3]),
> > "=r" (datahi[1][way][3])
> > : "r" (0x80000000 | (way << 14) | (line << 5))
> > );
>
> And this part may cause the problem you are seeing, I presume
> datalo/datahi live in memory, and accesses of it change the dcache.
As I was hoping disassembly would demonstrate for you,
declaring "=r" doesn't mean that the variable has no life
outside a register.
Regards,
Kevin K.
WARNING: multiple messages have this Message-ID (diff)
From: "Kevin D. Kissell" <kevink@mips.com>
To: "Kim, Jong-Sung" <jsungkim@lge.com>, Thiemo Seufer <ths@networkno.de>
Cc: linux-mips@linux-mips.org
Subject: Re: Reading an entire cacheline
Date: Wed, 26 Apr 2006 13:24:32 +0200 [thread overview]
Message-ID: <005701c66924$00a74860$10eca8c0@grendel> (raw)
Message-ID: <20060426112432.LrJBjwh4XhkutPzl-SmwxcRQ0buAxNkZC8Bc1lMQYgY@z> (raw)
In-Reply-To: 20060426101603.GB29550@networkno.de
> [snip]
> > //" bne %0, %9, 2b\n"
> > " .set mips0\n"
> > " .set reorder"
> > : "=r" (tag[1][way][0]), "=r" (datalo[1][way][0]),
> > "=r" (datahi[1][way][0]),
> > "=r" (tag[1][way][1]), "=r" (datalo[1][way][1]),
> > "=r" (datahi[1][way][1]),
> > "=r" (tag[1][way][2]), "=r" (datalo[1][way][2]),
> > "=r" (datahi[1][way][2]),
> > "=r" (tag[1][way][3]), "=r" (datalo[1][way][3]),
> > "=r" (datahi[1][way][3])
> > : "r" (0x80000000 | (way << 14) | (line << 5))
> > );
>
> And this part may cause the problem you are seeing, I presume
> datalo/datahi live in memory, and accesses of it change the dcache.
As I was hoping disassembly would demonstrate for you,
declaring "=r" doesn't mean that the variable has no life
outside a register.
Regards,
Kevin K.
next prev parent reply other threads:[~2006-04-26 11:08 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2006-04-24 9:52 Reading an entire cacheline Kim, Jong-Sung
2006-04-24 9:52 ` Kim, Jong-Sung
2006-04-26 8:47 ` Kim, Jong-Sung
2006-04-26 8:47 ` Kim, Jong-Sung
2006-04-26 9:48 ` Kevin D. Kissell
2006-04-26 9:48 ` Kevin D. Kissell
2006-04-26 10:16 ` Thiemo Seufer
2006-04-26 11:24 ` Kevin D. Kissell [this message]
2006-04-26 11:24 ` Kevin D. Kissell
2006-04-27 5:04 ` Kim, Jong-Sung
2006-04-27 5:04 ` Kim, Jong-Sung
2006-04-27 5:13 ` Kim, Jong-Sung
2006-04-27 5:13 ` Kim, Jong-Sung
-- strict thread matches above, loose matches on Subject: below --
2006-04-18 0:37 Kim, Jong-Sung
2006-04-18 0:37 ` Kim, Jong-Sung
2006-04-24 7:23 ` Kim, Jong-Sung
2006-04-24 7:23 ` Kim, Jong-Sung
2006-04-24 7:40 ` Kevin D. Kissell
2006-04-24 7:40 ` Kevin D. Kissell
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