Re: [PATCH] ret_from_irq adjustment

["Kevin D. Kissell" <kevink@mips.com>]

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I attach a text file (inline cut-and-paste produces Windows whitespace
which apparently is unacceptable) of a patch which (a) implements the
ret_from_irq optimization that Atsushi wanted to do to the SMTC code, 
only without breaking it.  I also reorganized and re-commented the code to
be easier to maintain in the future, and in an unrelated matter (b) fixes
a bug in arch/mips/kernel/smtc.c when there are 64 or more TLB
entry pairs on a 34K core.  This TLB patch has been in the internal
MIPS repository forever, but for some reason has never made it
out onto linux-mips.org.

The resulting kernel boots and runs (with a 64-entry TLB).

Note that these patches are relative to the 2.6.17 semi-stable
tree, and not the latest hackfest, so the renaming of ret_from_irq
to _ret_from_irq had not been done, and is not reflected in the patch.

            Regards,

            Kevin K.

----- Original Message ----- 
From: "Kevin D. Kissell" <KevinK@mips.com>
To: <linux-mips@linux-mips.org>; "Atsushi Nemoto" <anemo@mba.ocn.ne.jp>
Cc: <ralf@linux-mips.org>
Sent: Sunday, October 08, 2006 8:26 PM
Subject: Re: [PATCH] ret_from_irq adjustment


> While setting up ra "by hand" and transferring control via the jr
> is a reasonable optimization, you're otherwise breaking things for SMTC.
> While the comments are misleading (they accurately described an earlier
> version of the code), the function being called here is ipi_decode(), which
>  needs a pt_regs * in the first argument (hence the copy of the sp), and 
> the pointer to the IPI message descriptor in the second.
> 
> Do you have access to a 34K to test changes to SMTC?  I'd have
> expected this one to have been pretty quickly fatal.
> 
>             Regards,
> 
>             Kevin K.
> 
> > diff --git a/arch/mips/kernel/smtc-asm.S b/arch/mips/kernel/smtc-asm.S
> > index 76cb31d..1cb9441 100644
> > --- a/arch/mips/kernel/smtc-asm.S
> > +++ b/arch/mips/kernel/smtc-asm.S
> > @@ -97,15 +97,12 @@ FEXPORT(__smtc_ipi_vector)
> >   SAVE_ALL
> >   CLI
> >   TRACE_IRQS_OFF
> > - move a0,sp
> >   /* Function to be invoked passed stack pad slot 5 */
> >   lw t0,PT_PADSLOT5(sp)
> >   /* Argument from sender passed in stack pad slot 4 */
> > - lw a1,PT_PADSLOT4(sp)
> > - jalr t0
> > - nop
> > - j ret_from_irq
> > - nop
> > + lw a0,PT_PADSLOT4(sp)
> > + PTR_LA ra, _ret_from_irq
> > + jr t0
> >  
> >  /*
> >   * Called from idle loop to provoke processing of queued IPIs
> > 
> > 
> 
> 

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diff --git a/arch/mips/kernel/smtc-asm.S b/arch/mips/kernel/smtc-asm.S
index 72c6d98..a1709de 100644
--- a/arch/mips/kernel/smtc-asm.S
+++ b/arch/mips/kernel/smtc-asm.S
@@ -96,15 +96,14 @@ FEXPORT(__smtc_ipi_vector)
 	/* Save all will redundantly recompute the SP, but use it for now */
 	SAVE_ALL
 	CLI
-	move	a0,sp
 	/* Function to be invoked passed stack pad slot 5 */
 	lw	t0,PT_PADSLOT5(sp)
-	/* Argument from sender passed in stack pad slot 4 */
+	/* First argument is pointer to pt_regs on kernel stack */
+	move	a0,sp
+	/* Additional argument from sender passed in stack pad slot 4 */
 	lw	a1,PT_PADSLOT4(sp)
-	jalr	t0
-	nop
-	j	ret_from_irq
-	nop
+	PTR_LA	ra,ret_from_irq
+	jr	t0
 
 /*
  * Called from idle loop to provoke processing of queued IPIs
diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c
index 2e8e52c..1657d15 100644
--- a/arch/mips/kernel/smtc.c
+++ b/arch/mips/kernel/smtc.c
@@ -269,7 +269,8 @@ void smtc_configure_tlb(void)
 		 * of their initialization in smtc_cpu_setup().
 		 */
 
-		tlbsiz = tlbsiz & 0x3f;	/* MIPS32 limits TLB indices to 64 */
+		/* MIPS32 limits TLB indices to 64 */
+		if (tlbsiz > 64) tlbsiz = 64;
 		cpu_data[0].tlbsize = tlbsiz;
 		smtc_status |= SMTC_TLB_SHARED;