* [dpdk-dev] [PATCH v4 1/6] net/txgbe: update device ID
2021-03-29 3:17 [dpdk-dev] [PATCH v4 0/6] txgbe backplane AN training Jiawen Wu
@ 2021-03-29 3:17 ` Jiawen Wu
2021-03-29 3:17 ` [dpdk-dev] [PATCH v4 2/6] net/txgbe: move firmware version get function to base code Jiawen Wu
` (5 subsequent siblings)
6 siblings, 0 replies; 10+ messages in thread
From: Jiawen Wu @ 2021-03-29 3:17 UTC (permalink / raw)
To: dev; +Cc: Jiawen Wu
For more different devices, update device ID and subsystem id.
Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
---
drivers/net/txgbe/base/txgbe_devids.h | 44 ++++++++++++++-------
drivers/net/txgbe/base/txgbe_hw.c | 55 ++++++++++++---------------
drivers/net/txgbe/base/txgbe_phy.c | 40 +++++++++++--------
drivers/net/txgbe/txgbe_ethdev.c | 4 +-
drivers/net/txgbe/txgbe_ethdev_vf.c | 4 +-
5 files changed, 84 insertions(+), 63 deletions(-)
diff --git a/drivers/net/txgbe/base/txgbe_devids.h b/drivers/net/txgbe/base/txgbe_devids.h
index 744f2f3b5..cb186170e 100644
--- a/drivers/net/txgbe/base/txgbe_devids.h
+++ b/drivers/net/txgbe/base/txgbe_devids.h
@@ -15,22 +15,40 @@
/*
* Device IDs
*/
-#define TXGBE_DEV_ID_RAPTOR_VF 0x1000
-#define TXGBE_DEV_ID_RAPTOR_SFP 0x1001 /* fiber */
-#define TXGBE_DEV_ID_RAPTOR_KR_KX_KX4 0x1002 /* backplane */
-#define TXGBE_DEV_ID_RAPTOR_XAUI 0x1003 /* copper */
-#define TXGBE_DEV_ID_RAPTOR_SGMII 0x1004 /* copper */
-#define TXGBE_DEV_ID_RAPTOR_QSFP 0x1011 /* fiber */
-#define TXGBE_DEV_ID_RAPTOR_VF_HV 0x2000
-#define TXGBE_DEV_ID_RAPTOR_T3_LOM 0x2001
-
-#define TXGBE_DEV_ID_WX1820_SFP 0x2001
+#define TXGBE_DEV_ID_SP1000 0x1001
+#define TXGBE_DEV_ID_WX1820 0x2001
+#define TXGBE_DEV_ID_SP1000_VF 0x1000
+#define TXGBE_DEV_ID_WX1820_VF 0x2000
/*
- * Subdevice IDs
+ * Subsystem IDs
*/
-#define TXGBE_SUBDEV_ID_RAPTOR 0x0000
-#define TXGBE_SUBDEV_ID_MPW 0x0001
+/* SFP */
+#define TXGBE_DEV_ID_SP1000_SFP 0x0000
+#define TXGBE_DEV_ID_WX1820_SFP 0x2000
+#define TXGBE_DEV_ID_SFP 0x00
+/* copper */
+#define TXGBE_DEV_ID_SP1000_XAUI 0x1010
+#define TXGBE_DEV_ID_WX1820_XAUI 0x2010
+#define TXGBE_DEV_ID_XAUI 0x10
+#define TXGBE_DEV_ID_SP1000_SGMII 0x1020
+#define TXGBE_DEV_ID_WX1820_SGMII 0x2020
+#define TXGBE_DEV_ID_SGMII 0x20
+/* backplane */
+#define TXGBE_DEV_ID_SP1000_KR_KX_KX4 0x1030
+#define TXGBE_DEV_ID_WX1820_KR_KX_KX4 0x2030
+#define TXGBE_DEV_ID_KR_KX_KX4 0x30
+/* MAC Interface */
+#define TXGBE_DEV_ID_SP1000_MAC_XAUI 0x1040
+#define TXGBE_DEV_ID_WX1820_MAC_XAUI 0x2040
+#define TXGBE_DEV_ID_MAC_XAUI 0x40
+#define TXGBE_DEV_ID_SP1000_MAC_SGMII 0x1060
+#define TXGBE_DEV_ID_WX1820_MAC_SGMII 0x2060
+#define TXGBE_DEV_ID_MAC_SGMII 0x60
+/* combined interface*/
+#define TXGBE_DEV_ID_SFI_XAUI 0x50
+/* fiber qsfp*/
+#define TXGBE_DEV_ID_QSFP 0x11
#define TXGBE_ETHERTYPE_FLOW_CTRL 0x8808
#define TXGBE_ETHERTYPE_IEEE_VLAN 0x8100 /* 802.1q protocol */
diff --git a/drivers/net/txgbe/base/txgbe_hw.c b/drivers/net/txgbe/base/txgbe_hw.c
index 3cee8b857..81efb6444 100644
--- a/drivers/net/txgbe/base/txgbe_hw.c
+++ b/drivers/net/txgbe/base/txgbe_hw.c
@@ -60,9 +60,9 @@ bool txgbe_device_supports_autoneg_fc(struct txgbe_hw *hw)
break;
case txgbe_media_type_copper:
/* only some copper devices support flow control autoneg */
- switch (hw->device_id) {
- case TXGBE_DEV_ID_RAPTOR_XAUI:
- case TXGBE_DEV_ID_RAPTOR_SGMII:
+ switch (hw->subsystem_device_id & 0xFF) {
+ case TXGBE_DEV_ID_XAUI:
+ case TXGBE_DEV_ID_SGMII:
supported = true;
break;
default:
@@ -2525,26 +2525,12 @@ s32 txgbe_set_mac_type(struct txgbe_hw *hw)
}
switch (hw->device_id) {
- case TXGBE_DEV_ID_RAPTOR_KR_KX_KX4:
- hw->phy.media_type = txgbe_media_type_backplane;
+ case TXGBE_DEV_ID_SP1000:
+ case TXGBE_DEV_ID_WX1820:
hw->mac.type = txgbe_mac_raptor;
break;
- case TXGBE_DEV_ID_RAPTOR_XAUI:
- case TXGBE_DEV_ID_RAPTOR_SGMII:
- hw->phy.media_type = txgbe_media_type_copper;
- hw->mac.type = txgbe_mac_raptor;
- break;
- case TXGBE_DEV_ID_RAPTOR_SFP:
- case TXGBE_DEV_ID_WX1820_SFP:
- hw->phy.media_type = txgbe_media_type_fiber;
- hw->mac.type = txgbe_mac_raptor;
- break;
- case TXGBE_DEV_ID_RAPTOR_QSFP:
- hw->phy.media_type = txgbe_media_type_fiber_qsfp;
- hw->mac.type = txgbe_mac_raptor;
- break;
- case TXGBE_DEV_ID_RAPTOR_VF:
- case TXGBE_DEV_ID_RAPTOR_VF_HV:
+ case TXGBE_DEV_ID_SP1000_VF:
+ case TXGBE_DEV_ID_WX1820_VF:
hw->phy.media_type = txgbe_media_type_virtual;
hw->mac.type = txgbe_mac_raptor_vf;
break;
@@ -2554,8 +2540,8 @@ s32 txgbe_set_mac_type(struct txgbe_hw *hw)
break;
}
- DEBUGOUT("found mac: %d media: %d, returns: %d\n",
- hw->mac.type, hw->phy.media_type, err);
+ DEBUGOUT("found mac: %d, returns: %d\n",
+ hw->mac.type, err);
return err;
}
@@ -2613,7 +2599,7 @@ s32 txgbe_init_phy_raptor(struct txgbe_hw *hw)
DEBUGFUNC("txgbe_init_phy_raptor");
- if (hw->device_id == TXGBE_DEV_ID_RAPTOR_QSFP) {
+ if ((hw->device_id & 0xFF) == TXGBE_DEV_ID_QSFP) {
/* Store flag indicating I2C bus access control unit. */
hw->phy.qsfp_shared_i2c_bus = TRUE;
@@ -3017,22 +3003,29 @@ u32 txgbe_get_media_type_raptor(struct txgbe_hw *hw)
break;
}
- switch (hw->device_id) {
- case TXGBE_DEV_ID_RAPTOR_KR_KX_KX4:
+ switch (hw->subsystem_device_id & 0xFF) {
+ case TXGBE_DEV_ID_KR_KX_KX4:
+ case TXGBE_DEV_ID_MAC_SGMII:
+ case TXGBE_DEV_ID_MAC_XAUI:
/* Default device ID is mezzanine card KX/KX4 */
media_type = txgbe_media_type_backplane;
break;
- case TXGBE_DEV_ID_RAPTOR_SFP:
- case TXGBE_DEV_ID_WX1820_SFP:
+ case TXGBE_DEV_ID_SFP:
media_type = txgbe_media_type_fiber;
break;
- case TXGBE_DEV_ID_RAPTOR_QSFP:
+ case TXGBE_DEV_ID_QSFP:
media_type = txgbe_media_type_fiber_qsfp;
break;
- case TXGBE_DEV_ID_RAPTOR_XAUI:
- case TXGBE_DEV_ID_RAPTOR_SGMII:
+ case TXGBE_DEV_ID_XAUI:
+ case TXGBE_DEV_ID_SGMII:
media_type = txgbe_media_type_copper;
break;
+ case TXGBE_DEV_ID_SFI_XAUI:
+ if (hw->bus.lan_id == 0)
+ media_type = txgbe_media_type_fiber;
+ else
+ media_type = txgbe_media_type_copper;
+ break;
default:
media_type = txgbe_media_type_unknown;
break;
diff --git a/drivers/net/txgbe/base/txgbe_phy.c b/drivers/net/txgbe/base/txgbe_phy.c
index bdd6bf780..37c41099f 100644
--- a/drivers/net/txgbe/base/txgbe_phy.c
+++ b/drivers/net/txgbe/base/txgbe_phy.c
@@ -2126,26 +2126,32 @@ u64 txgbe_autoc_read(struct txgbe_hw *hw)
u32 sr_pma_ctl1;
u32 sr_an_ctl;
u32 sr_an_adv_reg2;
+ u8 type = hw->subsystem_device_id & 0xFF;
if (hw->phy.multispeed_fiber) {
autoc |= TXGBE_AUTOC_LMS_10G;
- } else if (hw->device_id == TXGBE_DEV_ID_RAPTOR_SFP ||
- hw->device_id == TXGBE_DEV_ID_WX1820_SFP) {
- autoc |= TXGBE_AUTOC_LMS_10G |
- TXGBE_AUTOC_10GS_SFI;
- } else if (hw->device_id == TXGBE_DEV_ID_RAPTOR_QSFP) {
+ } else if (type == TXGBE_DEV_ID_SFP) {
+ autoc |= TXGBE_AUTOC_LMS_10G;
+ autoc |= TXGBE_AUTOC_10GS_SFI;
+ } else if (type == TXGBE_DEV_ID_QSFP) {
autoc = 0; /*TBD*/
- } else if (hw->device_id == TXGBE_DEV_ID_RAPTOR_XAUI) {
- autoc |= TXGBE_AUTOC_LMS_10G_LINK_NO_AN |
- TXGBE_AUTOC_10G_XAUI;
+ } else if (type == TXGBE_DEV_ID_XAUI || type == TXGBE_DEV_ID_SFI_XAUI) {
+ autoc |= TXGBE_AUTOC_LMS_10G_LINK_NO_AN;
+ autoc |= TXGBE_AUTOC_10G_XAUI;
hw->phy.link_mode = TXGBE_PHYSICAL_LAYER_10GBASE_T;
- } else if (hw->device_id == TXGBE_DEV_ID_RAPTOR_SGMII) {
+ } else if (type == TXGBE_DEV_ID_SGMII) {
autoc |= TXGBE_AUTOC_LMS_SGMII_1G_100M;
hw->phy.link_mode = TXGBE_PHYSICAL_LAYER_1000BASE_T |
TXGBE_PHYSICAL_LAYER_100BASE_TX;
+ } else if (type == TXGBE_DEV_ID_MAC_XAUI) {
+ autoc |= TXGBE_AUTOC_LMS_10G_LINK_NO_AN;
+ hw->phy.link_mode = TXGBE_PHYSICAL_LAYER_10GBASE_KX4;
+ } else if (type == TXGBE_DEV_ID_MAC_SGMII) {
+ autoc |= TXGBE_AUTOC_LMS_1G_LINK_NO_AN;
+ hw->phy.link_mode = TXGBE_PHYSICAL_LAYER_1000BASE_KX;
}
- if (hw->device_id != TXGBE_DEV_ID_RAPTOR_SGMII)
+ if (type != TXGBE_DEV_ID_KR_KX_KX4)
return autoc;
sr_pcs_ctl = rd32_epcs(hw, SR_XS_PCS_CTRL2);
@@ -2201,13 +2207,14 @@ void txgbe_autoc_write(struct txgbe_hw *hw, u64 autoc)
bool autoneg;
u32 speed;
u32 mactxcfg = 0;
+ u8 device_type = hw->subsystem_device_id & 0xFF;
speed = TXGBE_AUTOC_SPEED(autoc);
autoc &= ~TXGBE_AUTOC_SPEED_MASK;
autoneg = (autoc & TXGBE_AUTOC_AUTONEG ? true : false);
autoc &= ~TXGBE_AUTOC_AUTONEG;
- if (hw->device_id == TXGBE_DEV_ID_RAPTOR_KR_KX_KX4) {
+ if (device_type == TXGBE_DEV_ID_KR_KX_KX4) {
if (!autoneg) {
switch (hw->phy.link_mode) {
case TXGBE_PHYSICAL_LAYER_10GBASE_KR:
@@ -2223,16 +2230,19 @@ void txgbe_autoc_write(struct txgbe_hw *hw, u64 autoc)
return;
}
}
- } else if (hw->device_id == TXGBE_DEV_ID_RAPTOR_XAUI ||
- hw->device_id == TXGBE_DEV_ID_RAPTOR_SGMII) {
+ } else if (device_type == TXGBE_DEV_ID_XAUI ||
+ device_type == TXGBE_DEV_ID_SGMII ||
+ device_type == TXGBE_DEV_ID_MAC_XAUI ||
+ device_type == TXGBE_DEV_ID_MAC_SGMII ||
+ (device_type == TXGBE_DEV_ID_SFI_XAUI &&
+ hw->phy.media_type == txgbe_media_type_copper)) {
if (speed == TXGBE_LINK_SPEED_10GB_FULL) {
txgbe_set_link_to_kx4(hw, autoneg);
} else {
txgbe_set_link_to_kx(hw, speed, 0);
txgbe_set_sgmii_an37_ability(hw);
}
- } else if (hw->device_id == TXGBE_DEV_ID_RAPTOR_SFP ||
- hw->device_id == TXGBE_DEV_ID_WX1820_SFP) {
+ } else if (hw->phy.media_type == txgbe_media_type_fiber) {
txgbe_set_link_to_sfi(hw, speed);
}
diff --git a/drivers/net/txgbe/txgbe_ethdev.c b/drivers/net/txgbe/txgbe_ethdev.c
index 5509e5f35..63a987506 100644
--- a/drivers/net/txgbe/txgbe_ethdev.c
+++ b/drivers/net/txgbe/txgbe_ethdev.c
@@ -138,8 +138,8 @@ static void txgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
* The set of PCI devices this driver supports
*/
static const struct rte_pci_id pci_id_txgbe_map[] = {
- { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_RAPTOR_SFP) },
- { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_WX1820_SFP) },
+ { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_SP1000) },
+ { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_WX1820) },
{ .vendor_id = 0, /* sentinel */ },
};
diff --git a/drivers/net/txgbe/txgbe_ethdev_vf.c b/drivers/net/txgbe/txgbe_ethdev_vf.c
index 63a45d32c..3a5123733 100644
--- a/drivers/net/txgbe/txgbe_ethdev_vf.c
+++ b/drivers/net/txgbe/txgbe_ethdev_vf.c
@@ -71,8 +71,8 @@ static void txgbevf_dev_interrupt_handler(void *param);
* The set of PCI devices this driver supports (for VF)
*/
static const struct rte_pci_id pci_id_txgbevf_map[] = {
- { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_RAPTOR_VF) },
- { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_RAPTOR_VF_HV) },
+ { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_SP1000_VF) },
+ { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_WX1820_VF) },
{ .vendor_id = 0, /* sentinel */ },
};
--
2.27.0
^ permalink raw reply related [flat|nested] 10+ messages in thread* [dpdk-dev] [PATCH v4 2/6] net/txgbe: move firmware version get function to base code
2021-03-29 3:17 [dpdk-dev] [PATCH v4 0/6] txgbe backplane AN training Jiawen Wu
2021-03-29 3:17 ` [dpdk-dev] [PATCH v4 1/6] net/txgbe: update device ID Jiawen Wu
@ 2021-03-29 3:17 ` Jiawen Wu
2021-03-29 3:17 ` [dpdk-dev] [PATCH v4 3/6] net/txgbe: update link setup process of backplane NICs Jiawen Wu
` (4 subsequent siblings)
6 siblings, 0 replies; 10+ messages in thread
From: Jiawen Wu @ 2021-03-29 3:17 UTC (permalink / raw)
To: dev; +Cc: Jiawen Wu
Move firmware version get function to base code,
and store firmware version in PHY info.
Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
---
drivers/net/txgbe/base/txgbe_dummy.h | 6 ++++++
drivers/net/txgbe/base/txgbe_hw.c | 4 ++++
drivers/net/txgbe/base/txgbe_phy.c | 12 ++++++++++++
drivers/net/txgbe/base/txgbe_phy.h | 1 +
drivers/net/txgbe/base/txgbe_type.h | 2 ++
drivers/net/txgbe/txgbe_ethdev.c | 5 +----
6 files changed, 26 insertions(+), 4 deletions(-)
diff --git a/drivers/net/txgbe/base/txgbe_dummy.h b/drivers/net/txgbe/base/txgbe_dummy.h
index c9f2e7893..b62501d65 100644
--- a/drivers/net/txgbe/base/txgbe_dummy.h
+++ b/drivers/net/txgbe/base/txgbe_dummy.h
@@ -424,6 +424,11 @@ static inline s32 txgbe_phy_check_link_dummy(struct txgbe_hw *TUP0, u32 *TUP1,
{
return TXGBE_ERR_OPS_DUMMY;
}
+static inline s32 txgbe_get_phy_fw_version_dummy(struct txgbe_hw *TUP0,
+ u32 *TUP1)
+{
+ return TXGBE_ERR_OPS_DUMMY;
+}
static inline s32 txgbe_phy_read_i2c_byte_dummy(struct txgbe_hw *TUP0, u8 TUP1,
u8 TUP2, u8 *TUP3)
{
@@ -628,6 +633,7 @@ static inline void txgbe_init_ops_dummy(struct txgbe_hw *hw)
hw->phy.setup_link = txgbe_phy_setup_link_dummy;
hw->phy.setup_link_speed = txgbe_phy_setup_link_speed_dummy;
hw->phy.check_link = txgbe_phy_check_link_dummy;
+ hw->phy.get_fw_version = txgbe_get_phy_fw_version_dummy;
hw->phy.read_i2c_byte = txgbe_phy_read_i2c_byte_dummy;
hw->phy.write_i2c_byte = txgbe_phy_write_i2c_byte_dummy;
hw->phy.read_i2c_sff8472 = txgbe_phy_read_i2c_sff8472_dummy;
diff --git a/drivers/net/txgbe/base/txgbe_hw.c b/drivers/net/txgbe/base/txgbe_hw.c
index 81efb6444..26562f50d 100644
--- a/drivers/net/txgbe/base/txgbe_hw.c
+++ b/drivers/net/txgbe/base/txgbe_hw.c
@@ -323,6 +323,9 @@ s32 txgbe_init_hw(struct txgbe_hw *hw)
DEBUGFUNC("txgbe_init_hw");
+ /* Get firmware version */
+ hw->phy.get_fw_version(hw, &hw->fw_version);
+
/* Reset the hardware */
status = hw->mac.reset_hw(hw);
if (status == 0 || status == TXGBE_ERR_SFP_NOT_PRESENT) {
@@ -2774,6 +2777,7 @@ s32 txgbe_init_ops_pf(struct txgbe_hw *hw)
phy->write_reg_mdi = txgbe_write_phy_reg_mdi;
phy->setup_link = txgbe_setup_phy_link;
phy->setup_link_speed = txgbe_setup_phy_link_speed;
+ phy->get_fw_version = txgbe_get_phy_fw_version;
phy->read_i2c_byte = txgbe_read_i2c_byte;
phy->write_i2c_byte = txgbe_write_i2c_byte;
phy->read_i2c_sff8472 = txgbe_read_i2c_sff8472;
diff --git a/drivers/net/txgbe/base/txgbe_phy.c b/drivers/net/txgbe/base/txgbe_phy.c
index 37c41099f..1ca6e35a4 100644
--- a/drivers/net/txgbe/base/txgbe_phy.c
+++ b/drivers/net/txgbe/base/txgbe_phy.c
@@ -558,6 +558,18 @@ s32 txgbe_setup_phy_link_speed(struct txgbe_hw *hw,
return 0;
}
+s32 txgbe_get_phy_fw_version(struct txgbe_hw *hw, u32 *fw_version)
+{
+ u16 eeprom_verh, eeprom_verl;
+
+ hw->rom.readw_sw(hw, TXGBE_EEPROM_VERSION_H, &eeprom_verh);
+ hw->rom.readw_sw(hw, TXGBE_EEPROM_VERSION_L, &eeprom_verl);
+
+ *fw_version = (eeprom_verh << 16) | eeprom_verl;
+
+ return 0;
+}
+
/**
* txgbe_get_copper_speeds_supported - Get copper link speeds from phy
* @hw: pointer to hardware structure
diff --git a/drivers/net/txgbe/base/txgbe_phy.h b/drivers/net/txgbe/base/txgbe_phy.h
index 5aec1d28f..4a5b90077 100644
--- a/drivers/net/txgbe/base/txgbe_phy.h
+++ b/drivers/net/txgbe/base/txgbe_phy.h
@@ -340,6 +340,7 @@ s32 txgbe_setup_phy_link(struct txgbe_hw *hw);
s32 txgbe_setup_phy_link_speed(struct txgbe_hw *hw,
u32 speed,
bool autoneg_wait_to_complete);
+s32 txgbe_get_phy_fw_version(struct txgbe_hw *hw, u32 *fw_version);
s32 txgbe_get_copper_link_capabilities(struct txgbe_hw *hw,
u32 *speed,
bool *autoneg);
diff --git a/drivers/net/txgbe/base/txgbe_type.h b/drivers/net/txgbe/base/txgbe_type.h
index 2c8a3866a..40c551697 100644
--- a/drivers/net/txgbe/base/txgbe_type.h
+++ b/drivers/net/txgbe/base/txgbe_type.h
@@ -647,6 +647,7 @@ struct txgbe_phy_info {
s32 (*setup_link_speed)(struct txgbe_hw *hw, u32 speed,
bool autoneg_wait_to_complete);
s32 (*check_link)(struct txgbe_hw *hw, u32 *speed, bool *link_up);
+ s32 (*get_fw_version)(struct txgbe_hw *hw, u32 *fw_version);
s32 (*read_i2c_byte)(struct txgbe_hw *hw, u8 byte_offset,
u8 dev_addr, u8 *data);
s32 (*write_i2c_byte)(struct txgbe_hw *hw, u8 byte_offset,
@@ -747,6 +748,7 @@ struct txgbe_hw {
u16 nb_rx_queues;
u16 nb_tx_queues;
+ u32 fw_version;
u32 mode;
enum txgbe_link_status {
TXGBE_LINK_STATUS_NONE = 0,
diff --git a/drivers/net/txgbe/txgbe_ethdev.c b/drivers/net/txgbe/txgbe_ethdev.c
index 63a987506..2a59a139c 100644
--- a/drivers/net/txgbe/txgbe_ethdev.c
+++ b/drivers/net/txgbe/txgbe_ethdev.c
@@ -2505,14 +2505,11 @@ static int
txgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
{
struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
- u16 eeprom_verh, eeprom_verl;
u32 etrack_id;
int ret;
- hw->rom.readw_sw(hw, TXGBE_EEPROM_VERSION_H, &eeprom_verh);
- hw->rom.readw_sw(hw, TXGBE_EEPROM_VERSION_L, &eeprom_verl);
+ hw->phy.get_fw_version(hw, &etrack_id);
- etrack_id = (eeprom_verh << 16) | eeprom_verl;
ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
ret += 1; /* add the size of '\0' */
--
2.27.0
^ permalink raw reply related [flat|nested] 10+ messages in thread* [dpdk-dev] [PATCH v4 3/6] net/txgbe: update link setup process of backplane NICs
2021-03-29 3:17 [dpdk-dev] [PATCH v4 0/6] txgbe backplane AN training Jiawen Wu
2021-03-29 3:17 ` [dpdk-dev] [PATCH v4 1/6] net/txgbe: update device ID Jiawen Wu
2021-03-29 3:17 ` [dpdk-dev] [PATCH v4 2/6] net/txgbe: move firmware version get function to base code Jiawen Wu
@ 2021-03-29 3:17 ` Jiawen Wu
2021-03-29 3:17 ` [dpdk-dev] [PATCH v4 4/6] net/txgbe/base: support to handle backplane AN73 flow Jiawen Wu
` (3 subsequent siblings)
6 siblings, 0 replies; 10+ messages in thread
From: Jiawen Wu @ 2021-03-29 3:17 UTC (permalink / raw)
To: dev; +Cc: Jiawen Wu
Add device arguments to support runtime options.
And use these configuration to control the link setup flow, to adapt to
different NIC's construction. Use firmware version to control the impact
of firmware update. And fix some left bugs.
Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
---
doc/guides/nics/txgbe.rst | 34 +++++++
drivers/net/txgbe/base/txgbe_eeprom.h | 3 +
drivers/net/txgbe/base/txgbe_hw.c | 85 +---------------
drivers/net/txgbe/base/txgbe_osdep.h | 1 +
drivers/net/txgbe/base/txgbe_phy.c | 141 +++++++++++++++-----------
drivers/net/txgbe/base/txgbe_phy.h | 90 ++++++++++++++--
drivers/net/txgbe/base/txgbe_type.h | 23 ++++-
drivers/net/txgbe/txgbe_ethdev.c | 57 +++++++++++
drivers/net/txgbe/txgbe_logs.h | 9 ++
9 files changed, 299 insertions(+), 144 deletions(-)
diff --git a/doc/guides/nics/txgbe.rst b/doc/guides/nics/txgbe.rst
index e520f13f3..14243079d 100644
--- a/doc/guides/nics/txgbe.rst
+++ b/doc/guides/nics/txgbe.rst
@@ -84,6 +84,40 @@ TXGBE PMD provides the following log types available for control:
Extra logging of the messages during PMD initialization.
+- ``pmd.net.txgbe.bp`` (default level is **notice**)
+
+ Extra logging of auto-negtiation process for backplane NICs.
+ Supply ``--log-level=pmd.net.txgbe.bp:debug`` to view messages.
+
+Runtime Options
+~~~~~~~~~~~~~~~
+
+The following ``devargs`` options can be enabled at runtime. They must
+be passed as part of EAL arguments. For example,
+
+.. code-block:: console
+
+ dpdk-testpmd -a 01:00.0,auto_neg=1 -- -i
+
+Please note that following ``devargs`` are only set for backplane NICs.
+
+- ``auto_neg`` (default **1**)
+
+ Toggle behavior to use auto-negotiation mode or force mode to
+ link up backplane NICs.
+
+- ``poll`` (default **0**)
+
+ Toggle behavior to enable/disable polling mode to receive AN interrupt.
+
+- ``present`` (default **1**)
+
+ Toggle behavior to use present mode or init mode.
+
+- ``sgmii`` (default **0**)
+
+ Special treatment for KX SGMII cards.
+
Driver compilation and testing
------------------------------
diff --git a/drivers/net/txgbe/base/txgbe_eeprom.h b/drivers/net/txgbe/base/txgbe_eeprom.h
index 78b8af978..3a5d7c621 100644
--- a/drivers/net/txgbe/base/txgbe_eeprom.h
+++ b/drivers/net/txgbe/base/txgbe_eeprom.h
@@ -9,6 +9,9 @@
#define TXGBE_PBANUM_PTR_GUARD 0xFAFA
#define TXGBE_EEPROM_SUM 0xBABA
+#define TXGBE_FW_VER_LEN 32
+#define TXGBE_FW_N_TXEQ 0x0002000A
+
#define TXGBE_FW_PTR 0x0F
#define TXGBE_PBANUM0_PTR 0x05
#define TXGBE_PBANUM1_PTR 0x06
diff --git a/drivers/net/txgbe/base/txgbe_hw.c b/drivers/net/txgbe/base/txgbe_hw.c
index 26562f50d..521cb4650 100644
--- a/drivers/net/txgbe/base/txgbe_hw.c
+++ b/drivers/net/txgbe/base/txgbe_hw.c
@@ -91,7 +91,6 @@ s32 txgbe_setup_fc(struct txgbe_hw *hw)
u16 reg_cu = 0;
u32 value = 0;
u64 reg_bp = 0;
- bool locked = false;
DEBUGFUNC("txgbe_setup_fc");
@@ -109,29 +108,6 @@ s32 txgbe_setup_fc(struct txgbe_hw *hw)
if (hw->fc.requested_mode == txgbe_fc_default)
hw->fc.requested_mode = txgbe_fc_full;
- /*
- * Set up the 1G and 10G flow control advertisement registers so the
- * HW will be able to do fc autoneg once the cable is plugged in. If
- * we link at 10G, the 1G advertisement is harmless and vice versa.
- */
- switch (hw->phy.media_type) {
- case txgbe_media_type_backplane:
- /* some MAC's need RMW protection on AUTOC */
- err = hw->mac.prot_autoc_read(hw, &locked, ®_bp);
- if (err != 0)
- goto out;
-
- /* fall through - only backplane uses autoc */
- case txgbe_media_type_fiber_qsfp:
- case txgbe_media_type_fiber:
- case txgbe_media_type_copper:
- hw->phy.read_reg(hw, TXGBE_MD_AUTO_NEG_ADVT,
- TXGBE_MD_DEV_AUTO_NEG, ®_cu);
- break;
- default:
- break;
- }
-
/*
* The possible values of fc.requested_mode are:
* 0: Flow control is completely disabled
@@ -145,13 +121,6 @@ s32 txgbe_setup_fc(struct txgbe_hw *hw)
switch (hw->fc.requested_mode) {
case txgbe_fc_none:
/* Flow control completely disabled by software override. */
- reg &= ~(SR_MII_MMD_AN_ADV_PAUSE_SYM |
- SR_MII_MMD_AN_ADV_PAUSE_ASM);
- if (hw->phy.media_type == txgbe_media_type_backplane)
- reg_bp &= ~(TXGBE_AUTOC_SYM_PAUSE |
- TXGBE_AUTOC_ASM_PAUSE);
- else if (hw->phy.media_type == txgbe_media_type_copper)
- reg_cu &= ~(TXGBE_TAF_SYM_PAUSE | TXGBE_TAF_ASM_PAUSE);
break;
case txgbe_fc_tx_pause:
/*
@@ -159,15 +128,6 @@ s32 txgbe_setup_fc(struct txgbe_hw *hw)
* disabled by software override.
*/
reg |= SR_MII_MMD_AN_ADV_PAUSE_ASM;
- reg &= ~SR_MII_MMD_AN_ADV_PAUSE_SYM;
- if (hw->phy.media_type == txgbe_media_type_backplane) {
- reg_bp |= TXGBE_AUTOC_ASM_PAUSE;
- reg_bp &= ~TXGBE_AUTOC_SYM_PAUSE;
- } else if (hw->phy.media_type == txgbe_media_type_copper) {
- reg_cu |= TXGBE_TAF_ASM_PAUSE;
- reg_cu &= ~TXGBE_TAF_SYM_PAUSE;
- }
- reg |= SR_MII_MMD_AN_ADV_PAUSE_ASM;
reg_bp |= SR_AN_MMD_ADV_REG1_PAUSE_ASM;
break;
case txgbe_fc_rx_pause:
@@ -182,13 +142,6 @@ s32 txgbe_setup_fc(struct txgbe_hw *hw)
*/
case txgbe_fc_full:
/* Flow control (both Rx and Tx) is enabled by SW override. */
- reg |= SR_MII_MMD_AN_ADV_PAUSE_SYM |
- SR_MII_MMD_AN_ADV_PAUSE_ASM;
- if (hw->phy.media_type == txgbe_media_type_backplane)
- reg_bp |= TXGBE_AUTOC_SYM_PAUSE |
- TXGBE_AUTOC_ASM_PAUSE;
- else if (hw->phy.media_type == txgbe_media_type_copper)
- reg_cu |= TXGBE_TAF_SYM_PAUSE | TXGBE_TAF_ASM_PAUSE;
reg |= SR_MII_MMD_AN_ADV_PAUSE_SYM |
SR_MII_MMD_AN_ADV_PAUSE_ASM;
reg_bp |= SR_AN_MMD_ADV_REG1_PAUSE_SYM |
@@ -2575,13 +2528,9 @@ void txgbe_init_mac_link_ops(struct txgbe_hw *hw)
mac->setup_link = txgbe_setup_mac_link_multispeed_fiber;
mac->setup_mac_link = txgbe_setup_mac_link;
mac->set_rate_select_speed = txgbe_set_hard_rate_select_speed;
- } else if ((hw->phy.media_type == txgbe_media_type_backplane) &&
- (hw->phy.smart_speed == txgbe_smart_speed_auto ||
- hw->phy.smart_speed == txgbe_smart_speed_on) &&
- !txgbe_verify_lesm_fw_enabled_raptor(hw)) {
- mac->setup_link = txgbe_setup_mac_link_smartspeed;
} else {
mac->setup_link = txgbe_setup_mac_link;
+ mac->set_rate_select_speed = txgbe_set_hard_rate_select_speed;
}
}
@@ -3309,13 +3258,11 @@ s32 txgbe_setup_mac_link(struct txgbe_hw *hw,
u64 pma_pmd_10gs = autoc & TXGBE_AUTOC_10GS_PMA_PMD_MASK;
u64 pma_pmd_1g = autoc & TXGBE_AUTOC_1G_PMA_PMD_MASK;
u64 link_mode = autoc & TXGBE_AUTOC_LMS_MASK;
- u64 current_autoc = autoc;
u64 orig_autoc = 0;
- u32 links_reg;
- u32 i;
u32 link_capabilities = TXGBE_LINK_SPEED_UNKNOWN;
DEBUGFUNC("txgbe_setup_mac_link");
+ UNREFERENCED_PARAMETER(autoneg_wait_to_complete);
/* Check to see if speed passed in is supported. */
status = hw->mac.get_link_capabilities(hw,
@@ -3346,8 +3293,7 @@ s32 txgbe_setup_mac_link(struct txgbe_hw *hw,
if (speed & TXGBE_LINK_SPEED_10GB_FULL) {
if (orig_autoc & TXGBE_AUTOC_KX4_SUPP)
autoc |= TXGBE_AUTOC_KX4_SUPP;
- if ((orig_autoc & TXGBE_AUTOC_KR_SUPP) &&
- !hw->phy.smart_speed_active)
+ if (orig_autoc & TXGBE_AUTOC_KR_SUPP)
autoc |= TXGBE_AUTOC_KR_SUPP;
}
if (speed & TXGBE_LINK_SPEED_1GB_FULL)
@@ -3374,35 +3320,14 @@ s32 txgbe_setup_mac_link(struct txgbe_hw *hw,
}
}
- if (autoc == current_autoc)
- return status;
-
autoc &= ~TXGBE_AUTOC_SPEED_MASK;
autoc |= TXGBE_AUTOC_SPEED(speed);
+ autoc &= ~TXGBE_AUTOC_AUTONEG;
autoc |= (autoneg ? TXGBE_AUTOC_AUTONEG : 0);
/* Restart link */
hw->mac.autoc_write(hw, autoc);
- /* Only poll for autoneg to complete if specified to do so */
- if (autoneg_wait_to_complete) {
- if (link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR ||
- link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
- link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
- links_reg = 0; /*Just in case Autoneg time=0*/
- for (i = 0; i < TXGBE_AUTO_NEG_TIME; i++) {
- links_reg = rd32(hw, TXGBE_PORTSTAT);
- if (links_reg & TXGBE_PORTSTAT_UP)
- break;
- msec_delay(100);
- }
- if (!(links_reg & TXGBE_PORTSTAT_UP)) {
- status = TXGBE_ERR_AUTONEG_NOT_COMPLETE;
- DEBUGOUT("Autoneg did not complete.\n");
- }
- }
- }
-
/* Add delay to filter out noises during initial link setup */
msec_delay(50);
@@ -3515,6 +3440,7 @@ txgbe_reset_misc(struct txgbe_hw *hw)
/* enable mac transmitter */
wr32m(hw, TXGBE_MACTXCFG, TXGBE_MACTXCFG_TXE, TXGBE_MACTXCFG_TXE);
+ hw->mac.autoc = hw->mac.orig_autoc;
for (i = 0; i < 4; i++)
wr32m(hw, TXGBE_IVAR(i), 0x80808080, 0);
}
@@ -3608,7 +3534,6 @@ s32 txgbe_reset_hw(struct txgbe_hw *hw)
*/
if (!hw->mac.orig_link_settings_stored) {
hw->mac.orig_autoc = hw->mac.autoc_read(hw);
- hw->mac.autoc_write(hw, hw->mac.orig_autoc);
hw->mac.orig_link_settings_stored = true;
} else {
hw->mac.orig_autoc = autoc;
diff --git a/drivers/net/txgbe/base/txgbe_osdep.h b/drivers/net/txgbe/base/txgbe_osdep.h
index e18e400af..074d7a306 100644
--- a/drivers/net/txgbe/base/txgbe_osdep.h
+++ b/drivers/net/txgbe/base/txgbe_osdep.h
@@ -36,6 +36,7 @@
#define msec_delay(x) rte_delay_ms(x)
#define usleep(x) rte_delay_us(x)
#define msleep(x) rte_delay_ms(x)
+#define usec_stamp() (rte_get_timer_cycles() * 1000000 / rte_get_timer_hz())
#define FALSE 0
#define TRUE 1
diff --git a/drivers/net/txgbe/base/txgbe_phy.c b/drivers/net/txgbe/base/txgbe_phy.c
index 1ca6e35a4..33d3839ed 100644
--- a/drivers/net/txgbe/base/txgbe_phy.c
+++ b/drivers/net/txgbe/base/txgbe_phy.c
@@ -9,6 +9,7 @@
static void txgbe_i2c_start(struct txgbe_hw *hw);
static void txgbe_i2c_stop(struct txgbe_hw *hw);
+static s32 txgbe_set_link_to_sfi(struct txgbe_hw *hw, u32 speed);
/**
* txgbe_identify_extphy - Identify a single address for a PHY
@@ -1416,6 +1417,7 @@ static s32
txgbe_set_link_to_kr(struct txgbe_hw *hw, bool autoneg)
{
u32 i;
+ u16 value;
s32 err = 0;
/* 1. Wait xpcs power-up good */
@@ -1430,18 +1432,33 @@ txgbe_set_link_to_kr(struct txgbe_hw *hw, bool autoneg)
err = TXGBE_ERR_XPCS_POWER_UP_FAILED;
goto out;
}
+ BP_LOG("It is set to kr.\n");
+
+ wr32_epcs(hw, VR_AN_INTR_MSK, 0x7);
+ wr32_epcs(hw, TXGBE_PHY_TX_POWER_ST_CTL, 0x00FC);
+ wr32_epcs(hw, TXGBE_PHY_RX_POWER_ST_CTL, 0x00FC);
if (!autoneg) {
/* 2. Disable xpcs AN-73 */
- wr32_epcs(hw, SR_AN_CTRL, 0x0);
- /* Disable PHY MPLLA for eth mode change(after ECO) */
- wr32_ephy(hw, 0x4, 0x243A);
- txgbe_flush(hw);
- msec_delay(1);
- /* Set the eth change_mode bit first in mis_rst register
- * for corresponding LAN port
- */
- wr32(hw, TXGBE_RST, TXGBE_RST_ETH(hw->bus.lan_id));
+ wr32_epcs(hw, SR_AN_CTRL,
+ SR_AN_CTRL_AN_EN | SR_AN_CTRL_EXT_NP);
+
+ wr32_epcs(hw, VR_AN_KR_MODE_CL, VR_AN_KR_MODE_CL_PDET);
+
+ if (!(hw->devarg.auto_neg == 1)) {
+ wr32_epcs(hw, SR_AN_CTRL, 0);
+ wr32_epcs(hw, VR_AN_KR_MODE_CL, 0);
+ }
+ if (hw->devarg.present == 1) {
+ value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1);
+ value |= TXGBE_PHY_TX_EQ_CTL1_DEF;
+ wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
+ }
+ if (hw->devarg.poll == 1) {
+ wr32_epcs(hw, VR_PMA_KRTR_TIMER_CTRL0,
+ VR_PMA_KRTR_TIMER_MAX_WAIT);
+ wr32_epcs(hw, VR_PMA_KRTR_TIMER_CTRL2, 0xA697);
+ }
/* 3. Set VR_XS_PMA_Gen5_12G_MPLLA_CTRL3 Register
* Bit[10:0](MPLLA_BANDWIDTH) = 11'd123 (default: 11'd16)
@@ -1501,6 +1518,10 @@ txgbe_set_link_to_kx4(struct txgbe_hw *hw, bool autoneg)
if (hw->link_status == TXGBE_LINK_STATUS_KX4)
goto out;
+ BP_LOG("It is set to kx4.\n");
+ wr32_epcs(hw, TXGBE_PHY_TX_POWER_ST_CTL, 0);
+ wr32_epcs(hw, TXGBE_PHY_RX_POWER_ST_CTL, 0);
+
/* 1. Wait xpcs power-up good */
for (i = 0; i < 100; i++) {
if ((rd32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_STATUS) &
@@ -1545,16 +1566,13 @@ txgbe_set_link_to_kx4(struct txgbe_hw *hw, bool autoneg)
wr32_epcs(hw, SR_PMA_CTRL1,
SR_PMA_CTRL1_SS13_KX4);
- value = (0xf5f0 & ~0x7F0) | (0x5 << 8) | (0x7 << 5) | 0x10;
+ value = (0xf5f0 & ~0x7F0) | (0x5 << 8) | (0x7 << 5) | 0xF0;
wr32_epcs(hw, TXGBE_PHY_TX_GENCTRL1, value);
- wr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0x4F00);
-
- value = (0x1804 & ~0x3F3F);
- wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
-
- value = (0x50 & ~0x7F) | 40 | (1 << 6);
- wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
+ if ((hw->subsystem_device_id & 0xFF) == TXGBE_DEV_ID_MAC_XAUI)
+ wr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0xCF00);
+ else
+ wr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0x4F00);
for (i = 0; i < 4; i++) {
if (i == 0)
@@ -1682,6 +1700,13 @@ txgbe_set_link_to_kx4(struct txgbe_hw *hw, bool autoneg)
goto out;
}
+ if (hw->fw_version <= TXGBE_FW_N_TXEQ) {
+ value = (0x1804 & ~0x3F3F);
+ wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
+
+ value = (0x50 & ~0x7F) | 40 | (1 << 6);
+ wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
+ }
out:
return err;
}
@@ -1700,6 +1725,10 @@ txgbe_set_link_to_kx(struct txgbe_hw *hw,
if (hw->link_status == TXGBE_LINK_STATUS_KX)
goto out;
+ BP_LOG("It is set to kx. speed =0x%x\n", speed);
+ wr32_epcs(hw, TXGBE_PHY_TX_POWER_ST_CTL, 0x00FC);
+ wr32_epcs(hw, TXGBE_PHY_RX_POWER_ST_CTL, 0x00FC);
+
/* 1. Wait xpcs power-up good */
for (i = 0; i < 100; i++) {
if ((rd32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_STATUS) &
@@ -1756,16 +1785,13 @@ txgbe_set_link_to_kx(struct txgbe_hw *hw,
wr32_epcs(hw, SR_MII_MMD_CTL,
wdata);
- value = (0xf5f0 & ~0x710) | (0x5 << 8);
+ value = (0xf5f0 & ~0x710) | (0x5 << 8) | 0x10;
wr32_epcs(hw, TXGBE_PHY_TX_GENCTRL1, value);
- wr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0x4F00);
-
- value = (0x1804 & ~0x3F3F) | (24 << 8) | 4;
- wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
-
- value = (0x50 & ~0x7F) | 16 | (1 << 6);
- wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
+ if (hw->devarg.sgmii == 1)
+ wr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0x4F00);
+ else
+ wr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0xCF00);
for (i = 0; i < 4; i++) {
if (i) {
@@ -1881,6 +1907,13 @@ txgbe_set_link_to_kx(struct txgbe_hw *hw,
goto out;
}
+ if (hw->fw_version <= TXGBE_FW_N_TXEQ) {
+ value = (0x1804 & ~0x3F3F) | (24 << 8) | 4;
+ wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
+
+ value = (0x50 & ~0x7F) | 16 | (1 << 6);
+ wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
+ }
out:
return err;
}
@@ -1977,18 +2010,7 @@ txgbe_set_link_to_sfi(struct txgbe_hw *hw,
* MPLLA_DIV8_CLK_EN=0
*/
wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL2, 0x0600);
- /* 5. Set VR_XS_PMA_Gen5_12G_TX_EQ_CTRL0 Register
- * Bit[13:8](TX_EQ_MAIN) = 6'd30, Bit[5:0](TX_EQ_PRE) = 6'd4
- */
- value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0);
- value = (value & ~0x3F3F) | (24 << 8) | 4;
- wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
- /* 6. Set VR_XS_PMA_Gen5_12G_TX_EQ_CTRL1 Register
- * Bit[6](TX_EQ_OVR_RIDE) = 1'b1, Bit[5:0](TX_EQ_POST) = 6'd36
- */
- value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1);
- value = (value & ~0x7F) | 16 | (1 << 6);
- wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
+
if (hw->phy.sfp_type == txgbe_sfp_type_da_cu_core0 ||
hw->phy.sfp_type == txgbe_sfp_type_da_cu_core1) {
/* 7. Set VR_XS_PMA_Gen5_12G_RX_EQ_CTRL0 Register
@@ -2055,18 +2077,7 @@ txgbe_set_link_to_sfi(struct txgbe_hw *hw,
* Bit[12:8](RX_VREF_CTRL) = 5'hF
*/
wr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0xCF00);
- /* 5. Set VR_XS_PMA_Gen5_12G_TX_EQ_CTRL0 Register
- * Bit[13:8](TX_EQ_MAIN) = 6'd30, Bit[5:0](TX_EQ_PRE) = 6'd4
- */
- value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0);
- value = (value & ~0x3F3F) | (24 << 8) | 4;
- wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
- /* 6. Set VR_XS_PMA_Gen5_12G_TX_EQ_CTRL1 Register Bit[6]
- * (TX_EQ_OVR_RIDE) = 1'b1, Bit[5:0](TX_EQ_POST) = 6'd36
- */
- value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1);
- value = (value & ~0x7F) | 16 | (1 << 6);
- wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
+
if (hw->phy.sfp_type == txgbe_sfp_type_da_cu_core0 ||
hw->phy.sfp_type == txgbe_sfp_type_da_cu_core1) {
wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0, 0x774F);
@@ -2123,6 +2134,15 @@ txgbe_set_link_to_sfi(struct txgbe_hw *hw,
goto out;
}
+ if (hw->fw_version <= TXGBE_FW_N_TXEQ) {
+ value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0);
+ value = (value & ~0x3F3F) | (24 << 8) | 4;
+ wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
+
+ value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1);
+ value = (value & ~0x7F) | 16 | (1 << 6);
+ wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
+ }
out:
return err;
}
@@ -2133,13 +2153,15 @@ txgbe_set_link_to_sfi(struct txgbe_hw *hw,
*/
u64 txgbe_autoc_read(struct txgbe_hw *hw)
{
- u64 autoc = 0;
+ u64 autoc;
u32 sr_pcs_ctl;
u32 sr_pma_ctl1;
u32 sr_an_ctl;
u32 sr_an_adv_reg2;
u8 type = hw->subsystem_device_id & 0xFF;
+ autoc = hw->mac.autoc;
+
if (hw->phy.multispeed_fiber) {
autoc |= TXGBE_AUTOC_LMS_10G;
} else if (type == TXGBE_DEV_ID_SFP) {
@@ -2195,11 +2217,11 @@ u64 txgbe_autoc_read(struct txgbe_hw *hw)
} else if ((sr_an_ctl & SR_AN_CTRL_AN_EN)) {
/* KX/KX4/KR backplane auto-negotiation enable */
if (sr_an_adv_reg2 & SR_AN_MMD_ADV_REG2_BP_TYPE_KR)
- autoc |= TXGBE_AUTOC_10G_KR;
+ autoc |= TXGBE_AUTOC_KR_SUPP;
if (sr_an_adv_reg2 & SR_AN_MMD_ADV_REG2_BP_TYPE_KX4)
- autoc |= TXGBE_AUTOC_10G_KX4;
+ autoc |= TXGBE_AUTOC_KX4_SUPP;
if (sr_an_adv_reg2 & SR_AN_MMD_ADV_REG2_BP_TYPE_KX)
- autoc |= TXGBE_AUTOC_1G_KX;
+ autoc |= TXGBE_AUTOC_KX_SUPP;
autoc |= TXGBE_AUTOC_LMS_KX4_KX_KR;
hw->phy.link_mode = TXGBE_PHYSICAL_LAYER_10GBASE_KR |
TXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
@@ -2221,7 +2243,7 @@ void txgbe_autoc_write(struct txgbe_hw *hw, u64 autoc)
u32 mactxcfg = 0;
u8 device_type = hw->subsystem_device_id & 0xFF;
- speed = TXGBE_AUTOC_SPEED(autoc);
+ speed = TXGBD_AUTOC_SPEED(autoc);
autoc &= ~TXGBE_AUTOC_SPEED_MASK;
autoneg = (autoc & TXGBE_AUTOC_AUTONEG ? true : false);
autoc &= ~TXGBE_AUTOC_AUTONEG;
@@ -2241,6 +2263,8 @@ void txgbe_autoc_write(struct txgbe_hw *hw, u64 autoc)
default:
return;
}
+ } else {
+ txgbe_set_link_to_kr(hw, !autoneg);
}
} else if (device_type == TXGBE_DEV_ID_XAUI ||
device_type == TXGBE_DEV_ID_SGMII ||
@@ -2249,10 +2273,11 @@ void txgbe_autoc_write(struct txgbe_hw *hw, u64 autoc)
(device_type == TXGBE_DEV_ID_SFI_XAUI &&
hw->phy.media_type == txgbe_media_type_copper)) {
if (speed == TXGBE_LINK_SPEED_10GB_FULL) {
- txgbe_set_link_to_kx4(hw, autoneg);
+ txgbe_set_link_to_kx4(hw, 0);
} else {
txgbe_set_link_to_kx(hw, speed, 0);
- txgbe_set_sgmii_an37_ability(hw);
+ if (hw->devarg.auto_neg == 1)
+ txgbe_set_sgmii_an37_ability(hw);
}
} else if (hw->phy.media_type == txgbe_media_type_fiber) {
txgbe_set_link_to_sfi(hw, speed);
@@ -2264,6 +2289,8 @@ void txgbe_autoc_write(struct txgbe_hw *hw, u64 autoc)
mactxcfg = TXGBE_MACTXCFG_SPEED_1G;
/* enable mac transmitter */
- wr32m(hw, TXGBE_MACTXCFG, TXGBE_MACTXCFG_SPEED_MASK, mactxcfg);
+ wr32m(hw, TXGBE_MACTXCFG,
+ TXGBE_MACTXCFG_SPEED_MASK | TXGBE_MACTXCFG_TXE,
+ mactxcfg | TXGBE_MACTXCFG_TXE);
}
diff --git a/drivers/net/txgbe/base/txgbe_phy.h b/drivers/net/txgbe/base/txgbe_phy.h
index 4a5b90077..b804d2406 100644
--- a/drivers/net/txgbe/base/txgbe_phy.h
+++ b/drivers/net/txgbe/base/txgbe_phy.h
@@ -18,11 +18,27 @@
#define SR_PCS_CTRL2_TYPE_SEL_R LS16(0, 0, 0x3)
#define SR_PCS_CTRL2_TYPE_SEL_X LS16(1, 0, 0x3)
#define SR_PCS_CTRL2_TYPE_SEL_W LS16(2, 0, 0x3)
+#define SR_XS_PCS_KR_STS1 0x030020
+#define SR_XS_PCS_KR_STS1_PLU MS16(12, 0x1)
#define SR_PMA_CTRL1 0x010000
#define SR_PMA_CTRL1_SS13 MS16(13, 0x1)
#define SR_PMA_CTRL1_SS13_KX LS16(0, 13, 0x1)
#define SR_PMA_CTRL1_SS13_KX4 LS16(1, 13, 0x1)
#define SR_PMA_CTRL1_LB MS16(0, 0x1)
+#define SR_PMA_KR_PMD_CTRL 0x010096
+#define SR_PMA_KR_PMD_CTRL_EN_TR MS16(1, 0x1)
+#define SR_PMA_KR_PMD_CTRL_RS_TR MS16(0, 0x1)
+#define SR_PMA_KR_PMD_STS 0x010097
+#define SR_PMA_KR_PMD_STS_TR_FAIL MS16(3, 0x1)
+#define SR_PMA_KR_PMD_STS_RCV MS16(0, 0x1)
+#define SR_PMA_KR_LP_CEU 0x010098
+#define SR_PMA_KR_LP_CESTS 0x010099
+#define SR_PMA_KR_LP_CESTS_RR MS16(15, 0x1)
+#define SR_PMA_KR_LD_CEU 0x01009A
+#define SR_PMA_KR_LD_CESTS 0x01009B
+#define SR_PMA_KR_LD_CESTS_RR MS16(15, 0x1)
+#define SR_PMA_KR_FEC_CTRL 0x0100AB
+#define SR_PMA_KR_FEC_CTRL_EN MS16(0, 0x1)
#define SR_MII_MMD_CTL 0x1F0000
#define SR_MII_MMD_CTL_AN_EN 0x1000
#define SR_MII_MMD_CTL_RESTART_AN 0x0200
@@ -33,26 +49,80 @@
#define SR_MII_MMD_AN_ADV_PAUSE_ASM 0x80
#define SR_MII_MMD_AN_ADV_PAUSE_SYM 0x100
#define SR_MII_MMD_LP_BABL 0x1F0005
+
+#define BP_TYPE_KX 0x20
+#define BP_TYPE_KX4 0x40
+#define BP_TYPE_KX4_KX 0x60
+#define BP_TYPE_KR 0x80
+#define BP_TYPE_KR_KX 0xA0
+#define BP_TYPE_KR_KX4 0xC0
+#define BP_TYPE_KR_KX4_KX 0xE0
+
#define SR_AN_CTRL 0x070000
#define SR_AN_CTRL_RSTRT_AN MS16(9, 0x1)
#define SR_AN_CTRL_AN_EN MS16(12, 0x1)
+#define SR_AN_CTRL_EXT_NP MS16(13, 0x1)
#define SR_AN_MMD_ADV_REG1 0x070010
#define SR_AN_MMD_ADV_REG1_PAUSE(v) ((0x3 & (v)) << 10)
#define SR_AN_MMD_ADV_REG1_PAUSE_SYM 0x400
#define SR_AN_MMD_ADV_REG1_PAUSE_ASM 0x800
-#define SR_AN_MMD_ADV_REG2 0x070011
-#define SR_AN_MMD_ADV_REG2_BP_TYPE_KX4 0x40
-#define SR_AN_MMD_ADV_REG2_BP_TYPE_KX 0x20
-#define SR_AN_MMD_ADV_REG2_BP_TYPE_KR 0x80
-#define SR_AN_MMD_ADV_REG2_BP_TYPE_MASK 0xFFFF
+#define SR_AN_MMD_ADV_REG1_NP(v) RS16(v, 15, 0x1)
+#define SR_AN_MMD_ADV_REG2 0x070011
+#define SR_AN_MMD_ADV_REG2_BP_TYPE_KX4 BP_TYPE_KX4
+#define SR_AN_MMD_ADV_REG2_BP_TYPE_KX BP_TYPE_KX
+#define SR_AN_MMD_ADV_REG2_BP_TYPE_KR BP_TYPE_KR
+#define SR_AN_MMD_ADV_REG2_BP_TYPE_KX4_KX BP_TYPE_KX4_KX
+#define SR_AN_MMD_ADV_REG2_BP_TYPE_KR_KX BP_TYPE_KR_KX
+#define SR_AN_MMD_ADV_REG2_BP_TYPE_KR_KX4 BP_TYPE_KR_KX4
+#define SR_AN_MMD_ADV_REG2_BP_TYPE_KR_KX4_KX BP_TYPE_KR_KX4_KX
+#define SR_AN_MMD_ADV_REG2_BP_TYPE_MASK 0xFFFF
+#define SR_AN_MMD_ADV_REG3 0x070012
+#define SR_AN_MMD_ADV_REG3_FCE(v) RS16(v, 14, 0x3)
#define SR_AN_MMD_LP_ABL1 0x070013
+#define SR_MMD_LP_ABL1_ADV_NP(v) RS16(v, 15, 0x1)
+#define SR_AN_MMD_LP_ABL2 0x070014
+#define SR_AN_MMD_LP_ABL2_BP_TYPE_KX4 BP_TYPE_KX4
+#define SR_AN_MMD_LP_ABL2_BP_TYPE_KX BP_TYPE_KX
+#define SR_AN_MMD_LP_ABL2_BP_TYPE_KR BP_TYPE_KR
+#define SR_AN_MMD_LP_ABL2_BP_TYPE_KX4_KX BP_TYPE_KX4_KX
+#define SR_AN_MMD_LP_ABL2_BP_TYPE_KR_KX BP_TYPE_KR_KX
+#define SR_AN_MMD_LP_ABL2_BP_TYPE_KR_KX4 BP_TYPE_KR_KX4
+#define SR_AN_MMD_LP_ABL2_BP_TYPE_KR_KX4_KX BP_TYPE_KR_KX4_KX
+#define SR_AN_MMD_LP_ABL2_BP_TYPE_MASK 0xFFFF
+#define SR_AN_MMD_LP_ABL3 0x070015
+#define SR_AN_MMD_LP_ABL3_FCE(v) RS16(v, 14, 0x3)
+#define SR_AN_XNP_TX1 0x070016
+#define SR_AN_XNP_TX1_NP MS16(15, 0x1)
+#define SR_AN_LP_XNP_ABL1 0x070019
+#define SR_AN_LP_XNP_ABL1_NP(v) RS16(v, 15, 0x1)
+
+#define VR_AN_INTR_MSK 0x078001
+#define VR_AN_INTR_CMPLT_IE MS16(0, 0x1)
+#define VR_AN_INTR_LINK_IE MS16(1, 0x1)
+#define VR_AN_INTR_PG_RCV_IE MS16(2, 0x1)
+#define VR_AN_INTR 0x078002
+#define VR_AN_INTR_CMPLT MS16(0, 0x1)
+#define VR_AN_INTR_LINK MS16(1, 0x1)
+#define VR_AN_INTR_PG_RCV MS16(2, 0x1)
#define VR_AN_KR_MODE_CL 0x078003
+#define VR_AN_KR_MODE_CL_PDET MS16(0, 0x1)
#define VR_XS_OR_PCS_MMD_DIGI_CTL1 0x038000
#define VR_XS_OR_PCS_MMD_DIGI_CTL1_ENABLE 0x1000
#define VR_XS_OR_PCS_MMD_DIGI_CTL1_VR_RST 0x8000
+#define VR_XS_OR_PCS_MMD_DIGI_CTL2 0x038001
#define VR_XS_OR_PCS_MMD_DIGI_STATUS 0x038010
#define VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_MASK 0x1C
#define VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_POWER_GOOD 0x10
+#define VR_PMA_KRTR_PRBS_CTRL0 0x018003
+#define VR_PMA_KRTR_PRBS31_EN MS16(1, 0x1)
+#define VR_PMA_KRTR_PRBS_MODE_EN MS16(0, 0x1)
+#define VR_PMA_KRTR_PRBS_CTRL1 0x018004
+#define VR_PMA_KRTR_PRBS_TIME_LMT MS16(0, 0xFFFF)
+#define VR_PMA_KRTR_PRBS_CTRL2 0x018005
+#define VR_PMA_KRTR_PRBS_ERR_LIM MS16(0, 0x2FFF)
+#define VR_PMA_KRTR_TIMER_CTRL0 0x018006
+#define VR_PMA_KRTR_TIMER_MAX_WAIT MS16(0, 0xFFFF)
+#define VR_PMA_KRTR_TIMER_CTRL2 0x018008
#define TXGBE_PHY_MPLLA_CTL0 0x018071
#define TXGBE_PHY_MPLLA_CTL3 0x018077
@@ -71,6 +141,7 @@
#define TXGBE_PHY_RX_EQ_CTL 0x01805C
#define TXGBE_PHY_TX_EQ_CTL0 0x018036
#define TXGBE_PHY_TX_EQ_CTL1 0x018037
+#define TXGBE_PHY_TX_EQ_CTL1_DEF MS16(7, 0x1)
#define TXGBE_PHY_TX_RATE_CTL 0x018034
#define TXGBE_PHY_RX_RATE_CTL 0x018054
#define TXGBE_PHY_TX_GEN_CTL2 0x018032
@@ -80,12 +151,14 @@
#define TXGBE_PHY_RX_POWER_ST_CTL 0x018055
#define TXGBE_PHY_TX_POWER_ST_CTL 0x018035
#define TXGBE_PHY_TX_GENCTRL1 0x018031
+#define TXGBE_PHY_EQ_INIT_CTL0 0x01803A
+#define TXGBE_PHY_EQ_INIT_CTL1 0x01803B
#define TXGBE_PHY_MPLLA_CTL0_MULTIPLIER_1GBASEX_KX 32
#define TXGBE_PHY_MPLLA_CTL0_MULTIPLIER_10GBASER_KR 33
#define TXGBE_PHY_MPLLA_CTL0_MULTIPLIER_OTHER 40
#define TXGBE_PHY_MPLLA_CTL0_MULTIPLIER_MASK 0xFF
-#define TXGBE_PHY_MPLLA_CTL3_MULTIPLIER_BW_1GBASEX_KX 0x46
+#define TXGBE_PHY_MPLLA_CTL3_MULTIPLIER_BW_1GBASEX_KX 0x56
#define TXGBE_PHY_MPLLA_CTL3_MULTIPLIER_BW_10GBASER_KR 0x7B
#define TXGBE_PHY_MPLLA_CTL3_MULTIPLIER_BW_OTHER 0x56
#define TXGBE_PHY_MPLLA_CTL3_MULTIPLIER_BW_MASK 0x7FF
@@ -151,6 +224,11 @@
#define TXGBE_PHY_MPLLA_CTL2_DIV_CLK_EN_10 0x200
#define TXGBE_PHY_MPLLA_CTL2_DIV_CLK_EN_16P5 0x400
#define TXGBE_PHY_MPLLA_CTL2_DIV_CLK_EN_MASK 0x700
+#define TXGBE_PHY_LANE0_TX_EQ_CTL1 0x100E
+#define TXGBE_PHY_LANE0_TX_EQ_CTL1_MAIN(v) RS16(v, 6, 0x3F)
+#define TXGBE_PHY_LANE0_TX_EQ_CTL2 0x100F
+#define TXGBE_PHY_LANE0_TX_EQ_CTL2_PRE MS16(0, 0x3F)
+#define TXGBE_PHY_LANE0_TX_EQ_CTL2_POST(v) RS16(v, 6, 0x3F)
/******************************************************************************
* SFP I2C Registers:
diff --git a/drivers/net/txgbe/base/txgbe_type.h b/drivers/net/txgbe/base/txgbe_type.h
index 40c551697..33572cc3c 100644
--- a/drivers/net/txgbe/base/txgbe_type.h
+++ b/drivers/net/txgbe/base/txgbe_type.h
@@ -617,9 +617,10 @@ struct txgbe_mac_info {
u32 rx_pb_size;
u32 max_tx_queues;
u32 max_rx_queues;
+ u64 autoc;
+ u64 orig_autoc; /* cached value of AUTOC */
u8 san_mac_rar_index;
bool get_link_status;
- u64 orig_autoc; /* cached value of AUTOC */
bool orig_link_settings_stored;
bool autotry_restart;
u8 flags;
@@ -685,6 +686,18 @@ struct txgbe_phy_info {
u32 link_mode;
};
+#define TXGBE_DEVARG_BP_AUTO "auto_neg"
+#define TXGBE_DEVARG_KR_POLL "poll"
+#define TXGBE_DEVARG_KR_PRESENT "present"
+#define TXGBE_DEVARG_KX_SGMII "sgmii"
+
+static const char * const txgbe_valid_arguments[] = {
+ TXGBE_DEVARG_BP_AUTO,
+ TXGBE_DEVARG_KR_POLL,
+ TXGBE_DEVARG_KR_PRESENT,
+ TXGBE_DEVARG_KX_SGMII,
+};
+
struct txgbe_mbx_stats {
u32 msgs_tx;
u32 msgs_rx;
@@ -721,6 +734,13 @@ enum txgbe_isb_idx {
TXGBE_ISB_MAX
};
+struct txgbe_devargs {
+ u16 auto_neg;
+ u16 poll;
+ u16 present;
+ u16 sgmii;
+};
+
struct txgbe_hw {
void IOMEM *hw_addr;
void *back;
@@ -742,6 +762,7 @@ struct txgbe_hw {
int api_version;
bool allow_unsupported_sfp;
bool need_crosstalk_fix;
+ struct txgbe_devargs devarg;
uint64_t isb_dma;
void IOMEM *isb_mem;
diff --git a/drivers/net/txgbe/txgbe_ethdev.c b/drivers/net/txgbe/txgbe_ethdev.c
index 2a59a139c..447a511ca 100644
--- a/drivers/net/txgbe/txgbe_ethdev.c
+++ b/drivers/net/txgbe/txgbe_ethdev.c
@@ -16,6 +16,7 @@
#include <rte_memory.h>
#include <rte_eal.h>
#include <rte_alarm.h>
+#include <rte_kvargs.h>
#include "txgbe_logs.h"
#include "base/txgbe.h"
@@ -469,6 +470,55 @@ txgbe_swfw_lock_reset(struct txgbe_hw *hw)
hw->mac.release_swfw_sync(hw, mask);
}
+static int
+txgbe_handle_devarg(__rte_unused const char *key, const char *value,
+ void *extra_args)
+{
+ uint16_t *n = extra_args;
+
+ if (value == NULL || extra_args == NULL)
+ return -EINVAL;
+
+ *n = (uint16_t)strtoul(value, NULL, 10);
+ if (*n == USHRT_MAX && errno == ERANGE)
+ return -1;
+
+ return 0;
+}
+
+static void
+txgbe_parse_devargs(struct txgbe_hw *hw, struct rte_devargs *devargs)
+{
+ struct rte_kvargs *kvlist;
+ u16 auto_neg = 1;
+ u16 poll = 0;
+ u16 present = 1;
+ u16 sgmii = 0;
+
+ if (devargs == NULL)
+ goto null;
+
+ kvlist = rte_kvargs_parse(devargs->args, txgbe_valid_arguments);
+ if (kvlist == NULL)
+ goto null;
+
+ rte_kvargs_process(kvlist, TXGBE_DEVARG_BP_AUTO,
+ &txgbe_handle_devarg, &auto_neg);
+ rte_kvargs_process(kvlist, TXGBE_DEVARG_KR_POLL,
+ &txgbe_handle_devarg, &poll);
+ rte_kvargs_process(kvlist, TXGBE_DEVARG_KR_PRESENT,
+ &txgbe_handle_devarg, &present);
+ rte_kvargs_process(kvlist, TXGBE_DEVARG_KX_SGMII,
+ &txgbe_handle_devarg, &sgmii);
+ rte_kvargs_free(kvlist);
+
+null:
+ hw->devarg.auto_neg = auto_neg;
+ hw->devarg.poll = poll;
+ hw->devarg.present = present;
+ hw->devarg.sgmii = sgmii;
+}
+
static int
eth_txgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
{
@@ -537,6 +587,7 @@ eth_txgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
hw->isb_dma = TMZ_PADDR(mz);
hw->isb_mem = TMZ_VADDR(mz);
+ txgbe_parse_devargs(hw, pci_dev->device.devargs);
/* Initialize the shared code (base driver) */
err = txgbe_init_shared_code(hw);
if (err != 0) {
@@ -5234,9 +5285,15 @@ static const struct eth_dev_ops txgbe_eth_dev_ops = {
RTE_PMD_REGISTER_PCI(net_txgbe, rte_txgbe_pmd);
RTE_PMD_REGISTER_PCI_TABLE(net_txgbe, pci_id_txgbe_map);
RTE_PMD_REGISTER_KMOD_DEP(net_txgbe, "* igb_uio | uio_pci_generic | vfio-pci");
+RTE_PMD_REGISTER_PARAM_STRING(net_txgbe,
+ TXGBE_DEVARG_BP_AUTO "=<0|1>"
+ TXGBE_DEVARG_KR_POLL "=<0|1>"
+ TXGBE_DEVARG_KR_PRESENT "=<0|1>"
+ TXGBE_DEVARG_KX_SGMII "=<0|1>");
RTE_LOG_REGISTER(txgbe_logtype_init, pmd.net.txgbe.init, NOTICE);
RTE_LOG_REGISTER(txgbe_logtype_driver, pmd.net.txgbe.driver, NOTICE);
+RTE_LOG_REGISTER(txgbe_logtype_bp, pmd.net.txgbe.bp, NOTICE);
#ifdef RTE_LIBRTE_TXGBE_DEBUG_RX
RTE_LOG_REGISTER(txgbe_logtype_rx, pmd.net.txgbe.rx, DEBUG);
diff --git a/drivers/net/txgbe/txgbe_logs.h b/drivers/net/txgbe/txgbe_logs.h
index f44ca06ee..6764466e2 100644
--- a/drivers/net/txgbe/txgbe_logs.h
+++ b/drivers/net/txgbe/txgbe_logs.h
@@ -5,6 +5,8 @@
#ifndef _TXGBE_LOGS_H_
#define _TXGBE_LOGS_H_
+#include <inttypes.h>
+
/*
* PMD_USER_LOG: for user
*/
@@ -51,4 +53,11 @@ extern int txgbe_logtype_tx_free;
#define PMD_INIT_FUNC_TRACE() TLOG_DEBUG(" >>")
#define DEBUGFUNC(fmt) TLOG_DEBUG(fmt)
+extern int txgbe_logtype_bp;
+#define BP_LOG(fmt, args...) \
+ rte_log(RTE_LOG_DEBUG, txgbe_logtype_bp, \
+ "[%"PRIu64".%"PRIu64"]%s(%d): " fmt, \
+ usec_stamp() / 1000000, usec_stamp() % 1000000, \
+ __func__, __LINE__, ##args)
+
#endif /* _TXGBE_LOGS_H_ */
--
2.27.0
^ permalink raw reply related [flat|nested] 10+ messages in thread* [dpdk-dev] [PATCH v4 4/6] net/txgbe/base: support to handle backplane AN73 flow
2021-03-29 3:17 [dpdk-dev] [PATCH v4 0/6] txgbe backplane AN training Jiawen Wu
` (2 preceding siblings ...)
2021-03-29 3:17 ` [dpdk-dev] [PATCH v4 3/6] net/txgbe: update link setup process of backplane NICs Jiawen Wu
@ 2021-03-29 3:17 ` Jiawen Wu
2021-03-29 3:17 ` [dpdk-dev] [PATCH v4 5/6] net/txgbe: handle AN interrupt and link update Jiawen Wu
` (2 subsequent siblings)
6 siblings, 0 replies; 10+ messages in thread
From: Jiawen Wu @ 2021-03-29 3:17 UTC (permalink / raw)
To: dev; +Cc: Jiawen Wu
Suppot to handle the interrupt of auto-negotiation, improve the
link training process of connecting with other switches.
Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
---
drivers/net/txgbe/base/txgbe_hw.c | 3 +
drivers/net/txgbe/base/txgbe_phy.c | 461 +++++++++++++++++++++++++++-
drivers/net/txgbe/base/txgbe_phy.h | 5 +
drivers/net/txgbe/base/txgbe_type.h | 9 +
4 files changed, 476 insertions(+), 2 deletions(-)
diff --git a/drivers/net/txgbe/base/txgbe_hw.c b/drivers/net/txgbe/base/txgbe_hw.c
index 521cb4650..9a82a329a 100644
--- a/drivers/net/txgbe/base/txgbe_hw.c
+++ b/drivers/net/txgbe/base/txgbe_hw.c
@@ -2574,6 +2574,9 @@ s32 txgbe_init_phy_raptor(struct txgbe_hw *hw)
txgbe_get_copper_link_capabilities;
}
+ if (phy->media_type == txgbe_media_type_backplane)
+ mac->kr_handle = txgbe_kr_handle;
+
/* Set necessary function pointers based on PHY type */
switch (hw->phy.type) {
case txgbe_phy_tn:
diff --git a/drivers/net/txgbe/base/txgbe_phy.c b/drivers/net/txgbe/base/txgbe_phy.c
index 33d3839ed..140857121 100644
--- a/drivers/net/txgbe/base/txgbe_phy.c
+++ b/drivers/net/txgbe/base/txgbe_phy.c
@@ -9,6 +9,17 @@
static void txgbe_i2c_start(struct txgbe_hw *hw);
static void txgbe_i2c_stop(struct txgbe_hw *hw);
+static s32 txgbe_handle_bp_flow(u32 link_mode, struct txgbe_hw *hw);
+static void txgbe_get_bp_ability(struct txgbe_backplane_ability *ability,
+ u32 link_partner, struct txgbe_hw *hw);
+static s32 txgbe_check_bp_ability(struct txgbe_backplane_ability *local_ability,
+ struct txgbe_backplane_ability *lp_ability, struct txgbe_hw *hw);
+static void txgbe_clear_bp_intr(u32 bit, u32 bit_high, struct txgbe_hw *hw);
+static s32 txgbe_enable_kr_training(struct txgbe_hw *hw);
+static s32 txgbe_disable_kr_training(struct txgbe_hw *hw, s32 post, s32 mode);
+static s32 txgbe_check_kr_training(struct txgbe_hw *hw);
+static void txgbe_read_phy_lane_tx_eq(u16 lane, struct txgbe_hw *hw,
+ s32 post, s32 mode);
static s32 txgbe_set_link_to_sfi(struct txgbe_hw *hw, u32 speed);
/**
@@ -1399,7 +1410,7 @@ static void txgbe_i2c_stop(struct txgbe_hw *hw)
wr32(hw, TXGBE_I2CENA, 0);
}
-static s32
+static void
txgbe_set_sgmii_an37_ability(struct txgbe_hw *hw)
{
u32 value;
@@ -1410,7 +1421,6 @@ txgbe_set_sgmii_an37_ability(struct txgbe_hw *hw)
value = rd32_epcs(hw, SR_MII_MMD_CTL);
value = (value & ~0x1200) | (0x1 << 12) | (0x1 << 9);
wr32_epcs(hw, SR_MII_MMD_CTL, value);
- return 0;
}
static s32
@@ -2294,3 +2304,450 @@ void txgbe_autoc_write(struct txgbe_hw *hw, u64 autoc)
mactxcfg | TXGBE_MACTXCFG_TXE);
}
+/**
+ * txgbe_kr_handle - Handle the interrupt of auto-negotiation
+ * @hw: pointer to hardware structure
+ */
+s32 txgbe_kr_handle(struct txgbe_hw *hw)
+{
+ u32 value;
+ s32 status = 0;
+
+ DEBUGFUNC("txgbe_kr_handle");
+
+ value = rd32_epcs(hw, VR_AN_INTR);
+ BP_LOG("AN INTERRUPT!! value: 0x%x\n", value);
+ if (!(value & VR_AN_INTR_PG_RCV)) {
+ wr32_epcs(hw, VR_AN_INTR, 0);
+ return status;
+ }
+
+ status = txgbe_handle_bp_flow(0, hw);
+
+ return status;
+}
+
+/**
+ * txgbe_handle_bp_flow - Handle backplane AN73 flow
+ * @hw: pointer to hardware structure
+ * @link_mode: local AN73 link mode
+ */
+static s32 txgbe_handle_bp_flow(u32 link_mode, struct txgbe_hw *hw)
+{
+ u32 value, i, lp_reg, ld_reg;
+ s32 status = 0;
+ struct txgbe_backplane_ability local_ability, lp_ability;
+
+ DEBUGFUNC("txgbe_handle_bp_flow");
+
+ local_ability.current_link_mode = link_mode;
+
+ /* 1. Get the local AN73 Base Page Ability */
+ BP_LOG("<1>. Get the local AN73 Base Page Ability ...\n");
+ txgbe_get_bp_ability(&local_ability, 0, hw);
+
+ /* 2. Check and clear the AN73 Interrupt Status */
+ BP_LOG("<2>. Check the AN73 Interrupt Status ...\n");
+ txgbe_clear_bp_intr(2, 0, hw);
+
+ /* 3.1. Get the link partner AN73 Base Page Ability */
+ BP_LOG("<3.1>. Get the link partner AN73 Base Page Ability ...\n");
+ txgbe_get_bp_ability(&lp_ability, 1, hw);
+
+ /* 3.2. Check the AN73 Link Ability with Link Partner */
+ BP_LOG("<3.2>. Check the AN73 Link Ability with Link Partner ...\n");
+ BP_LOG(" Local Link Ability: 0x%x\n", local_ability.link_ability);
+ BP_LOG(" Link Partner Link Ability: 0x%x\n", lp_ability.link_ability);
+
+ status = txgbe_check_bp_ability(&local_ability, &lp_ability, hw);
+
+ wr32_epcs(hw, SR_AN_CTRL, 0);
+ wr32_epcs(hw, VR_AN_KR_MODE_CL, 0);
+
+ /* 3.3. Check the FEC and KR Training for KR mode */
+ BP_LOG("<3.3>. Check the FEC for KR mode ...\n");
+ if ((local_ability.fec_ability & lp_ability.fec_ability) == 0x03) {
+ BP_LOG("Enable the Backplane KR FEC ...\n");
+ wr32_epcs(hw, SR_PMA_KR_FEC_CTRL, SR_PMA_KR_FEC_CTRL_EN);
+ } else {
+ BP_LOG("Backplane KR FEC is disabled.\n");
+ }
+
+ printf("Enter training.\n");
+ /* CL72 KR training on */
+ for (i = 0; i < 2; i++) {
+ /* 3.4. Check the CL72 KR Training for KR mode */
+ BP_LOG("<3.4>. Check the CL72 KR Training for KR mode ...\n");
+ BP_LOG("==================%d==================\n", i);
+ status = txgbe_enable_kr_training(hw);
+ BP_LOG("Check the Clause 72 KR Training status ...\n");
+ status |= txgbe_check_kr_training(hw);
+
+ lp_reg = rd32_epcs(hw, SR_PMA_KR_LP_CESTS);
+ lp_reg &= SR_PMA_KR_LP_CESTS_RR;
+ BP_LOG("SR PMA MMD 10GBASE-KR LP Coefficient Status Register: 0x%x\n",
+ lp_reg);
+ ld_reg = rd32_epcs(hw, SR_PMA_KR_LD_CESTS);
+ ld_reg &= SR_PMA_KR_LD_CESTS_RR;
+ BP_LOG("SR PMA MMD 10GBASE-KR LD Coefficient Status Register: 0x%x\n",
+ ld_reg);
+ if (hw->devarg.poll == 0 && status != 0)
+ lp_reg = SR_PMA_KR_LP_CESTS_RR;
+
+ if (lp_reg & ld_reg) {
+ BP_LOG("==================out==================\n");
+ status = txgbe_disable_kr_training(hw, 0, 0);
+ wr32_epcs(hw, SR_AN_CTRL, 0);
+ txgbe_clear_bp_intr(2, 0, hw);
+ txgbe_clear_bp_intr(1, 0, hw);
+ txgbe_clear_bp_intr(0, 0, hw);
+ for (i = 0; i < 10; i++) {
+ value = rd32_epcs(hw, SR_XS_PCS_KR_STS1);
+ if (value & SR_XS_PCS_KR_STS1_PLU) {
+ BP_LOG("\nINT_AN_INT_CMPLT =1, AN73 Done Success.\n");
+ wr32_epcs(hw, SR_AN_CTRL, 0);
+ return 0;
+ }
+ msec_delay(10);
+ }
+ msec_delay(1000);
+ txgbe_set_link_to_kr(hw, 0);
+
+ return 0;
+ }
+
+ status |= txgbe_disable_kr_training(hw, 0, 0);
+ }
+
+ txgbe_clear_bp_intr(2, 0, hw);
+ txgbe_clear_bp_intr(1, 0, hw);
+ txgbe_clear_bp_intr(0, 0, hw);
+
+ return status;
+}
+
+/**
+ * txgbe_get_bp_ability
+ * @hw: pointer to hardware structure
+ * @ability: pointer to blackplane ability structure
+ * @link_partner:
+ * 1: Get Link Partner Base Page
+ * 2: Get Link Partner Next Page
+ * (only get NXP Ability Register 1 at the moment)
+ * 0: Get Local Device Base Page
+ */
+static void txgbe_get_bp_ability(struct txgbe_backplane_ability *ability,
+ u32 link_partner, struct txgbe_hw *hw)
+{
+ u32 value = 0;
+
+ DEBUGFUNC("txgbe_get_bp_ability");
+
+ /* Link Partner Base Page */
+ if (link_partner == 1) {
+ /* Read the link partner AN73 Base Page Ability Registers */
+ BP_LOG("Read the link partner AN73 Base Page Ability Registers...\n");
+ value = rd32_epcs(hw, SR_AN_MMD_LP_ABL1);
+ BP_LOG("SR AN MMD LP Base Page Ability Register 1: 0x%x\n",
+ value);
+ ability->next_page = SR_MMD_LP_ABL1_ADV_NP(value);
+ BP_LOG(" Next Page (bit15): %d\n", ability->next_page);
+
+ value = rd32_epcs(hw, SR_AN_MMD_LP_ABL2);
+ BP_LOG("SR AN MMD LP Base Page Ability Register 2: 0x%x\n",
+ value);
+ ability->link_ability =
+ value & SR_AN_MMD_LP_ABL2_BP_TYPE_KR_KX4_KX;
+ BP_LOG(" Link Ability (bit[15:0]): 0x%x\n",
+ ability->link_ability);
+ BP_LOG(" (0x20- KX_ONLY, 0x40- KX4_ONLY, 0x60- KX4_KX\n");
+ BP_LOG(" 0x80- KR_ONLY, 0xA0- KR_KX, 0xC0- KR_KX4, 0xE0- KR_KX4_KX)\n");
+
+ value = rd32_epcs(hw, SR_AN_MMD_LP_ABL3);
+ BP_LOG("SR AN MMD LP Base Page Ability Register 3: 0x%x\n",
+ value);
+ BP_LOG(" FEC Request (bit15): %d\n", ((value >> 15) & 0x01));
+ BP_LOG(" FEC Enable (bit14): %d\n", ((value >> 14) & 0x01));
+ ability->fec_ability = SR_AN_MMD_LP_ABL3_FCE(value);
+ } else if (link_partner == 2) {
+ /* Read the link partner AN73 Next Page Ability Registers */
+ BP_LOG("\nRead the link partner AN73 Next Page Ability Registers...\n");
+ value = rd32_epcs(hw, SR_AN_LP_XNP_ABL1);
+ BP_LOG(" SR AN MMD LP XNP Ability Register 1: 0x%x\n", value);
+ ability->next_page = SR_AN_LP_XNP_ABL1_NP(value);
+ BP_LOG(" Next Page (bit15): %d\n", ability->next_page);
+ } else {
+ /* Read the local AN73 Base Page Ability Registers */
+ BP_LOG("Read the local AN73 Base Page Ability Registers...\n");
+ value = rd32_epcs(hw, SR_AN_MMD_ADV_REG1);
+ BP_LOG("SR AN MMD Advertisement Register 1: 0x%x\n", value);
+ ability->next_page = SR_AN_MMD_ADV_REG1_NP(value);
+ BP_LOG(" Next Page (bit15): %d\n", ability->next_page);
+
+ value = rd32_epcs(hw, SR_AN_MMD_ADV_REG2);
+ BP_LOG("SR AN MMD Advertisement Register 2: 0x%x\n", value);
+ ability->link_ability =
+ value & SR_AN_MMD_ADV_REG2_BP_TYPE_KR_KX4_KX;
+ BP_LOG(" Link Ability (bit[15:0]): 0x%x\n",
+ ability->link_ability);
+ BP_LOG(" (0x20- KX_ONLY, 0x40- KX4_ONLY, 0x60- KX4_KX\n");
+ BP_LOG(" 0x80- KR_ONLY, 0xA0- KR_KX, 0xC0- KR_KX4, 0xE0- KR_KX4_KX)\n");
+
+ value = rd32_epcs(hw, SR_AN_MMD_ADV_REG3);
+ BP_LOG("SR AN MMD Advertisement Register 3: 0x%x\n", value);
+ BP_LOG(" FEC Request (bit15): %d\n", ((value >> 15) & 0x01));
+ BP_LOG(" FEC Enable (bit14): %d\n", ((value >> 14) & 0x01));
+ ability->fec_ability = SR_AN_MMD_ADV_REG3_FCE(value);
+ }
+
+ BP_LOG("done.\n");
+}
+
+/**
+ * txgbe_check_bp_ability
+ * @hw: pointer to hardware structure
+ * @ability: pointer to blackplane ability structure
+ */
+static s32 txgbe_check_bp_ability(struct txgbe_backplane_ability *local_ability,
+ struct txgbe_backplane_ability *lp_ability, struct txgbe_hw *hw)
+{
+ u32 com_link_abi;
+ s32 ret = 0;
+
+ DEBUGFUNC("txgbe_check_bp_ability");
+
+ com_link_abi = local_ability->link_ability & lp_ability->link_ability;
+ BP_LOG("com_link_abi = 0x%x, local_ability = 0x%x, lp_ability = 0x%x\n",
+ com_link_abi, local_ability->link_ability,
+ lp_ability->link_ability);
+
+ if (!com_link_abi) {
+ BP_LOG("The Link Partner does not support any compatible speed mode.\n");
+ ret = -1;
+ } else if (com_link_abi & BP_TYPE_KR) {
+ if (local_ability->current_link_mode) {
+ BP_LOG("Link mode is not matched with Link Partner: [LINK_KR].\n");
+ BP_LOG("Set the local link mode to [LINK_KR] ...\n");
+ txgbe_set_link_to_kr(hw, 0);
+ ret = 1;
+ } else {
+ BP_LOG("Link mode is matched with Link Partner: [LINK_KR].\n");
+ ret = 0;
+ }
+ } else if (com_link_abi & BP_TYPE_KX4) {
+ if (local_ability->current_link_mode == 0x10) {
+ BP_LOG("Link mode is matched with Link Partner: [LINK_KX4].\n");
+ ret = 0;
+ } else {
+ BP_LOG("Link mode is not matched with Link Partner: [LINK_KX4].\n");
+ BP_LOG("Set the local link mode to [LINK_KX4] ...\n");
+ txgbe_set_link_to_kx4(hw, 1);
+ ret = 1;
+ }
+ } else if (com_link_abi & BP_TYPE_KX) {
+ if (local_ability->current_link_mode == 0x1) {
+ BP_LOG("Link mode is matched with Link Partner: [LINK_KX].\n");
+ ret = 0;
+ } else {
+ BP_LOG("Link mode is not matched with Link Partner: [LINK_KX].\n");
+ BP_LOG("Set the local link mode to [LINK_KX] ...\n");
+ txgbe_set_link_to_kx(hw, 1, 1);
+ ret = 1;
+ }
+ }
+
+ return ret;
+}
+
+/**
+ * txgbe_clear_bp_intr
+ * @hw: pointer to hardware structure
+ * @index: the bit will be cleared
+ * @index_high:
+ * index_high = 0: Only the index bit will be cleared
+ * index_high != 0: the [index_high, index] range will be cleared
+ */
+static void txgbe_clear_bp_intr(u32 bit, u32 bit_high, struct txgbe_hw *hw)
+{
+ u32 rdata = 0, wdata, i;
+
+ DEBUGFUNC("txgbe_clear_bp_intr");
+
+ rdata = rd32_epcs(hw, VR_AN_INTR);
+ BP_LOG("[Before clear]Read VR AN MMD Interrupt Register: 0x%x\n",
+ rdata);
+ BP_LOG("Interrupt: 0- AN_INT_CMPLT, 1- AN_INC_LINK, 2- AN_PG_RCV\n\n");
+
+ wdata = rdata;
+ if (bit_high) {
+ for (i = bit; i <= bit_high; i++)
+ wdata &= ~(1 << i);
+ } else {
+ wdata &= ~(1 << bit);
+ }
+
+ wr32_epcs(hw, VR_AN_INTR, wdata);
+
+ rdata = rd32_epcs(hw, VR_AN_INTR);
+ BP_LOG("[After clear]Read VR AN MMD Interrupt Register: 0x%x\n", rdata);
+}
+
+static s32 txgbe_enable_kr_training(struct txgbe_hw *hw)
+{
+ s32 status = 0;
+ u32 value = 0;
+
+ DEBUGFUNC("txgbe_enable_kr_training");
+
+ BP_LOG("Enable Clause 72 KR Training ...\n");
+
+ if (CL72_KRTR_PRBS_MODE_EN != 0xFFFF) {
+ /* Set PRBS Timer Duration Control to maximum 6.7ms in
+ * VR_PMA_KRTR_PRBS_CTRL2 Register
+ */
+ value = CL72_KRTR_PRBS_MODE_EN;
+ wr32_epcs(hw, VR_PMA_KRTR_PRBS_CTRL2, value);
+ /* Set PRBS Timer Duration Control to maximum 6.7ms in
+ * VR_PMA_KRTR_PRBS_CTRL1 Register
+ */
+ wr32_epcs(hw, VR_PMA_KRTR_PRBS_CTRL1,
+ VR_PMA_KRTR_PRBS_TIME_LMT);
+ /* Enable PRBS Mode to determine KR Training Status by setting
+ * Bit 0 of VR_PMA_KRTR_PRBS_CTRL0 Register
+ */
+ value = VR_PMA_KRTR_PRBS_MODE_EN;
+ }
+#ifdef CL72_KRTR_PRBS31_EN
+ /* Enable PRBS Mode to determine KR Training Status by setting
+ * Bit 1 of VR_PMA_KRTR_PRBS_CTRL0 Register
+ */
+ value = VR_PMA_KRTR_PRBS31_EN;
+#endif
+ wr32_epcs(hw, VR_PMA_KRTR_PRBS_CTRL0, value);
+ /* Read PHY Lane0 TX EQ before Clause 72 KR Training. */
+ txgbe_read_phy_lane_tx_eq(0, hw, 0, 0);
+
+ /* Enable the Clause 72 start-up protocol
+ * by setting Bit 1 of SR_PMA_KR_PMD_CTRL Register.
+ * Restart the Clause 72 start-up protocol
+ * by setting Bit 0 of SR_PMA_KR_PMD_CTRL Register.
+ */
+ wr32_epcs(hw, SR_PMA_KR_PMD_CTRL,
+ SR_PMA_KR_PMD_CTRL_EN_TR | SR_PMA_KR_PMD_CTRL_RS_TR);
+
+ return status;
+}
+
+static s32 txgbe_disable_kr_training(struct txgbe_hw *hw, s32 post, s32 mode)
+{
+ s32 status = 0;
+
+ DEBUGFUNC("txgbe_disable_kr_training");
+
+ BP_LOG("Disable Clause 72 KR Training ...\n");
+ /* Read PHY Lane0 TX EQ before Clause 72 KR Training. */
+ txgbe_read_phy_lane_tx_eq(0, hw, post, mode);
+
+ wr32_epcs(hw, SR_PMA_KR_PMD_CTRL, SR_PMA_KR_PMD_CTRL_RS_TR);
+
+ return status;
+}
+
+static s32 txgbe_check_kr_training(struct txgbe_hw *hw)
+{
+ s32 status = 0;
+ u32 value, test;
+ int i;
+ int times = hw->devarg.poll ? 35 : 20;
+
+ DEBUGFUNC("txgbe_check_kr_training");
+
+ for (i = 0; i < times; i++) {
+ value = rd32_epcs(hw, SR_PMA_KR_LP_CEU);
+ BP_LOG("SR PMA MMD 10GBASE-KR LP Coefficient Update Register: 0x%x\n",
+ value);
+ value = rd32_epcs(hw, SR_PMA_KR_LP_CESTS);
+ BP_LOG("SR PMA MMD 10GBASE-KR LP Coefficient Status Register: 0x%x\n",
+ value);
+ value = rd32_epcs(hw, SR_PMA_KR_LD_CEU);
+ BP_LOG("SR PMA MMD 10GBASE-KR LD Coefficient Update: 0x%x\n",
+ value);
+ value = rd32_epcs(hw, SR_PMA_KR_LD_CESTS);
+ BP_LOG("SR PMA MMD 10GBASE-KR LD Coefficient Status: 0x%x\n",
+ value);
+ value = rd32_epcs(hw, SR_PMA_KR_PMD_STS);
+ BP_LOG("SR PMA MMD 10GBASE-KR Status Register: 0x%x\n", value);
+ BP_LOG(" Training Failure (bit3): %d\n",
+ ((value >> 3) & 0x01));
+ BP_LOG(" Start-Up Protocol Status (bit2): %d\n",
+ ((value >> 2) & 0x01));
+ BP_LOG(" Frame Lock (bit1): %d\n",
+ ((value >> 1) & 0x01));
+ BP_LOG(" Receiver Status (bit0): %d\n",
+ ((value >> 0) & 0x01));
+
+ test = rd32_epcs(hw, SR_PMA_KR_LP_CESTS);
+ if (test & SR_PMA_KR_LP_CESTS_RR) {
+ BP_LOG("TEST Coefficient Status Register: 0x%x\n",
+ test);
+ status = 1;
+ }
+
+ if (value & SR_PMA_KR_PMD_STS_TR_FAIL) {
+ BP_LOG("Training is completed with failure.\n");
+ txgbe_read_phy_lane_tx_eq(0, hw, 0, 0);
+ return 0;
+ }
+
+ if (value & SR_PMA_KR_PMD_STS_RCV) {
+ BP_LOG("Receiver trained and ready to receive data.\n");
+ txgbe_read_phy_lane_tx_eq(0, hw, 0, 0);
+ return 0;
+ }
+
+ msec_delay(20);
+ }
+
+ BP_LOG("ERROR: Check Clause 72 KR Training Complete Timeout.\n");
+ return status;
+}
+
+static void txgbe_read_phy_lane_tx_eq(u16 lane, struct txgbe_hw *hw,
+ s32 post, s32 mode)
+{
+ u32 value = 0;
+ u32 addr;
+ u32 tx_main_cursor, tx_pre_cursor, tx_post_cursor, lmain;
+
+ DEBUGFUNC("txgbe_read_phy_lane_tx_eq");
+
+ addr = TXGBE_PHY_LANE0_TX_EQ_CTL1 | (lane << 8);
+ value = rd32_ephy(hw, addr);
+ BP_LOG("PHY LANE TX EQ Read Value: %x\n", lane);
+ tx_main_cursor = TXGBE_PHY_LANE0_TX_EQ_CTL1_MAIN(value);
+ BP_LOG("TX_MAIN_CURSOR: %x\n", tx_main_cursor);
+ UNREFERENCED_PARAMETER(tx_main_cursor);
+
+ addr = TXGBE_PHY_LANE0_TX_EQ_CTL2 | (lane << 8);
+ value = rd32_ephy(hw, addr);
+ tx_pre_cursor = value & TXGBE_PHY_LANE0_TX_EQ_CTL2_PRE;
+ tx_post_cursor = TXGBE_PHY_LANE0_TX_EQ_CTL2_POST(value);
+ BP_LOG("TX_PRE_CURSOR: %x\n", tx_pre_cursor);
+ BP_LOG("TX_POST_CURSOR: %x\n", tx_post_cursor);
+
+ if (mode == 1) {
+ lmain = 160 - tx_pre_cursor - tx_post_cursor;
+ if (lmain < 88)
+ lmain = 88;
+
+ if (post)
+ tx_post_cursor = post;
+
+ wr32_epcs(hw, TXGBE_PHY_EQ_INIT_CTL1, tx_post_cursor);
+ wr32_epcs(hw, TXGBE_PHY_EQ_INIT_CTL0,
+ tx_pre_cursor | (lmain << 8));
+ value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1);
+ value &= ~TXGBE_PHY_TX_EQ_CTL1_DEF;
+ wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
+ }
+}
diff --git a/drivers/net/txgbe/base/txgbe_phy.h b/drivers/net/txgbe/base/txgbe_phy.h
index b804d2406..ad4a915f8 100644
--- a/drivers/net/txgbe/base/txgbe_phy.h
+++ b/drivers/net/txgbe/base/txgbe_phy.h
@@ -396,6 +396,10 @@
#define TXGBE_MD_PORT_CTRL 0xF001
#define TXGBE_MD_PORT_CTRL_RESET MS16(14, 0x1)
+#ifndef CL72_KRTR_PRBS_MODE_EN
+#define CL72_KRTR_PRBS_MODE_EN 0xFFFF /* open kr prbs check */
+#endif
+
/******************************************************************************
* SFP I2C Registers:
******************************************************************************/
@@ -450,5 +454,6 @@ s32 txgbe_write_i2c_eeprom(struct txgbe_hw *hw, u8 byte_offset,
u8 eeprom_data);
u64 txgbe_autoc_read(struct txgbe_hw *hw);
void txgbe_autoc_write(struct txgbe_hw *hw, u64 value);
+s32 txgbe_kr_handle(struct txgbe_hw *hw);
#endif /* _TXGBE_PHY_H_ */
diff --git a/drivers/net/txgbe/base/txgbe_type.h b/drivers/net/txgbe/base/txgbe_type.h
index 33572cc3c..0ce469212 100644
--- a/drivers/net/txgbe/base/txgbe_type.h
+++ b/drivers/net/txgbe/base/txgbe_type.h
@@ -600,6 +600,8 @@ struct txgbe_mac_info {
s32 (*dmac_config)(struct txgbe_hw *hw);
s32 (*setup_eee)(struct txgbe_hw *hw, bool enable_eee);
+ s32 (*kr_handle)(struct txgbe_hw *hw);
+
enum txgbe_mac_type type;
u8 addr[ETH_ADDR_LEN];
u8 perm_addr[ETH_ADDR_LEN];
@@ -795,6 +797,13 @@ struct txgbe_hw {
} qp_last[TXGBE_MAX_QP];
};
+struct txgbe_backplane_ability {
+ u32 next_page; /* Next Page (bit0) */
+ u32 link_ability; /* Link Ability (bit[7:0]) */
+ u32 fec_ability; /* FEC Request (bit1), FEC Enable (bit0) */
+ u32 current_link_mode; /* current link mode for local device */
+};
+
#include "txgbe_regs.h"
#include "txgbe_dummy.h"
--
2.27.0
^ permalink raw reply related [flat|nested] 10+ messages in thread* [dpdk-dev] [PATCH v4 5/6] net/txgbe: handle AN interrupt and link update
2021-03-29 3:17 [dpdk-dev] [PATCH v4 0/6] txgbe backplane AN training Jiawen Wu
` (3 preceding siblings ...)
2021-03-29 3:17 ` [dpdk-dev] [PATCH v4 4/6] net/txgbe/base: support to handle backplane AN73 flow Jiawen Wu
@ 2021-03-29 3:17 ` Jiawen Wu
2021-03-29 3:17 ` [dpdk-dev] [PATCH v4 6/6] net/txgbe: add FFE parameters for user debugging Jiawen Wu
2021-03-29 15:51 ` [dpdk-dev] [PATCH v4 0/6] txgbe backplane AN training Ferruh Yigit
6 siblings, 0 replies; 10+ messages in thread
From: Jiawen Wu @ 2021-03-29 3:17 UTC (permalink / raw)
To: dev; +Cc: Jiawen Wu
Read AN interrupt from misc, and do the AN configuration action.
When link status is down, PHY power should be restarted to config KR
mode again.
Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
---
drivers/net/txgbe/base/txgbe_hw.c | 4 +-
drivers/net/txgbe/base/txgbe_phy.c | 14 +++++++
drivers/net/txgbe/base/txgbe_phy.h | 1 +
drivers/net/txgbe/base/txgbe_type.h | 1 +
drivers/net/txgbe/txgbe_ethdev.c | 58 +++++++++++++++++++++++++----
drivers/net/txgbe/txgbe_ethdev.h | 7 ++--
6 files changed, 73 insertions(+), 12 deletions(-)
diff --git a/drivers/net/txgbe/base/txgbe_hw.c b/drivers/net/txgbe/base/txgbe_hw.c
index 9a82a329a..917bd947f 100644
--- a/drivers/net/txgbe/base/txgbe_hw.c
+++ b/drivers/net/txgbe/base/txgbe_hw.c
@@ -2574,8 +2574,10 @@ s32 txgbe_init_phy_raptor(struct txgbe_hw *hw)
txgbe_get_copper_link_capabilities;
}
- if (phy->media_type == txgbe_media_type_backplane)
+ if (phy->media_type == txgbe_media_type_backplane) {
mac->kr_handle = txgbe_kr_handle;
+ mac->bp_down_event = txgbe_bp_down_event;
+ }
/* Set necessary function pointers based on PHY type */
switch (hw->phy.type) {
diff --git a/drivers/net/txgbe/base/txgbe_phy.c b/drivers/net/txgbe/base/txgbe_phy.c
index 140857121..5402a064f 100644
--- a/drivers/net/txgbe/base/txgbe_phy.c
+++ b/drivers/net/txgbe/base/txgbe_phy.c
@@ -2304,6 +2304,20 @@ void txgbe_autoc_write(struct txgbe_hw *hw, u64 autoc)
mactxcfg | TXGBE_MACTXCFG_TXE);
}
+void txgbe_bp_down_event(struct txgbe_hw *hw)
+{
+ if (!(hw->devarg.auto_neg == 1))
+ return;
+
+ BP_LOG("restart phy power.\n");
+ wr32_epcs(hw, VR_AN_KR_MODE_CL, 0);
+ wr32_epcs(hw, SR_AN_CTRL, 0);
+ wr32_epcs(hw, VR_AN_INTR_MSK, 0);
+
+ msleep(1050);
+ txgbe_set_link_to_kr(hw, 0);
+}
+
/**
* txgbe_kr_handle - Handle the interrupt of auto-negotiation
* @hw: pointer to hardware structure
diff --git a/drivers/net/txgbe/base/txgbe_phy.h b/drivers/net/txgbe/base/txgbe_phy.h
index ad4a915f8..d2f2b2f8e 100644
--- a/drivers/net/txgbe/base/txgbe_phy.h
+++ b/drivers/net/txgbe/base/txgbe_phy.h
@@ -454,6 +454,7 @@ s32 txgbe_write_i2c_eeprom(struct txgbe_hw *hw, u8 byte_offset,
u8 eeprom_data);
u64 txgbe_autoc_read(struct txgbe_hw *hw);
void txgbe_autoc_write(struct txgbe_hw *hw, u64 value);
+void txgbe_bp_down_event(struct txgbe_hw *hw);
s32 txgbe_kr_handle(struct txgbe_hw *hw);
#endif /* _TXGBE_PHY_H_ */
diff --git a/drivers/net/txgbe/base/txgbe_type.h b/drivers/net/txgbe/base/txgbe_type.h
index 0ce469212..363e70733 100644
--- a/drivers/net/txgbe/base/txgbe_type.h
+++ b/drivers/net/txgbe/base/txgbe_type.h
@@ -601,6 +601,7 @@ struct txgbe_mac_info {
s32 (*setup_eee)(struct txgbe_hw *hw, bool enable_eee);
s32 (*kr_handle)(struct txgbe_hw *hw);
+ void (*bp_down_event)(struct txgbe_hw *hw);
enum txgbe_mac_type type;
u8 addr[ETH_ADDR_LEN];
diff --git a/drivers/net/txgbe/txgbe_ethdev.c b/drivers/net/txgbe/txgbe_ethdev.c
index 447a511ca..149cc1771 100644
--- a/drivers/net/txgbe/txgbe_ethdev.c
+++ b/drivers/net/txgbe/txgbe_ethdev.c
@@ -106,6 +106,7 @@ static void txgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev,
static void txgbe_dev_link_status_print(struct rte_eth_dev *dev);
static int txgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
static int txgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
+static int txgbe_dev_misc_interrupt_setup(struct rte_eth_dev *dev);
static int txgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
static int txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
static int txgbe_dev_interrupt_action(struct rte_eth_dev *dev,
@@ -1507,6 +1508,7 @@ txgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
gpie |= TXGBE_GPIOBIT_6;
wr32(hw, TXGBE_GPIOINTEN, gpie);
intr->mask_misc |= TXGBE_ICRMISC_GPIO;
+ intr->mask_misc |= TXGBE_ICRMISC_ANDONE;
}
int
@@ -1740,7 +1742,8 @@ txgbe_dev_start(struct rte_eth_dev *dev)
hw->mac.enable_tx_laser(hw);
}
- err = hw->mac.check_link(hw, &speed, &link_up, 0);
+ if ((hw->subsystem_device_id & 0xFF) != TXGBE_DEV_ID_KR_KX_KX4)
+ err = hw->mac.check_link(hw, &speed, &link_up, 0);
if (err)
goto error;
dev->data->dev_link.link_status = link_up;
@@ -1783,6 +1786,7 @@ txgbe_dev_start(struct rte_eth_dev *dev)
skip_link_setup:
if (rte_intr_allow_others(intr_handle)) {
+ txgbe_dev_misc_interrupt_setup(dev);
/* check if lsc interrupt is enabled */
if (dev->data->dev_conf.intr_conf.lsc != 0)
txgbe_dev_lsc_interrupt_setup(dev, TRUE);
@@ -2700,7 +2704,10 @@ txgbe_dev_link_update_share(struct rte_eth_dev *dev,
}
if (link_up == 0) {
- if (hw->phy.media_type == txgbe_media_type_fiber) {
+ if ((hw->subsystem_device_id & 0xFF) ==
+ TXGBE_DEV_ID_KR_KX_KX4) {
+ hw->mac.bp_down_event(hw);
+ } else if (hw->phy.media_type == txgbe_media_type_fiber) {
intr->flags |= TXGBE_FLAG_NEED_LINK_CONFIG;
rte_eal_alarm_set(10,
txgbe_dev_setup_link_alarm_handler, dev);
@@ -2835,6 +2842,20 @@ txgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
return 0;
}
+static int
+txgbe_dev_misc_interrupt_setup(struct rte_eth_dev *dev)
+{
+ struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
+ u64 mask;
+
+ mask = TXGBE_ICR_MASK;
+ mask &= (1ULL << TXGBE_MISC_VEC_ID);
+ intr->mask |= mask;
+ intr->mask_misc |= TXGBE_ICRMISC_GPIO;
+ intr->mask_misc |= TXGBE_ICRMISC_ANDONE;
+ return 0;
+}
+
/**
* It clears the interrupt causes and enables the interrupt.
* It will be called once only during nic initialized.
@@ -2850,9 +2871,11 @@ static int
txgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
{
struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
+ u64 mask;
- intr->mask[0] |= TXGBE_ICR_MASK;
- intr->mask[1] |= TXGBE_ICR_MASK;
+ mask = TXGBE_ICR_MASK;
+ mask &= ~((1ULL << TXGBE_RX_VEC_START) - 1);
+ intr->mask |= mask;
return 0;
}
@@ -2908,6 +2931,9 @@ txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
if (eicr & TXGBE_ICRMISC_LSC)
intr->flags |= TXGBE_FLAG_NEED_LINK_UPDATE;
+ if (eicr & TXGBE_ICRMISC_ANDONE)
+ intr->flags |= TXGBE_FLAG_NEED_AN_CONFIG;
+
if (eicr & TXGBE_ICRMISC_VFMBX)
intr->flags |= TXGBE_FLAG_MAILBOX;
@@ -2985,6 +3011,13 @@ txgbe_dev_interrupt_action(struct rte_eth_dev *dev,
intr->flags &= ~TXGBE_FLAG_PHY_INTERRUPT;
}
+ if (intr->flags & TXGBE_FLAG_NEED_AN_CONFIG) {
+ if (hw->devarg.auto_neg == 1 && hw->devarg.poll == 0) {
+ hw->mac.kr_handle(hw);
+ intr->flags &= ~TXGBE_FLAG_NEED_AN_CONFIG;
+ }
+ }
+
if (intr->flags & TXGBE_FLAG_NEED_LINK_UPDATE) {
struct rte_eth_link link;
@@ -2998,6 +3031,11 @@ txgbe_dev_interrupt_action(struct rte_eth_dev *dev,
/* handle it 1 sec later, wait it being stable */
timeout = TXGBE_LINK_UP_CHECK_TIMEOUT;
/* likely to down */
+ else if ((hw->subsystem_device_id & 0xFF) ==
+ TXGBE_DEV_ID_KR_KX_KX4 &&
+ hw->devarg.auto_neg == 1)
+ /* handle it 2 sec later for backplane AN73 */
+ timeout = 2000;
else
/* handle it 4 sec later, wait it being stable */
timeout = TXGBE_LINK_DOWN_CHECK_TIMEOUT;
@@ -3008,10 +3046,12 @@ txgbe_dev_interrupt_action(struct rte_eth_dev *dev,
(void *)dev) < 0) {
PMD_DRV_LOG(ERR, "Error setting alarm");
} else {
- /* remember original mask */
- intr->mask_misc_orig = intr->mask_misc;
/* only disable lsc interrupt */
intr->mask_misc &= ~TXGBE_ICRMISC_LSC;
+
+ intr->mask_orig = intr->mask;
+ /* only disable all misc interrupts */
+ intr->mask &= ~(1ULL << TXGBE_MISC_VEC_ID);
}
}
@@ -3072,8 +3112,10 @@ txgbe_dev_interrupt_delayed_handler(void *param)
}
/* restore original mask */
- intr->mask_misc = intr->mask_misc_orig;
- intr->mask_misc_orig = 0;
+ intr->mask_misc |= TXGBE_ICRMISC_LSC;
+
+ intr->mask = intr->mask_orig;
+ intr->mask_orig = 0;
PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
txgbe_enable_intr(dev);
diff --git a/drivers/net/txgbe/txgbe_ethdev.h b/drivers/net/txgbe/txgbe_ethdev.h
index 5d4d9434a..8d46e6bb5 100644
--- a/drivers/net/txgbe/txgbe_ethdev.h
+++ b/drivers/net/txgbe/txgbe_ethdev.h
@@ -28,6 +28,7 @@
#define TXGBE_FLAG_PHY_INTERRUPT (uint32_t)(1 << 2)
#define TXGBE_FLAG_MACSEC (uint32_t)(1 << 3)
#define TXGBE_FLAG_NEED_LINK_CONFIG (uint32_t)(1 << 4)
+#define TXGBE_FLAG_NEED_AN_CONFIG (uint32_t)(1 << 5)
/*
* Defines that were not part of txgbe_type.h as they are not used by the
@@ -138,9 +139,9 @@ struct txgbe_rte_flow_rss_conf {
struct txgbe_interrupt {
uint32_t flags;
uint32_t mask_misc;
- /* to save original mask during delayed handler */
- uint32_t mask_misc_orig;
- uint32_t mask[2];
+ uint32_t mask_misc_orig; /* save mask during delayed handler */
+ uint64_t mask;
+ uint64_t mask_orig; /* save mask during delayed handler */
};
#define TXGBE_NB_STAT_MAPPING 32
--
2.27.0
^ permalink raw reply related [flat|nested] 10+ messages in thread* [dpdk-dev] [PATCH v4 6/6] net/txgbe: add FFE parameters for user debugging
2021-03-29 3:17 [dpdk-dev] [PATCH v4 0/6] txgbe backplane AN training Jiawen Wu
` (4 preceding siblings ...)
2021-03-29 3:17 ` [dpdk-dev] [PATCH v4 5/6] net/txgbe: handle AN interrupt and link update Jiawen Wu
@ 2021-03-29 3:17 ` Jiawen Wu
2021-03-29 15:50 ` Ferruh Yigit
2021-03-29 15:51 ` [dpdk-dev] [PATCH v4 0/6] txgbe backplane AN training Ferruh Yigit
6 siblings, 1 reply; 10+ messages in thread
From: Jiawen Wu @ 2021-03-29 3:17 UTC (permalink / raw)
To: dev; +Cc: Jiawen Wu
Support to set PHY link mode by user defined.
And update release notes 21.05 for txgbe.
Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
---
doc/guides/nics/txgbe.rst | 21 ++++++
doc/guides/rel_notes/release_21_05.rst | 1 +
drivers/net/txgbe/base/txgbe_hw.c | 11 +++
drivers/net/txgbe/base/txgbe_phy.c | 98 +++++++++++++++++++++++++-
drivers/net/txgbe/base/txgbe_phy.h | 10 +++
drivers/net/txgbe/base/txgbe_type.h | 15 ++++
drivers/net/txgbe/txgbe_ethdev.c | 22 +++++-
7 files changed, 174 insertions(+), 4 deletions(-)
diff --git a/doc/guides/nics/txgbe.rst b/doc/guides/nics/txgbe.rst
index 14243079d..39a157eb8 100644
--- a/doc/guides/nics/txgbe.rst
+++ b/doc/guides/nics/txgbe.rst
@@ -118,6 +118,27 @@ Please note that following ``devargs`` are only set for backplane NICs.
Special treatment for KX SGMII cards.
+- ``ffe_set`` (default **0**)
+
+ Use to set PHY link mode and enable FFE parameters for user debugging.
+ If disabled, the FFE parameters will not take effect. Otherwise, set 1
+ for SFI mode, set 2 for KR mode, set 3 for KX4 mode, set 4 for KX mode.
+
+- ``ffe_main`` (default **27**)
+
+ PHY parameter used for user debugging. Setting other values to
+ take effect requires setting the ``ffe_set``.
+
+- ``ffe_pre`` (default **8**)
+
+ PHY parameter used for user debugging. Setting other values to
+ take effect requires setting the ``ffe_set``.
+
+- ``ffe_post`` (default **44**)
+
+ PHY parameter used for user debugging. Setting other values to
+ take effect requires setting the ``ffe_set``.
+
Driver compilation and testing
------------------------------
diff --git a/doc/guides/rel_notes/release_21_05.rst b/doc/guides/rel_notes/release_21_05.rst
index c187f1fa2..56e8014a8 100644
--- a/doc/guides/rel_notes/release_21_05.rst
+++ b/doc/guides/rel_notes/release_21_05.rst
@@ -89,6 +89,7 @@ New Features
* **Updated Wangxun txgbe driver.**
* Added support for txgbevf PMD.
+ * Support device arguments to handle AN training for backplane NICs.
* **Updated the AF_XDP driver.**
diff --git a/drivers/net/txgbe/base/txgbe_hw.c b/drivers/net/txgbe/base/txgbe_hw.c
index 917bd947f..3e7f2f9a3 100644
--- a/drivers/net/txgbe/base/txgbe_hw.c
+++ b/drivers/net/txgbe/base/txgbe_hw.c
@@ -2951,6 +2951,9 @@ u32 txgbe_get_media_type_raptor(struct txgbe_hw *hw)
DEBUGFUNC("txgbe_get_media_type_raptor");
+ if (hw->phy.ffe_set)
+ txgbe_bp_mode_set(hw);
+
/* Detect if there is a copper PHY attached. */
switch (hw->phy.type) {
case txgbe_phy_cu_unknown:
@@ -3544,6 +3547,14 @@ s32 txgbe_reset_hw(struct txgbe_hw *hw)
hw->mac.orig_autoc = autoc;
}
+ if (hw->phy.ffe_set) {
+ /* Make sure phy power is up */
+ msec_delay(50);
+
+ /* A temporary solution to set phy */
+ txgbe_set_phy_temp(hw);
+ }
+
/* Store the permanent mac address */
hw->mac.get_mac_addr(hw, hw->mac.perm_addr);
diff --git a/drivers/net/txgbe/base/txgbe_phy.c b/drivers/net/txgbe/base/txgbe_phy.c
index 5402a064f..dabc346f5 100644
--- a/drivers/net/txgbe/base/txgbe_phy.c
+++ b/drivers/net/txgbe/base/txgbe_phy.c
@@ -1513,6 +1513,15 @@ txgbe_set_link_to_kr(struct txgbe_hw *hw, bool autoneg)
} else {
wr32_epcs(hw, VR_AN_KR_MODE_CL, 0x1);
}
+
+ if (hw->phy.ffe_set == TXGBE_BP_M_KR) {
+ value = (0x1804 & ~0x3F3F);
+ value |= hw->phy.ffe_main << 8 | hw->phy.ffe_pre;
+ wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
+
+ value = (0x50 & ~0x7F) | (1 << 6) | hw->phy.ffe_post;
+ wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
+ }
out:
return err;
}
@@ -1710,7 +1719,14 @@ txgbe_set_link_to_kx4(struct txgbe_hw *hw, bool autoneg)
goto out;
}
- if (hw->fw_version <= TXGBE_FW_N_TXEQ) {
+ if (hw->phy.ffe_set == TXGBE_BP_M_KX4) {
+ value = (0x1804 & ~0x3F3F);
+ value |= hw->phy.ffe_main << 8 | hw->phy.ffe_pre;
+ wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
+
+ value = (0x50 & ~0x7F) | (1 << 6) | hw->phy.ffe_post;
+ wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
+ } else if (hw->fw_version <= TXGBE_FW_N_TXEQ) {
value = (0x1804 & ~0x3F3F);
wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
@@ -1917,7 +1933,15 @@ txgbe_set_link_to_kx(struct txgbe_hw *hw,
goto out;
}
- if (hw->fw_version <= TXGBE_FW_N_TXEQ) {
+ if (hw->phy.ffe_set == TXGBE_BP_M_KX) {
+ value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0) & ~0x3F3F;
+ value |= hw->phy.ffe_main << 8 | hw->phy.ffe_pre;
+ wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
+
+ value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0) & ~0x7F;
+ value |= hw->phy.ffe_post | (1 << 6);
+ wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
+ } else if (hw->fw_version <= TXGBE_FW_N_TXEQ) {
value = (0x1804 & ~0x3F3F) | (24 << 8) | 4;
wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
@@ -2144,7 +2168,15 @@ txgbe_set_link_to_sfi(struct txgbe_hw *hw,
goto out;
}
- if (hw->fw_version <= TXGBE_FW_N_TXEQ) {
+ if (hw->phy.ffe_set == TXGBE_BP_M_SFI) {
+ value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0) & ~0x3F3F;
+ value |= hw->phy.ffe_main << 8 | hw->phy.ffe_pre;
+ wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
+
+ value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0) & ~0x7F;
+ value |= hw->phy.ffe_post | (1 << 6);
+ wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
+ } else if (hw->fw_version <= TXGBE_FW_N_TXEQ) {
value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0);
value = (value & ~0x3F3F) | (24 << 8) | 4;
wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
@@ -2318,6 +2350,66 @@ void txgbe_bp_down_event(struct txgbe_hw *hw)
txgbe_set_link_to_kr(hw, 0);
}
+void txgbe_bp_mode_set(struct txgbe_hw *hw)
+{
+ if (hw->phy.ffe_set == TXGBE_BP_M_SFI)
+ hw->subsystem_device_id = TXGBE_DEV_ID_WX1820_SFP;
+ else if (hw->phy.ffe_set == TXGBE_BP_M_KR)
+ hw->subsystem_device_id = TXGBE_DEV_ID_WX1820_KR_KX_KX4;
+ else if (hw->phy.ffe_set == TXGBE_BP_M_KX4)
+ hw->subsystem_device_id = TXGBE_DEV_ID_WX1820_MAC_XAUI;
+ else if (hw->phy.ffe_set == TXGBE_BP_M_KX)
+ hw->subsystem_device_id = TXGBE_DEV_ID_WX1820_MAC_SGMII;
+}
+
+void txgbe_set_phy_temp(struct txgbe_hw *hw)
+{
+ u32 value;
+
+ if (hw->phy.ffe_set == TXGBE_BP_M_SFI) {
+ BP_LOG("Set SFI TX_EQ MAIN:%d PRE:%d POST:%d\n",
+ hw->phy.ffe_main, hw->phy.ffe_pre, hw->phy.ffe_post);
+
+ value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0);
+ value = (value & ~0x3F3F) | (hw->phy.ffe_main << 8) |
+ hw->phy.ffe_pre;
+ wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
+
+ value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1);
+ value = (value & ~0x7F) | hw->phy.ffe_post | (1 << 6);
+ wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
+ }
+
+ if (hw->phy.ffe_set == TXGBE_BP_M_KR) {
+ BP_LOG("Set KR TX_EQ MAIN:%d PRE:%d POST:%d\n",
+ hw->phy.ffe_main, hw->phy.ffe_pre, hw->phy.ffe_post);
+ value = (0x1804 & ~0x3F3F);
+ value |= hw->phy.ffe_main << 8 | hw->phy.ffe_pre;
+ wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
+
+ value = (0x50 & ~0x7F) | (1 << 6) | hw->phy.ffe_post;
+ wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
+ wr32_epcs(hw, 0x18035, 0x00FF);
+ wr32_epcs(hw, 0x18055, 0x00FF);
+ }
+
+ if (hw->phy.ffe_set == TXGBE_BP_M_KX) {
+ BP_LOG("Set KX TX_EQ MAIN:%d PRE:%d POST:%d\n",
+ hw->phy.ffe_main, hw->phy.ffe_pre, hw->phy.ffe_post);
+ value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0);
+ value = (value & ~0x3F3F) | (hw->phy.ffe_main << 8) |
+ hw->phy.ffe_pre;
+ wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
+
+ value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1);
+ value = (value & ~0x7F) | hw->phy.ffe_post | (1 << 6);
+ wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
+
+ wr32_epcs(hw, 0x18035, 0x00FF);
+ wr32_epcs(hw, 0x18055, 0x00FF);
+ }
+}
+
/**
* txgbe_kr_handle - Handle the interrupt of auto-negotiation
* @hw: pointer to hardware structure
diff --git a/drivers/net/txgbe/base/txgbe_phy.h b/drivers/net/txgbe/base/txgbe_phy.h
index d2f2b2f8e..56531c4f8 100644
--- a/drivers/net/txgbe/base/txgbe_phy.h
+++ b/drivers/net/txgbe/base/txgbe_phy.h
@@ -396,6 +396,14 @@
#define TXGBE_MD_PORT_CTRL 0xF001
#define TXGBE_MD_PORT_CTRL_RESET MS16(14, 0x1)
+#define TXGBE_BP_M_NULL 0
+#define TXGBE_BP_M_SFI 1
+#define TXGBE_BP_M_KR 2
+#define TXGBE_BP_M_KX4 3
+#define TXGBE_BP_M_KX 4
+#define TXGBE_BP_M_NAUTO 0
+#define TXGBE_BP_M_AUTO 1
+
#ifndef CL72_KRTR_PRBS_MODE_EN
#define CL72_KRTR_PRBS_MODE_EN 0xFFFF /* open kr prbs check */
#endif
@@ -454,6 +462,8 @@ s32 txgbe_write_i2c_eeprom(struct txgbe_hw *hw, u8 byte_offset,
u8 eeprom_data);
u64 txgbe_autoc_read(struct txgbe_hw *hw);
void txgbe_autoc_write(struct txgbe_hw *hw, u64 value);
+void txgbe_bp_mode_set(struct txgbe_hw *hw);
+void txgbe_set_phy_temp(struct txgbe_hw *hw);
void txgbe_bp_down_event(struct txgbe_hw *hw);
s32 txgbe_kr_handle(struct txgbe_hw *hw);
diff --git a/drivers/net/txgbe/base/txgbe_type.h b/drivers/net/txgbe/base/txgbe_type.h
index 363e70733..b69e7b85b 100644
--- a/drivers/net/txgbe/base/txgbe_type.h
+++ b/drivers/net/txgbe/base/txgbe_type.h
@@ -687,18 +687,33 @@ struct txgbe_phy_info {
bool qsfp_shared_i2c_bus;
u32 nw_mng_if_sel;
u32 link_mode;
+
+ /* Some features need tri-state capability */
+ u16 ffe_set;
+ u16 ffe_main;
+ u16 ffe_pre;
+ u16 ffe_post;
};
#define TXGBE_DEVARG_BP_AUTO "auto_neg"
#define TXGBE_DEVARG_KR_POLL "poll"
#define TXGBE_DEVARG_KR_PRESENT "present"
#define TXGBE_DEVARG_KX_SGMII "sgmii"
+#define TXGBE_DEVARG_FFE_SET "ffe_set"
+#define TXGBE_DEVARG_FFE_MAIN "ffe_main"
+#define TXGBE_DEVARG_FFE_PRE "ffe_pre"
+#define TXGBE_DEVARG_FFE_POST "ffe_post"
static const char * const txgbe_valid_arguments[] = {
TXGBE_DEVARG_BP_AUTO,
TXGBE_DEVARG_KR_POLL,
TXGBE_DEVARG_KR_PRESENT,
TXGBE_DEVARG_KX_SGMII,
+ TXGBE_DEVARG_FFE_SET,
+ TXGBE_DEVARG_FFE_MAIN,
+ TXGBE_DEVARG_FFE_PRE,
+ TXGBE_DEVARG_FFE_POST,
+ NULL
};
struct txgbe_mbx_stats {
diff --git a/drivers/net/txgbe/txgbe_ethdev.c b/drivers/net/txgbe/txgbe_ethdev.c
index 149cc1771..212c9857f 100644
--- a/drivers/net/txgbe/txgbe_ethdev.c
+++ b/drivers/net/txgbe/txgbe_ethdev.c
@@ -495,6 +495,10 @@ txgbe_parse_devargs(struct txgbe_hw *hw, struct rte_devargs *devargs)
u16 poll = 0;
u16 present = 1;
u16 sgmii = 0;
+ u16 ffe_set = 0;
+ u16 ffe_main = 27;
+ u16 ffe_pre = 8;
+ u16 ffe_post = 44;
if (devargs == NULL)
goto null;
@@ -511,6 +515,14 @@ txgbe_parse_devargs(struct txgbe_hw *hw, struct rte_devargs *devargs)
&txgbe_handle_devarg, &present);
rte_kvargs_process(kvlist, TXGBE_DEVARG_KX_SGMII,
&txgbe_handle_devarg, &sgmii);
+ rte_kvargs_process(kvlist, TXGBE_DEVARG_FFE_SET,
+ &txgbe_handle_devarg, &ffe_set);
+ rte_kvargs_process(kvlist, TXGBE_DEVARG_FFE_MAIN,
+ &txgbe_handle_devarg, &ffe_main);
+ rte_kvargs_process(kvlist, TXGBE_DEVARG_FFE_PRE,
+ &txgbe_handle_devarg, &ffe_pre);
+ rte_kvargs_process(kvlist, TXGBE_DEVARG_FFE_POST,
+ &txgbe_handle_devarg, &ffe_post);
rte_kvargs_free(kvlist);
null:
@@ -518,6 +530,10 @@ txgbe_parse_devargs(struct txgbe_hw *hw, struct rte_devargs *devargs)
hw->devarg.poll = poll;
hw->devarg.present = present;
hw->devarg.sgmii = sgmii;
+ hw->phy.ffe_set = ffe_set;
+ hw->phy.ffe_main = ffe_main;
+ hw->phy.ffe_pre = ffe_pre;
+ hw->phy.ffe_post = ffe_post;
}
static int
@@ -5331,7 +5347,11 @@ RTE_PMD_REGISTER_PARAM_STRING(net_txgbe,
TXGBE_DEVARG_BP_AUTO "=<0|1>"
TXGBE_DEVARG_KR_POLL "=<0|1>"
TXGBE_DEVARG_KR_PRESENT "=<0|1>"
- TXGBE_DEVARG_KX_SGMII "=<0|1>");
+ TXGBE_DEVARG_KX_SGMII "=<0|1>"
+ TXGBE_DEVARG_FFE_SET "=<0-4>"
+ TXGBE_DEVARG_FFE_MAIN "=<uint16>"
+ TXGBE_DEVARG_FFE_PRE "=<uint16>"
+ TXGBE_DEVARG_FFE_POST "=<uint16>");
RTE_LOG_REGISTER(txgbe_logtype_init, pmd.net.txgbe.init, NOTICE);
RTE_LOG_REGISTER(txgbe_logtype_driver, pmd.net.txgbe.driver, NOTICE);
--
2.27.0
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [dpdk-dev] [PATCH v4 6/6] net/txgbe: add FFE parameters for user debugging
2021-03-29 3:17 ` [dpdk-dev] [PATCH v4 6/6] net/txgbe: add FFE parameters for user debugging Jiawen Wu
@ 2021-03-29 15:50 ` Ferruh Yigit
2021-03-30 1:44 ` Jiawen Wu
0 siblings, 1 reply; 10+ messages in thread
From: Ferruh Yigit @ 2021-03-29 15:50 UTC (permalink / raw)
To: Jiawen Wu, dev
On 3/29/2021 4:17 AM, Jiawen Wu wrote:
> Support to set PHY link mode by user defined.
> And update release notes 21.05 for txgbe.
>
During merge, release notes update moved to 3/6 where looks more appropriate,
since this patch adds FFE parameters but note is about AN training. But please
let me know if it is wrong.
> Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
<...>
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [dpdk-dev] [PATCH v4 6/6] net/txgbe: add FFE parameters for user debugging
2021-03-29 15:50 ` Ferruh Yigit
@ 2021-03-30 1:44 ` Jiawen Wu
0 siblings, 0 replies; 10+ messages in thread
From: Jiawen Wu @ 2021-03-30 1:44 UTC (permalink / raw)
To: 'Ferruh Yigit', dev
On March 29, 2021 11:51 PM, Ferruh Yigit wrote:
> On 3/29/2021 4:17 AM, Jiawen Wu wrote:
> > Support to set PHY link mode by user defined.
> > And update release notes 21.05 for txgbe.
> >
>
> During merge, release notes update moved to 3/6 where looks more
> appropriate, since this patch adds FFE parameters but note is about AN
> training. But please let me know if it is wrong.
>
That's right, thanks.
> > Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
>
> <...>
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [dpdk-dev] [PATCH v4 0/6] txgbe backplane AN training
2021-03-29 3:17 [dpdk-dev] [PATCH v4 0/6] txgbe backplane AN training Jiawen Wu
` (5 preceding siblings ...)
2021-03-29 3:17 ` [dpdk-dev] [PATCH v4 6/6] net/txgbe: add FFE parameters for user debugging Jiawen Wu
@ 2021-03-29 15:51 ` Ferruh Yigit
6 siblings, 0 replies; 10+ messages in thread
From: Ferruh Yigit @ 2021-03-29 15:51 UTC (permalink / raw)
To: Jiawen Wu, dev
On 3/29/2021 4:17 AM, Jiawen Wu wrote:
> This series update link process for backplane NICs.
> And support to control AN training.
>
> v4:
> - Convert BP_LOG to dynamic log.
> v3:
> - Add devargs gradually in the patches they are used.
> - Update 21.05 relaese notes.
> v2:
> - Convert compile time flags to runtime options
> - Move firmware version get operation to base code
> - Fix minor bugs
>
> Jiawen Wu (6):
> net/txgbe: update device ID
> net/txgbe: move firmware version get function to base code
> net/txgbe: update link setup process of backplane NICs
> net/txgbe/base: support to handle backplane AN73 flow
> net/txgbe: handle AN interrupt and link update
> net/txgbe: add FFE parameters for user debugging
>
Series applied to dpdk-next-net/main, thanks.
^ permalink raw reply [flat|nested] 10+ messages in thread