From: Pavel Fedin <p.fedin@samsung.com>
To: 'Shlomo Pongratz' <shlomopongratz@gmail.com>,
'Peter Maydell' <peter.maydell@linaro.org>
Cc: eric.auger@linaro.org,
'Shlomo Pongratz' <shlomo.pongratz@huawei.com>,
qemu-devel@nongnu.org, shannon.zhao@linaro.org,
ashoks@broadcom.com, imammedo@redhat.com
Subject: Re: [Qemu-devel] [PATCH RFC V5 9/9] hw/arm: Add virt-v3 machine that uses GIC-500
Date: Wed, 21 Oct 2015 16:26:59 +0300 [thread overview]
Message-ID: <015901d10c04$2aa7fd70$7ff7f850$@samsung.com> (raw)
In-Reply-To: <CAHzK-V3E9HwqijW99JZmT8MaKaXW+E+qXOmqHB8aRSr+7iq8vw@mail.gmail.com>
Hello!
>> The system register implementation belongs in the gic code, not
>> target-arm/. We already have support for devices that say
>> "I have some system registers, please add them to this CPU".
> I don't understand.
> The system registers are defined in ARM Architecture reference Manual.
> It is true that the real implementation is in arm_gicv3_interrupts.c
> But the crn, crm, op0, and op1 of the instructions are in CPU domain.
Not really. If you take a closer look, you'll see that crn, crm, op1, op2 are the same for both ARM64 and ARM32. The only difference is that ARM64 uses op0 = 3, and ARM32 uses cp = 15. Both of these specifiers can coexist in the descriptor table.
I think Peter wants to tell that you should not insert your register table and registration function into target-arm/cpu64.c. This code should go to hw/intc/arm_gicv3_cpu_interface.c, add .cp = 15, and - voila - it magically works with both ARM32 and ARM64.
Kind regards,
Pavel Fedin
Expert Engineer
Samsung Electronics Research center Russia
next prev parent reply other threads:[~2015-10-21 13:27 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-20 17:22 [Qemu-devel] [PATCH RFC V5 0/9] Implement GIC-500 from GICv3 family for arm64 Shlomo Pongratz
2015-10-20 17:22 ` [Qemu-devel] [PATCH RFC V5 2/9] hw/intc: arm_gicv3_interrupts Shlomo Pongratz
2015-10-20 17:22 ` [Qemu-devel] [PATCH RFC V5 3/9] hw/intc: arm_gicv3_cpu_interface Shlomo Pongratz
2015-10-20 17:22 ` [Qemu-devel] [PATCH RFC V5 4/9] hw/intc: arm_gicv3_dist Shlomo Pongratz
2015-10-20 17:22 ` [Qemu-devel] [PATCH RFC V5 5/9] hw/intc arm_gicv3_redist Shlomo Pongratz
2015-10-20 17:22 ` [Qemu-devel] [PATCH RFC V5 6/9] hw/intc: arm_gicv3_spi_its Shlomo Pongratz
2015-10-21 12:43 ` Pavel Fedin
2015-10-21 13:05 ` Shlomo Pongratz
2015-10-21 13:12 ` Pavel Fedin
2015-10-21 13:14 ` Shlomo Pongratz
2015-10-21 13:48 ` Pavel Fedin
2015-10-21 14:19 ` Shlomo Pongratz
2015-10-21 14:26 ` Pavel Fedin
2015-10-21 14:35 ` Shlomo Pongratz
2015-10-21 14:41 ` Pavel Fedin
2015-10-21 14:46 ` Peter Maydell
2015-10-21 14:54 ` Pavel Fedin
2015-10-20 17:22 ` [Qemu-devel] [PATCH RFC V5 7/9] hw/intc: arm_gicv3 Shlomo Pongratz
2015-10-20 17:22 ` [Qemu-devel] [PATCH RFC V5 8/9] target-arm/cpu64 GICv3 system instructions support Shlomo Pongratz
2015-10-22 7:33 ` Pavel Fedin
2015-10-22 8:19 ` Shlomo Pongratz
2015-10-22 8:33 ` Pavel Fedin
2015-10-22 8:52 ` Shlomo Pongratz
2015-10-22 10:05 ` Pavel Fedin
2015-10-22 10:45 ` Shlomo Pongratz
2015-10-20 17:22 ` [Qemu-devel] [PATCH RFC V5 9/9] hw/arm: Add virt-v3 machine that uses GIC-500 Shlomo Pongratz
2015-10-21 7:02 ` Pavel Fedin
2015-10-21 8:52 ` Shlomo Pongratz
2015-10-21 10:30 ` Pavel Fedin
2015-10-21 11:33 ` Shlomo Pongratz
2015-10-21 12:24 ` Peter Maydell
2015-10-21 13:01 ` Shlomo Pongratz
2015-10-21 13:24 ` Peter Maydell
2015-10-21 13:26 ` Pavel Fedin [this message]
2015-10-21 14:05 ` Shlomo Pongratz
[not found] ` <1445361732-16257-2-git-send-email-shlomopongratz@gmail.com>
2015-10-22 11:53 ` [Qemu-devel] [PATCH RFC V5 1/9] hw/intc: Implement GIC-500 support files Pavel Fedin
2016-01-29 16:58 ` [Qemu-devel] [PATCH RFC V5 0/9] Implement GIC-500 from GICv3 family for arm64 Christopher Covington
2016-01-31 15:54 ` Shlomo Pongratz
[not found] ` <CAFEAcA9yQoPzC917Lw2zDsa7a5NOfgEk+x68wA1o+Y4ocywCgw@mail.gmail.com>
[not found] ` <CAHzK-V0Ur=qYM_OAKmSf+smp3M1E49swkT7yUj=jBkLp+J6Pag@mail.gmail.com>
2016-02-21 12:30 ` Shlomo Pongratz
2016-02-21 15:32 ` Peter Maydell
2016-02-22 11:09 ` Peter Maydell
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