[PATCH v2 00/12] Add FSD CSI support

[PATCH v2 00/12] Add FSD CSI support

[Inbaraj E]

FSD CSI(Camera Serial Interface) IP bundles Link controller and DMA
controller for receiving frames. FSD SoC has 12 instances of CSI IP and
3 D-PHY. 4 instances of CSI IP use 1 D-PHY.

This patch series does the following:
1) Refactor the imx-mipi-csis driver to support platform specific
clock names and interrupt handlers through device specific data
(struct mipi_csis_info).
2) Add FSD CSI link controller support in imx-mipi-csis driver.
3) Introduce a new media driver for FSD CSI DMA providing support for
video capture and streaming.
 
These patches were tested on the FSD platform using the
capture_raw_frames application.

Changes since v1:
1. Addressed review comments from Laurent Pinchart to integrate the
with imx-mipi-csis.c to handle the CSIS and expose it as a subdev.

Here is the link to v1 patch for reference:
https://patchwork.kernel.org/project/linux-media/patch/7e7832c16925386b771ddb7e00e08661115aa0ea.1668963790.git.sathya@samsung.com/

Inbaraj E (12):
  dt-bindings: clock: Add CAM_CSI clock macro for FSD
  clk: samsung: fsd: Add clk id for PCLK and PLL in CAM_CSI block
  dt-bindings: media: nxp: Add support for FSD SoC
  arm64: dts: fsd: Add CSI nodes
  media: imx-mipi-csis: Move clk to mipi_csis_info structure
  media: imx-mipi-csis: Move irq flag and handler to mipi_csis_info
    structure
  media: imx-mipi-csis: Add support to configure specific vc
  media: imx-mipi-csis: Add support to dump all vc regs
  media: imx-mipi-csis: Add support for FSD CSI Rx
  dt-bindings: media: fsd: Document CSIS DMA controller
  arm64: defconfig: Enable FSD CSIS DMA driver
  media: fsd-csis: Add support for FSD CSIS DMA

 .../bindings/media/nxp,imx-mipi-csi2.yaml     |   88 +-
 .../bindings/media/tesla,fsd-csis-media.yaml  |   74 +
 MAINTAINERS                                   |    8 +
 arch/arm64/boot/dts/tesla/fsd-evb.dts         |   96 +
 arch/arm64/boot/dts/tesla/fsd.dtsi            |  552 ++++++
 arch/arm64/configs/defconfig                  |    1 +
 drivers/clk/samsung/clk-fsd.c                 |   28 +-
 drivers/media/platform/nxp/imx-mipi-csis.c    |  354 +++-
 drivers/media/platform/samsung/Kconfig        |    1 +
 drivers/media/platform/samsung/Makefile       |    1 +
 .../media/platform/samsung/fsd-csis/Kconfig   |   16 +
 .../media/platform/samsung/fsd-csis/Makefile  |    3 +
 .../platform/samsung/fsd-csis/fsd-csis.c      | 1730 +++++++++++++++++
 include/dt-bindings/clock/fsd-clk.h           |   13 +
 14 files changed, 2890 insertions(+), 75 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/media/tesla,fsd-csis-media.yaml
 create mode 100644 drivers/media/platform/samsung/fsd-csis/Kconfig
 create mode 100644 drivers/media/platform/samsung/fsd-csis/Makefile
 create mode 100644 drivers/media/platform/samsung/fsd-csis/fsd-csis.c

-- 
2.49.0

[PATCH v2 01/12] dt-bindings: clock: Add CAM_CSI clock macro for FSD

[Inbaraj E]

CAM_CSI block has ACLK, PCLK and PLL clocks. PCLK id is already
assigned. To use PCLK and PLL clock in driver add id macro for CAM_CSI_PLL
and CAM_CSI_PCLK.

Signed-off-by: Inbaraj E <inbaraj.e@samsung.com>
---
 include/dt-bindings/clock/fsd-clk.h | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/include/dt-bindings/clock/fsd-clk.h b/include/dt-bindings/clock/fsd-clk.h
index 3f7b64d93558..58fdec8f4c2a 100644
--- a/include/dt-bindings/clock/fsd-clk.h
+++ b/include/dt-bindings/clock/fsd-clk.h
@@ -139,5 +139,18 @@
 #define CAM_CSI2_1_IPCLKPORT_I_ACLK		10
 #define CAM_CSI2_2_IPCLKPORT_I_ACLK		11
 #define CAM_CSI2_3_IPCLKPORT_I_ACLK		12
+#define CAM_CSI_PLL				13
+#define CAM_CSI0_0_IPCLKPORT_I_PCLK		14
+#define CAM_CSI0_1_IPCLKPORT_I_PCLK		15
+#define CAM_CSI0_2_IPCLKPORT_I_PCLK		16
+#define CAM_CSI0_3_IPCLKPORT_I_PCLK		17
+#define CAM_CSI1_0_IPCLKPORT_I_PCLK		18
+#define CAM_CSI1_1_IPCLKPORT_I_PCLK		19
+#define CAM_CSI1_2_IPCLKPORT_I_PCLK		20
+#define CAM_CSI1_3_IPCLKPORT_I_PCLK		21
+#define CAM_CSI2_0_IPCLKPORT_I_PCLK		22
+#define CAM_CSI2_1_IPCLKPORT_I_PCLK		23
+#define CAM_CSI2_2_IPCLKPORT_I_PCLK		24
+#define CAM_CSI2_3_IPCLKPORT_I_PCLK		25
 
 #endif /*_DT_BINDINGS_CLOCK_FSD_H */
-- 
2.49.0

Re: (subset) [PATCH v2 01/12] dt-bindings: clock: Add CAM_CSI clock macro for FSD

[Krzysztof Kozlowski]

On Thu, 14 Aug 2025 19:39:32 +0530, Inbaraj E wrote:
> CAM_CSI block has ACLK, PCLK and PLL clocks. PCLK id is already
> assigned. To use PCLK and PLL clock in driver add id macro for CAM_CSI_PLL
> and CAM_CSI_PCLK.
> 
> 

Applied, thanks!

[01/12] dt-bindings: clock: Add CAM_CSI clock macro for FSD
        https://git.kernel.org/krzk/linux/c/5576d8098052952a6c95af86ad3dcb341554ac75

Best regards,
-- 
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

[PATCH v2 02/12] clk: samsung: fsd: Add clk id for PCLK and PLL in CAM_CSI block

[Inbaraj E]

Add clock id for PCLK and PLL. These clock id will be used for
operation of CSI driver. PCLK is AXI2APB clock used for register
access. PLL clock is main clock source for CAM_CSI block.

Signed-off-by: Inbaraj E <inbaraj.e@samsung.com>
---
 drivers/clk/samsung/clk-fsd.c | 28 ++++++++++++++--------------
 1 file changed, 14 insertions(+), 14 deletions(-)

diff --git a/drivers/clk/samsung/clk-fsd.c b/drivers/clk/samsung/clk-fsd.c
index 594931334574..4124d65e3d18 100644
--- a/drivers/clk/samsung/clk-fsd.c
+++ b/drivers/clk/samsung/clk-fsd.c
@@ -89,7 +89,7 @@
 #define CLKS_NR_FSYS1		(PCIE_LINK1_IPCLKPORT_SLV_ACLK + 1)
 #define CLKS_NR_IMEM		(IMEM_TMU_GT_IPCLKPORT_I_CLK_TS + 1)
 #define CLKS_NR_MFC		(MFC_MFC_IPCLKPORT_ACLK + 1)
-#define CLKS_NR_CAM_CSI		(CAM_CSI2_3_IPCLKPORT_I_ACLK + 1)
+#define CLKS_NR_CAM_CSI		(CAM_CSI2_3_IPCLKPORT_I_PCLK + 1)
 
 static const unsigned long cmu_clk_regs[] __initconst = {
 	PLL_LOCKTIME_PLL_SHARED0,
@@ -1646,7 +1646,7 @@ static const struct samsung_pll_rate_table pll_cam_csi_rate_table[] __initconst
 };
 
 static const struct samsung_pll_clock cam_csi_pll_clks[] __initconst = {
-	PLL(pll_142xx, 0, "fout_pll_cam_csi", "fin_pll",
+	PLL(pll_142xx, CAM_CSI_PLL, "fout_pll_cam_csi", "fin_pll",
 	    PLL_LOCKTIME_PLL_CAM_CSI, PLL_CON0_PLL_CAM_CSI, pll_cam_csi_rate_table),
 };
 
@@ -1682,51 +1682,51 @@ static const struct samsung_gate_clock cam_csi_gate_clks[] __initconst = {
 	     GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__NOC, 21, CLK_IGNORE_UNUSED, 0),
 	GATE(CAM_CSI0_0_IPCLKPORT_I_ACLK, "cam_csi0_0_ipclkport_i_aclk", "dout_cam_csi0_aclk",
 	     GAT_CAM_CSI0_0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
-	GATE(0, "cam_csi0_0_ipclkport_i_pclk", "dout_cam_csi_busp",
+	GATE(CAM_CSI0_0_IPCLKPORT_I_PCLK, "cam_csi0_0_ipclkport_i_pclk", "dout_cam_csi_busp",
 	     GAT_CAM_CSI0_0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
 	GATE(CAM_CSI0_1_IPCLKPORT_I_ACLK, "cam_csi0_1_ipclkport_i_aclk", "dout_cam_csi0_aclk",
 	     GAT_CAM_CSI0_1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
-	GATE(0, "cam_csi0_1_ipclkport_i_pclk", "dout_cam_csi_busp",
+	GATE(CAM_CSI0_1_IPCLKPORT_I_PCLK, "cam_csi0_1_ipclkport_i_pclk", "dout_cam_csi_busp",
 	     GAT_CAM_CSI0_1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
 	GATE(CAM_CSI0_2_IPCLKPORT_I_ACLK, "cam_csi0_2_ipclkport_i_aclk", "dout_cam_csi0_aclk",
 	     GAT_CAM_CSI0_2_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
-	GATE(0, "cam_csi0_2_ipclkport_i_pclk", "dout_cam_csi_busp",
+	GATE(CAM_CSI0_2_IPCLKPORT_I_PCLK, "cam_csi0_2_ipclkport_i_pclk", "dout_cam_csi_busp",
 	     GAT_CAM_CSI0_2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
 	GATE(CAM_CSI0_3_IPCLKPORT_I_ACLK, "cam_csi0_3_ipclkport_i_aclk", "dout_cam_csi0_aclk",
 	     GAT_CAM_CSI0_3_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
-	GATE(0, "cam_csi0_3_ipclkport_i_pclk", "dout_cam_csi_busp",
+	GATE(CAM_CSI0_3_IPCLKPORT_I_PCLK, "cam_csi0_3_ipclkport_i_pclk", "dout_cam_csi_busp",
 	     GAT_CAM_CSI0_3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
 	GATE(CAM_CSI1_0_IPCLKPORT_I_ACLK, "cam_csi1_0_ipclkport_i_aclk", "dout_cam_csi1_aclk",
 	     GAT_CAM_CSI1_0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
-	GATE(0, "cam_csi1_0_ipclkport_i_pclk", "dout_cam_csi_busp",
+	GATE(CAM_CSI1_0_IPCLKPORT_I_PCLK, "cam_csi1_0_ipclkport_i_pclk", "dout_cam_csi_busp",
 	     GAT_CAM_CSI1_0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
 	GATE(CAM_CSI1_1_IPCLKPORT_I_ACLK, "cam_csi1_1_ipclkport_i_aclk", "dout_cam_csi1_aclk",
 	     GAT_CAM_CSI1_1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
-	GATE(0, "cam_csi1_1_ipclkport_i_pclk", "dout_cam_csi_busp",
+	GATE(CAM_CSI1_1_IPCLKPORT_I_PCLK, "cam_csi1_1_ipclkport_i_pclk", "dout_cam_csi_busp",
 	     GAT_CAM_CSI1_1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
 	GATE(CAM_CSI1_2_IPCLKPORT_I_ACLK, "cam_csi1_2_ipclkport_i_aclk", "dout_cam_csi1_aclk",
 	     GAT_CAM_CSI1_2_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
-	GATE(0, "cam_csi1_2_ipclkport_i_pclk", "dout_cam_csi_busp",
+	GATE(CAM_CSI1_2_IPCLKPORT_I_PCLK, "cam_csi1_2_ipclkport_i_pclk", "dout_cam_csi_busp",
 	     GAT_CAM_CSI1_2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
 	GATE(CAM_CSI1_3_IPCLKPORT_I_ACLK, "cam_csi1_3_ipclkport_i_aclk", "dout_cam_csi1_aclk",
 	     GAT_CAM_CSI1_3_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
-	GATE(0, "cam_csi1_3_ipclkport_i_pclk", "dout_cam_csi_busp",
+	GATE(CAM_CSI1_3_IPCLKPORT_I_PCLK, "cam_csi1_3_ipclkport_i_pclk", "dout_cam_csi_busp",
 	     GAT_CAM_CSI1_3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
 	GATE(CAM_CSI2_0_IPCLKPORT_I_ACLK, "cam_csi2_0_ipclkport_i_aclk", "dout_cam_csi2_aclk",
 	     GAT_CAM_CSI2_0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
-	GATE(0, "cam_csi2_0_ipclkport_i_pclk", "dout_cam_csi_busp",
+	GATE(CAM_CSI2_0_IPCLKPORT_I_PCLK, "cam_csi2_0_ipclkport_i_pclk", "dout_cam_csi_busp",
 	     GAT_CAM_CSI2_0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
 	GATE(CAM_CSI2_1_IPCLKPORT_I_ACLK, "cam_csi2_1_ipclkport_i_aclk", "dout_cam_csi2_aclk",
 	     GAT_CAM_CSI2_1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
-	GATE(0, "cam_csi2_1_ipclkport_i_pclk", "dout_cam_csi_busp",
+	GATE(CAM_CSI2_1_IPCLKPORT_I_PCLK, "cam_csi2_1_ipclkport_i_pclk", "dout_cam_csi_busp",
 	     GAT_CAM_CSI2_1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
 	GATE(CAM_CSI2_2_IPCLKPORT_I_ACLK, "cam_csi2_2_ipclkport_i_aclk", "dout_cam_csi2_aclk",
 	     GAT_CAM_CSI2_2_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
-	GATE(0, "cam_csi2_2_ipclkport_i_pclk", "dout_cam_csi_busp",
+	GATE(CAM_CSI2_2_IPCLKPORT_I_PCLK, "cam_csi2_2_ipclkport_i_pclk", "dout_cam_csi_busp",
 	     GAT_CAM_CSI2_2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
 	GATE(CAM_CSI2_3_IPCLKPORT_I_ACLK, "cam_csi2_3_ipclkport_i_aclk", "dout_cam_csi2_aclk",
 	     GAT_CAM_CSI2_3_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0),
-	GATE(0, "cam_csi2_3_ipclkport_i_pclk", "dout_cam_csi_busp",
+	GATE(CAM_CSI2_3_IPCLKPORT_I_PCLK, "cam_csi2_3_ipclkport_i_pclk", "dout_cam_csi_busp",
 	     GAT_CAM_CSI2_3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0),
 	GATE(0, "cam_ns_brdg_cam_csi_ipclkport_clk__psoc_cam_csi__clk_cam_csi_d",
 	     "dout_cam_csi_busd",
-- 
2.49.0

Re: (subset) [PATCH v2 02/12] clk: samsung: fsd: Add clk id for PCLK and PLL in CAM_CSI block

[Krzysztof Kozlowski]

On Thu, 14 Aug 2025 19:39:33 +0530, Inbaraj E wrote:
> Add clock id for PCLK and PLL. These clock id will be used for
> operation of CSI driver. PCLK is AXI2APB clock used for register
> access. PLL clock is main clock source for CAM_CSI block.
> 
> 

Applied, thanks!

[02/12] clk: samsung: fsd: Add clk id for PCLK and PLL in CAM_CSI block
        https://git.kernel.org/krzk/linux/c/1a713bd3b0c60d826bdde633919bedc1fd38df4d

Best regards,
-- 
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

[PATCH v2 03/12] dt-bindings: media: nxp: Add support for FSD SoC

[Inbaraj E]

Document the MIPI CSI2 controller device tree bindings for Tesla
FSD SoC

Signed-off-by: Inbaraj E <inbaraj.e@samsung.com>
---
 .../bindings/media/nxp,imx-mipi-csi2.yaml     | 88 ++++++++++++++-----
 1 file changed, 68 insertions(+), 20 deletions(-)

diff --git a/Documentation/devicetree/bindings/media/nxp,imx-mipi-csi2.yaml b/Documentation/devicetree/bindings/media/nxp,imx-mipi-csi2.yaml
index 03a23a26c4f3..802fb1bd150d 100644
--- a/Documentation/devicetree/bindings/media/nxp,imx-mipi-csi2.yaml
+++ b/Documentation/devicetree/bindings/media/nxp,imx-mipi-csi2.yaml
@@ -14,7 +14,7 @@ description: |-
   The NXP i.MX7 and i.MX8 families contain SoCs that include a MIPI CSI-2
   receiver IP core named CSIS. The IP core originates from Samsung, and may be
   compatible with some of the Exynos4 and S5P SoCs. i.MX7 SoCs use CSIS version
-  3.3, and i.MX8 SoCs use CSIS version 3.6.3.
+  3.3, i.MX8 SoCs use CSIS version 3.6.3 and FSD SoC uses CSIS version 4.3.
 
   While the CSI-2 receiver is separate from the MIPI D-PHY IP core, the PHY is
   completely wrapped by the CSIS and doesn't expose a control interface of its
@@ -26,6 +26,7 @@ properties:
       - enum:
           - fsl,imx7-mipi-csi2
           - fsl,imx8mm-mipi-csi2
+          - tesla,fsd-mipi-csi2
       - items:
           - enum:
               - fsl,imx8mp-mipi-csi2
@@ -38,24 +39,21 @@ properties:
     maxItems: 1
 
   clocks:
-    minItems: 3
-    items:
-      - description: The peripheral clock (a.k.a. APB clock)
-      - description: The external clock (optionally used as the pixel clock)
-      - description: The MIPI D-PHY clock
-      - description: The AXI clock
+    minItems: 2
+    maxItems: 4
 
   clock-names:
-    minItems: 3
-    items:
-      - const: pclk
-      - const: wrap
-      - const: phy
-      - const: axi
+    minItems: 2
+    maxItems: 4
 
   power-domains:
     maxItems: 1
 
+  samsung,syscon-csis:
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    description:
+      Syscon used to hold and release the reset of MIPI D-PHY
+
   phy-supply:
     description: The MIPI D-PHY digital power supply
 
@@ -85,7 +83,8 @@ properties:
             properties:
               data-lanes:
                 description:
-                  Note that 'fsl,imx7-mipi-csi2' only supports up to 2 data lines.
+                  Note that 'fsl,imx7-mipi-csi2' only supports up to 2 data
+                  lines.
                 minItems: 1
                 items:
                   - const: 1
@@ -107,7 +106,6 @@ required:
   - interrupts
   - clocks
   - clock-names
-  - power-domains
   - ports
 
 additionalProperties: false
@@ -116,20 +114,70 @@ allOf:
   - if:
       properties:
         compatible:
-          contains:
-            const: fsl,imx7-mipi-csi2
+          const: fsl,imx7-mipi-csi2
     then:
+      properties:
+        clocks:
+          items:
+            - description: The peripheral clock (a.k.a. APB clock)
+            - description: The external clock (optionally used as the pixel
+                clock)
+            - description: The MIPI D-PHY clock
+        clock-names:
+          items:
+            - const: pclk
+            - const: wrap
+            - const: phy
+        samsung,syscon-csis: false
       required:
+        - power-domains
         - phy-supply
         - resets
-    else:
+
+  - if:
+      properties:
+        compatible:
+          const: fsl,imx8mm-mipi-csi2
+    then:
       properties:
         clocks:
-          minItems: 4
+          items:
+            - description: The peripheral clock (a.k.a. APB clock)
+            - description: The external clock (optionally used as the pixel
+                clock)
+            - description: The MIPI D-PHY clock
+            - description: The AXI clock
         clock-names:
-          minItems: 4
+          items:
+            - const: pclk
+            - const: wrap
+            - const: phy
+            - const: axi
+        samsung,syscon-csis: false
         phy-supply: false
         resets: false
+      required:
+        - power-domains
+
+  - if:
+      properties:
+        compatible:
+          const: tesla,fsd-mipi-csi2
+    then:
+      properties:
+        clocks:
+          items:
+            - description: The peripheral clock (a.k.a. APB clock)
+            - description: The DMA clock
+        clocks-names:
+          items:
+            - const: pclk
+            - const: aclk
+        phy-supply: false
+        resets: false
+        power-domains: false
+      required:
+        - samsung,syscon-csis
 
 examples:
   - |
-- 
2.49.0

Re: [PATCH v2 03/12] dt-bindings: media: nxp: Add support for FSD SoC

[Krzysztof Kozlowski]

On 14/08/2025 16:09, Inbaraj E wrote:
> Document the MIPI CSI2 controller device tree bindings for Tesla
> FSD SoC

Explain the hardware.

> 
> Signed-off-by: Inbaraj E <inbaraj.e@samsung.com>
> ---
>  .../bindings/media/nxp,imx-mipi-csi2.yaml     | 88 ++++++++++++++-----
>  1 file changed, 68 insertions(+), 20 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/media/nxp,imx-mipi-csi2.yaml b/Documentation/devicetree/bindings/media/nxp,imx-mipi-csi2.yaml
> index 03a23a26c4f3..802fb1bd150d 100644
> --- a/Documentation/devicetree/bindings/media/nxp,imx-mipi-csi2.yaml
> +++ b/Documentation/devicetree/bindings/media/nxp,imx-mipi-csi2.yaml
> @@ -14,7 +14,7 @@ description: |-
>    The NXP i.MX7 and i.MX8 families contain SoCs that include a MIPI CSI-2
>    receiver IP core named CSIS. The IP core originates from Samsung, and may be
>    compatible with some of the Exynos4 and S5P SoCs. i.MX7 SoCs use CSIS version
> -  3.3, and i.MX8 SoCs use CSIS version 3.6.3.
> +  3.3, i.MX8 SoCs use CSIS version 3.6.3 and FSD SoC uses CSIS version 4.3.
>  
>    While the CSI-2 receiver is separate from the MIPI D-PHY IP core, the PHY is
>    completely wrapped by the CSIS and doesn't expose a control interface of its
> @@ -26,6 +26,7 @@ properties:
>        - enum:
>            - fsl,imx7-mipi-csi2
>            - fsl,imx8mm-mipi-csi2
> +          - tesla,fsd-mipi-csi2


Isn't this Samsung CSI IP? Why are you adding it to NXP? Nothing in
commit msg helps me to understand that.

>        - items:
>            - enum:
>                - fsl,imx8mp-mipi-csi2
> @@ -38,24 +39,21 @@ properties:
>      maxItems: 1
>  
>    clocks:
> -    minItems: 3
> -    items:
> -      - description: The peripheral clock (a.k.a. APB clock)
> -      - description: The external clock (optionally used as the pixel clock)
> -      - description: The MIPI D-PHY clock
> -      - description: The AXI clock
> +    minItems: 2
> +    maxItems: 4
>  
>    clock-names:
> -    minItems: 3
> -    items:
> -      - const: pclk
> -      - const: wrap
> -      - const: phy
> -      - const: axi
> +    minItems: 2
> +    maxItems: 4
>  
>    power-domains:
>      maxItems: 1
>  
> +  samsung,syscon-csis:

samsung, so not nxp. Even more confusing.


Best regards,
Krzysztof

RE: [PATCH v2 03/12] dt-bindings: media: nxp: Add support for FSD SoC

[Inbaraj E]

Hi Krzysztof,

Thanks for the review.

> 
> Explain the hardware.

I'll explain in the next patchset.

> 
> >
> > Signed-off-by: Inbaraj E <inbaraj.e@samsung.com>
> > ---
> >  .../bindings/media/nxp,imx-mipi-csi2.yaml     | 88 ++++++++++++++-----
> >  1 file changed, 68 insertions(+), 20 deletions(-)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/media/nxp,imx-mipi-csi2.yaml
> > b/Documentation/devicetree/bindings/media/nxp,imx-mipi-csi2.yaml
> > index 03a23a26c4f3..802fb1bd150d 100644
> > --- a/Documentation/devicetree/bindings/media/nxp,imx-mipi-csi2.yaml
> > +++ b/Documentation/devicetree/bindings/media/nxp,imx-mipi-csi2.yaml
> > @@ -14,7 +14,7 @@ description: |-
> >    The NXP i.MX7 and i.MX8 families contain SoCs that include a MIPI CSI-2
> >    receiver IP core named CSIS. The IP core originates from Samsung, and
> may be
> >    compatible with some of the Exynos4 and S5P SoCs. i.MX7 SoCs use
> > CSIS version
> > -  3.3, and i.MX8 SoCs use CSIS version 3.6.3.
> > +  3.3, i.MX8 SoCs use CSIS version 3.6.3 and FSD SoC uses CSIS version 4.3.
> >
> >    While the CSI-2 receiver is separate from the MIPI D-PHY IP core, the PHY
> is
> >    completely wrapped by the CSIS and doesn't expose a control
> > interface of its @@ -26,6 +26,7 @@ properties:
> >        - enum:
> >            - fsl,imx7-mipi-csi2
> >            - fsl,imx8mm-mipi-csi2
> > +          - tesla,fsd-mipi-csi2
> 
> 
> Isn't this Samsung CSI IP? 

Yes, it is Samsung CSI IP.

Why are you adding it to NXP?

Samsung CSIS IP core present in Exynos(samsung/exynos4-is/mipi-csis.c) series is
completely different from the one in the Tesla FSD SoC. However, it is compatible
with the samsung CSIS IP used in the NXP SoC. For better code reusability, I am
integrating it with the NXP imx-mipi-csis driver.

 
> Nothing in commit, msg helps me to understand that.

I'll explain the same in commit description as well.

> 

> >        - items:
> >            - enum:
> >                - fsl,imx8mp-mipi-csi2
> > @@ -38,24 +39,21 @@ properties:
> >      maxItems: 1
> >
> >    clocks:
> > -    minItems: 3
> > -    items:
> > -      - description: The peripheral clock (a.k.a. APB clock)
> > -      - description: The external clock (optionally used as the pixel clock)
> > -      - description: The MIPI D-PHY clock
> > -      - description: The AXI clock
> > +    minItems: 2
> > +    maxItems: 4
> >
> >    clock-names:
> > -    minItems: 3
> > -    items:
> > -      - const: pclk
> > -      - const: wrap
> > -      - const: phy
> > -      - const: axi
> > +    minItems: 2
> > +    maxItems: 4
> >
> >    power-domains:
> >      maxItems: 1
> >
> > +  samsung,syscon-csis:
> 
> samsung, so not nxp. Even more confusing.
> 

I used samsung,syscon-csis because the system controller on Tesla FSD
follows Samsung's sysreg design.

> 
> Best regards,
> Krzysztof

Regards,
Inbaraj E

Re: [PATCH v2 03/12] dt-bindings: media: nxp: Add support for FSD SoC

[Krzysztof Kozlowski]

On 22/08/2025 15:39, Inbaraj E wrote:
>>>
>>>    power-domains:
>>>      maxItems: 1
>>>
>>> +  samsung,syscon-csis:
>>
>> samsung, so not nxp. Even more confusing.
>>
> 
> I used samsung,syscon-csis because the system controller on Tesla FSD
> follows Samsung's sysreg design.

OK, this is property for Tesla though, so please use tesla prefix.

Best regards,
Krzysztof

RE: [PATCH v2 03/12] dt-bindings: media: nxp: Add support for FSD SoC

[Inbaraj E]

> On 22/08/2025 15:39, Inbaraj E wrote:
> >>>
> >>>    power-domains:
> >>>      maxItems: 1
> >>>
> >>> +  samsung,syscon-csis:
> >>
> >> samsung, so not nxp. Even more confusing.
> >>
> >
> > I used samsung,syscon-csis because the system controller on Tesla FSD
> > follows Samsung's sysreg design.
> 
> OK, this is property for Tesla though, so please use tesla prefix.

Using tesla,syscon-csis results in a "prefix not found" issue when running dtbs_check

Regards,
Inbaraj E

Re: [PATCH v2 03/12] dt-bindings: media: nxp: Add support for FSD SoC

[Krzysztof Kozlowski]

On 22/08/2025 16:00, Inbaraj E wrote:
>> On 22/08/2025 15:39, Inbaraj E wrote:
>>>>>
>>>>>    power-domains:
>>>>>      maxItems: 1
>>>>>
>>>>> +  samsung,syscon-csis:
>>>>
>>>> samsung, so not nxp. Even more confusing.
>>>>
>>>
>>> I used samsung,syscon-csis because the system controller on Tesla FSD
>>> follows Samsung's sysreg design.
>>
>> OK, this is property for Tesla though, so please use tesla prefix.
> 
> Using tesla,syscon-csis results in a "prefix not found" issue when running dtbs_check
Because you develop on ancient, 10 year old downstream kernel?

You really do not try enough and this is just wasting our time.

Please think and really carefully check your replies. What prefix do you
have in compatible? This command:
git grep tesla, | wc -l

gives '99' results including obviously vendor prefix.

So your warning is basically impossible or your code is just broken.
Don't just ask maintainers on every little trouble you have. You must
debug it. Not we.

Best regards,
Krzysztof

RE: [PATCH v2 03/12] dt-bindings: media: nxp: Add support for FSD SoC

[Inbaraj E]

Hi Krzysztof,

> >
> > Using tesla,syscon-csis results in a "prefix not found" issue when
> > running dtbs_check
> Because you develop on ancient, 10 year old downstream kernel?
> 
> You really do not try enough and this is just wasting our time.
> 
> Please think and really carefully check your replies. What prefix do you have
> in compatible? This command:
> git grep tesla, | wc -l
> 
> gives '99' results including obviously vendor prefix.
> 
> So your warning is basically impossible or your code is just broken.
> Don't just ask maintainers on every little trouble you have. You must debug
> it. Not we.
> 

Sorry, I made a mistake while  running dtbs_check. I'll use the tesla prefix in the next
patchset

Regards,
Inbaraj E

[PATCH v2 04/12] arm64: dts: fsd: Add CSI nodes

[Inbaraj E]

There is a csi dma and csis interface that bundles together to allow
csi2 capture.

Signed-off-by: Inbaraj E <inbaraj.e@samsung.com>
---
 arch/arm64/boot/dts/tesla/fsd-evb.dts |  96 +++++
 arch/arm64/boot/dts/tesla/fsd.dtsi    | 552 ++++++++++++++++++++++++++
 2 files changed, 648 insertions(+)

diff --git a/arch/arm64/boot/dts/tesla/fsd-evb.dts b/arch/arm64/boot/dts/tesla/fsd-evb.dts
index 9ff22e1c8723..dcc9a138cdb9 100644
--- a/arch/arm64/boot/dts/tesla/fsd-evb.dts
+++ b/arch/arm64/boot/dts/tesla/fsd-evb.dts
@@ -130,3 +130,99 @@ &serial_0 {
 &ufs {
 	status = "okay";
 };
+
+&mipicsis0 {
+	status = "okay";
+};
+
+&mipicsis1 {
+	status = "okay";
+};
+
+&mipicsis2 {
+	status = "okay";
+};
+
+&mipicsis3 {
+	status = "okay";
+};
+
+&mipicsis4 {
+	status = "okay";
+};
+
+&mipicsis5 {
+	status = "okay";
+};
+
+&mipicsis6 {
+	status = "okay";
+};
+
+&mipicsis7 {
+	status = "okay";
+};
+
+&mipicsis8 {
+	status = "okay";
+};
+
+&mipicsis9 {
+	status = "okay";
+};
+
+&mipicsis10 {
+	status = "okay";
+};
+
+&mipicsis11 {
+	status = "okay";
+};
+
+&csis0 {
+	status = "okay";
+};
+
+&csis1 {
+	status = "okay";
+};
+
+&csis2 {
+	status = "okay";
+};
+
+&csis3 {
+	status = "okay";
+};
+
+&csis4 {
+	status = "okay";
+};
+
+&csis5 {
+	status = "okay";
+};
+
+&csis6 {
+	status = "okay";
+};
+
+&csis7 {
+	status = "okay";
+};
+
+&csis8 {
+	status = "okay";
+};
+
+&csis9 {
+	status = "okay";
+};
+
+&csis10 {
+	status = "okay";
+};
+
+&csis11 {
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi
index a5ebb3f9b18f..a83503e9c502 100644
--- a/arch/arm64/boot/dts/tesla/fsd.dtsi
+++ b/arch/arm64/boot/dts/tesla/fsd.dtsi
@@ -493,6 +493,558 @@ clock_mfc: clock-controller@12810000 {
 			clock-names = "fin_pll";
 		};
 
+		mipicsis0: mipi-csis@12640000 {
+			compatible = "tesla,fsd-mipi-csi2";
+			reg = <0x0 0x12640000 0x0 0x124>;
+			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clock_csi CAM_CSI0_0_IPCLKPORT_I_ACLK>,
+				<&clock_csi CAM_CSI0_0_IPCLKPORT_I_PCLK>;
+			clock-names = "aclk", "pclk";
+			samsung,syscon-csis = <&sysreg_cam 0x40c>;
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+				};
+
+				port@1 {
+					reg = <1>;
+
+					mipi_csis_0_out: endpoint {
+						remote-endpoint = <&csis_in_0>;
+					};
+				};
+			};
+		};
+
+		csis0: csis@12641000 {
+			compatible = "tesla,fsd-csis-media";
+			reg = <0x0 0x12641000 0x0 0x44c>;
+			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clock_csi CAM_CSI0_0_IPCLKPORT_I_ACLK>,
+				<&clock_csi CAM_CSI0_0_IPCLKPORT_I_PCLK>,
+				<&clock_csi CAM_CSI_PLL>;
+			clock-names = "aclk", "pclk", "pll";
+			iommus = <&smmu_isp 0x0 0x0>;
+			status = "disabled";
+
+			port {
+				csis_in_0: endpoint {
+					remote-endpoint = <&mipi_csis_0_out>;
+				};
+			};
+		};
+
+		mipicsis1: mipi-csis@12650000 {
+			compatible = "tesla,fsd-mipi-csi2";
+			reg = <0x0 0x12650000 0x0 0x124>;
+			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clock_csi CAM_CSI0_1_IPCLKPORT_I_ACLK>,
+				<&clock_csi CAM_CSI0_1_IPCLKPORT_I_PCLK>;
+			clock-names = "aclk", "pclk";
+			samsung,syscon-csis = <&sysreg_cam 0x40c>;
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+				};
+
+				port@1 {
+					reg = <1>;
+
+					mipi_csis_1_out: endpoint {
+						remote-endpoint = <&csis_in_1>;
+					};
+				};
+			};
+		};
+
+		csis1: csis@12651000 {
+			compatible = "tesla,fsd-csis-media";
+			reg = <0x0 0x12651000 0x0 0x44c>;
+			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clock_csi CAM_CSI0_1_IPCLKPORT_I_ACLK>,
+				<&clock_csi CAM_CSI0_1_IPCLKPORT_I_PCLK>,
+				<&clock_csi CAM_CSI_PLL>;
+			clock-names = "aclk", "pclk", "pll";
+			iommus = <&smmu_isp 0x0 0x0>;
+			status = "disabled";
+
+			port {
+				csis_in_1: endpoint {
+					remote-endpoint = <&mipi_csis_1_out>;
+				};
+			};
+		};
+
+		mipicsis2: mipi-csis@12660000 {
+			compatible = "tesla,fsd-mipi-csi2";
+			reg = <0x0 0x12660000 0x0 0x124>;
+			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clock_csi CAM_CSI0_2_IPCLKPORT_I_ACLK>,
+				<&clock_csi CAM_CSI0_2_IPCLKPORT_I_PCLK>;
+			clock-names = "aclk", "pclk";
+			samsung,syscon-csis = <&sysreg_cam 0x40c>;
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+				};
+
+				port@1 {
+					reg = <1>;
+
+					mipi_csis_2_out: endpoint {
+						remote-endpoint = <&csis_in_2>;
+					};
+				};
+			};
+		};
+
+		csis2: csis@12661000 {
+			compatible = "tesla,fsd-csis-media";
+			reg = <0x0 0x12661000 0x0 0x44c>;
+			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clock_csi CAM_CSI0_2_IPCLKPORT_I_ACLK>,
+				<&clock_csi CAM_CSI0_2_IPCLKPORT_I_PCLK>,
+				<&clock_csi CAM_CSI_PLL>;
+			clock-names = "aclk", "pclk", "pll";
+			iommus = <&smmu_isp 0x0 0x0>;
+			status = "disabled";
+
+			port {
+				csis_in_2: endpoint {
+					remote-endpoint = <&mipi_csis_2_out>;
+				};
+			};
+		};
+
+		mipicsis3: mipi-csis@12670000 {
+			compatible = "tesla,fsd-mipi-csi2";
+			reg = <0x0 0x12670000 0x0 0x124>;
+			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clock_csi CAM_CSI0_3_IPCLKPORT_I_ACLK>,
+				<&clock_csi CAM_CSI0_3_IPCLKPORT_I_PCLK>;
+			clock-names = "aclk", "pclk";
+			samsung,syscon-csis = <&sysreg_cam 0x40c>;
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+				};
+
+				port@1 {
+					reg = <1>;
+
+					mipi_csis_3_out: endpoint {
+						remote-endpoint = <&csis_in_3>;
+					};
+				};
+			};
+		};
+
+		csis3: csis@12671000 {
+			compatible = "tesla,fsd-csis-media";
+			reg = <0x0 0x12671000 0x0 0x44c>;
+			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clock_csi CAM_CSI0_3_IPCLKPORT_I_ACLK>,
+				<&clock_csi CAM_CSI0_3_IPCLKPORT_I_PCLK>,
+				<&clock_csi CAM_CSI_PLL>;
+			clock-names = "aclk", "pclk", "pll";
+			iommus = <&smmu_isp 0x0 0x0>;
+			status = "disabled";
+
+			port {
+				csis_in_3: endpoint {
+					remote-endpoint = <&mipi_csis_3_out>;
+				};
+			};
+		};
+
+		mipicsis4: mipi-csis@12680000 {
+			compatible = "tesla,fsd-mipi-csi2";
+			reg = <0x0 0x12680000 0x0 0x124>;
+			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clock_csi CAM_CSI1_0_IPCLKPORT_I_ACLK>,
+				<&clock_csi CAM_CSI1_0_IPCLKPORT_I_PCLK>;
+			clock-names = "aclk", "pclk";
+			samsung,syscon-csis = <&sysreg_cam 0x40c>;
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+				};
+
+				port@1 {
+					reg = <1>;
+
+					mipi_csis_4_out: endpoint {
+						remote-endpoint = <&csis_in_4>;
+					};
+				};
+			};
+		};
+
+		csis4: csis@12681000 {
+			compatible = "tesla,fsd-csis-media";
+			reg = <0x0 0x12681000 0x0 0x44c>;
+			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clock_csi CAM_CSI1_0_IPCLKPORT_I_ACLK>,
+				<&clock_csi CAM_CSI1_0_IPCLKPORT_I_PCLK>,
+				<&clock_csi CAM_CSI_PLL>;
+			clock-names = "aclk", "pclk", "pll";
+			iommus = <&smmu_isp 0x0 0x0>;
+			status = "disabled";
+
+			port {
+				csis_in_4: endpoint {
+					remote-endpoint = <&mipi_csis_4_out>;
+				};
+			};
+		};
+
+		mipicsis5: mipi-csis@12690000 {
+			compatible = "tesla,fsd-mipi-csi2";
+			reg = <0x0 0x12690000 0x0 0x124>;
+			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clock_csi CAM_CSI1_1_IPCLKPORT_I_ACLK>,
+				<&clock_csi CAM_CSI1_1_IPCLKPORT_I_PCLK>;
+			clock-names = "aclk", "pclk";
+			samsung,syscon-csis = <&sysreg_cam 0x40c>;
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+				};
+
+				port@1 {
+					reg = <1>;
+
+					mipi_csis_5_out: endpoint {
+						remote-endpoint = <&csis_in_5>;
+					};
+				};
+			};
+		};
+
+		csis5: csis@12691000 {
+			compatible = "tesla,fsd-csis-media";
+			reg = <0x0 0x12691000 0x0 0x44c>;
+			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clock_csi CAM_CSI1_1_IPCLKPORT_I_ACLK>,
+				<&clock_csi CAM_CSI1_1_IPCLKPORT_I_PCLK>,
+				<&clock_csi CAM_CSI_PLL>;
+			clock-names = "aclk", "pclk", "pll";
+			iommus = <&smmu_isp 0x0 0x0>;
+			status = "disabled";
+
+			port {
+				csis_in_5: endpoint {
+					remote-endpoint = <&mipi_csis_5_out>;
+				};
+			};
+		};
+
+		mipicsis6: mipi-csis@126a0000 {
+			compatible = "tesla,fsd-mipi-csi2";
+			reg = <0x0 0x126a0000 0x0 0x124>;
+			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clock_csi CAM_CSI1_2_IPCLKPORT_I_ACLK>,
+				<&clock_csi CAM_CSI1_2_IPCLKPORT_I_PCLK>;
+			clock-names = "aclk", "pclk";
+			samsung,syscon-csis = <&sysreg_cam 0x40c>;
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+				};
+
+				port@1 {
+					reg = <1>;
+
+					mipi_csis_6_out: endpoint {
+						remote-endpoint = <&csis_in_6>;
+					};
+				};
+			};
+		};
+
+		csis6: csis@126a1000 {
+			compatible = "tesla,fsd-csis-media";
+			reg = <0x0 0x126a1000 0x0 0x44c>;
+			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clock_csi CAM_CSI1_2_IPCLKPORT_I_ACLK>,
+				<&clock_csi CAM_CSI1_2_IPCLKPORT_I_PCLK>,
+				<&clock_csi CAM_CSI_PLL>;
+			clock-names = "aclk", "pclk", "pll";
+			iommus = <&smmu_isp 0x0 0x0>;
+			status = "disabled";
+
+			port {
+				csis_in_6: endpoint {
+					remote-endpoint = <&mipi_csis_6_out>;
+				};
+			};
+		};
+
+		mipicsis7: mipi-csis@126b0000 {
+			compatible = "tesla,fsd-mipi-csi2";
+			reg = <0x0 0x126b0000 0x0 0x124>;
+			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clock_csi CAM_CSI1_3_IPCLKPORT_I_ACLK>,
+				<&clock_csi CAM_CSI1_3_IPCLKPORT_I_PCLK>;
+			clock-names = "aclk", "pclk";
+			samsung,syscon-csis = <&sysreg_cam 0x40c>;
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+				};
+
+				port@1 {
+					reg = <1>;
+
+					mipi_csis_7_out: endpoint {
+						remote-endpoint = <&csis_in_7>;
+					};
+				};
+			};
+		};
+
+		csis7: csis@126b1000 {
+			compatible = "tesla,fsd-csis-media";
+			reg = <0x0 0x126b1000 0x0 0x44c>;
+			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clock_csi CAM_CSI1_3_IPCLKPORT_I_ACLK>,
+				<&clock_csi CAM_CSI1_3_IPCLKPORT_I_PCLK>,
+				<&clock_csi CAM_CSI_PLL>;
+			clock-names = "aclk", "pclk", "pll";
+			iommus = <&smmu_isp 0x0 0x0>;
+			status = "disabled";
+
+			port {
+				csis_in_7: endpoint {
+					remote-endpoint = <&mipi_csis_7_out>;
+				};
+			};
+		};
+
+		mipicsis8: mipi-csis@126c0000 {
+			compatible = "tesla,fsd-mipi-csi2";
+			reg = <0x0 0x126c0000 0x0 0x124>;
+			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clock_csi CAM_CSI2_0_IPCLKPORT_I_ACLK>,
+				<&clock_csi CAM_CSI2_0_IPCLKPORT_I_PCLK>;
+			clock-names = "aclk", "pclk";
+			samsung,syscon-csis = <&sysreg_cam 0x40c>;
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+				};
+
+				port@1 {
+					reg = <1>;
+
+					mipi_csis_8_out: endpoint {
+						remote-endpoint = <&csis_in_8>;
+					};
+				};
+			};
+		};
+
+		csis8: csis@126c1000 {
+			compatible = "tesla,fsd-csis-media";
+			reg = <0x0 0x126c1000 0x0 0x44c>;
+			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clock_csi CAM_CSI2_0_IPCLKPORT_I_ACLK>,
+				<&clock_csi CAM_CSI2_0_IPCLKPORT_I_PCLK>,
+				<&clock_csi CAM_CSI_PLL>;
+			clock-names = "aclk", "pclk", "pll";
+			iommus = <&smmu_isp 0x0 0x0>;
+			status = "disabled";
+
+			port {
+				csis_in_8: endpoint {
+					remote-endpoint = <&mipi_csis_8_out>;
+				};
+			};
+		};
+
+		mipicsis9: mipi-csis@126d0000 {
+			compatible = "tesla,fsd-mipi-csi2";
+			reg = <0x0 0x126d0000 0x0 0x124>;
+			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clock_csi CAM_CSI2_1_IPCLKPORT_I_ACLK>,
+				<&clock_csi CAM_CSI2_1_IPCLKPORT_I_PCLK>;
+			clock-names = "aclk", "pclk";
+			samsung,syscon-csis = <&sysreg_cam 0x40c>;
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+				};
+
+				port@1 {
+					reg = <1>;
+
+					mipi_csis_9_out: endpoint {
+						remote-endpoint = <&csis_in_9>;
+					};
+				};
+			};
+		};
+
+		csis9: csis@126d1000 {
+			compatible = "tesla,fsd-csis-media";
+			reg = <0x0 0x126d1000 0x0 0x44c>;
+			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clock_csi CAM_CSI2_1_IPCLKPORT_I_ACLK>,
+				<&clock_csi CAM_CSI2_1_IPCLKPORT_I_PCLK>,
+				<&clock_csi CAM_CSI_PLL>;
+			clock-names = "aclk", "pclk", "pll";
+			iommus = <&smmu_isp 0x0 0x0>;
+			status = "disabled";
+
+			port {
+				csis_in_9: endpoint {
+					remote-endpoint = <&mipi_csis_9_out>;
+				};
+			};
+		};
+
+		mipicsis10: mipi-csis@126e0000 {
+			compatible = "tesla,fsd-mipi-csi2";
+			reg = <0x0 0x126e0000 0x0 0x124>;
+			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clock_csi CAM_CSI2_2_IPCLKPORT_I_ACLK>,
+				<&clock_csi CAM_CSI2_2_IPCLKPORT_I_PCLK>;
+			clock-names = "aclk", "pclk";
+			samsung,syscon-csis = <&sysreg_cam 0x40c>;
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+				};
+
+				port@1 {
+					reg = <1>;
+
+					mipi_csis_10_out: endpoint {
+						remote-endpoint = <&csis_in_10>;
+					};
+				};
+			};
+		};
+
+		csis10: csis@126e1000 {
+			compatible = "tesla,fsd-csis-media";
+			reg = <0x0 0x126e1000 0x0 0x44c>;
+			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clock_csi CAM_CSI2_2_IPCLKPORT_I_ACLK>,
+				<&clock_csi CAM_CSI2_2_IPCLKPORT_I_PCLK>,
+				<&clock_csi CAM_CSI_PLL>;
+			clock-names = "aclk", "pclk", "pll";
+			iommus = <&smmu_isp 0x0 0x0>;
+			status = "disabled";
+
+			port {
+				csis_in_10: endpoint {
+					remote-endpoint = <&mipi_csis_10_out>;
+				};
+			};
+		};
+
+		mipicsis11: mipi-csis@126f0000 {
+			compatible = "tesla,fsd-mipi-csi2";
+			reg = <0x0 0x126f0000 0x0 0x124>;
+			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clock_csi CAM_CSI2_3_IPCLKPORT_I_ACLK>,
+				<&clock_csi CAM_CSI2_3_IPCLKPORT_I_PCLK>;
+			clock-names = "aclk", "pclk";
+			samsung,syscon-csis = <&sysreg_cam 0x40c>;
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+				};
+
+				port@1 {
+					reg = <1>;
+
+					mipi_csis_11_out: endpoint {
+						remote-endpoint = <&csis_in_11>;
+					};
+				};
+			};
+		};
+
+		csis11: csis@126f1000 {
+			compatible = "tesla,fsd-csis-media";
+			reg = <0x0 0x126f1000 0x0 0x44c>;
+			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clock_csi CAM_CSI2_3_IPCLKPORT_I_ACLK>,
+				<&clock_csi CAM_CSI2_3_IPCLKPORT_I_PCLK>,
+				<&clock_csi CAM_CSI_PLL>;
+			clock-names = "aclk", "pclk", "pll";
+			iommus = <&smmu_isp 0x0 0x0>;
+			status = "disabled";
+
+			port {
+				csis_in_11: endpoint {
+					remote-endpoint = <&mipi_csis_11_out>;
+				};
+			};
+		};
+
 		clock_peric: clock-controller@14010000 {
 			compatible = "tesla,fsd-clock-peric";
 			reg = <0x0 0x14010000 0x0 0x3000>;
-- 
2.49.0

Re: [PATCH v2 04/12] arm64: dts: fsd: Add CSI nodes

[Krzysztof Kozlowski]

On 14/08/2025 16:09, Inbaraj E wrote:
> There is a csi dma and csis interface that bundles together to allow

CSI DMA?
What is CSIS?

> csi2 capture.

CSI2?

> 
> Signed-off-by: Inbaraj E <inbaraj.e@samsung.com>
> ---
>  arch/arm64/boot/dts/tesla/fsd-evb.dts |  96 +++++
>  arch/arm64/boot/dts/tesla/fsd.dtsi    | 552 ++++++++++++++++++++++++++
>  2 files changed, 648 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/tesla/fsd-evb.dts b/arch/arm64/boot/dts/tesla/fsd-evb.dts
> index 9ff22e1c8723..dcc9a138cdb9 100644
> --- a/arch/arm64/boot/dts/tesla/fsd-evb.dts
> +++ b/arch/arm64/boot/dts/tesla/fsd-evb.dts
> @@ -130,3 +130,99 @@ &serial_0 {
>  &ufs {
>  	status = "okay";
>  };
> +
> +&mipicsis0 {
> +	status = "okay";
> +};
> +
> +&mipicsis1 {
> +	status = "okay";
> +};
> +
> +&mipicsis2 {
> +	status = "okay";
> +};
> +
> +&mipicsis3 {
> +	status = "okay";
> +};
> +
> +&mipicsis4 {
> +	status = "okay";
> +};
> +
> +&mipicsis5 {
> +	status = "okay";
> +};
> +
> +&mipicsis6 {
> +	status = "okay";
> +};
> +
> +&mipicsis7 {
> +	status = "okay";
> +};
> +
> +&mipicsis8 {
> +	status = "okay";
> +};
> +
> +&mipicsis9 {
> +	status = "okay";
> +};
> +
> +&mipicsis10 {
> +	status = "okay";
> +};
> +
> +&mipicsis11 {
> +	status = "okay";
> +};
> +
> +&csis0 {
> +	status = "okay";
> +};
> +
> +&csis1 {
> +	status = "okay";
> +};
> +
> +&csis2 {
> +	status = "okay";
> +};
> +
> +&csis3 {
> +	status = "okay";
> +};
> +
> +&csis4 {
> +	status = "okay";
> +};
> +
> +&csis5 {
> +	status = "okay";
> +};
> +
> +&csis6 {
> +	status = "okay";
> +};
> +
> +&csis7 {
> +	status = "okay";
> +};
> +
> +&csis8 {
> +	status = "okay";
> +};
> +
> +&csis9 {
> +	status = "okay";
> +};
> +
> +&csis10 {
> +	status = "okay";
> +};
> +
> +&csis11 {
> +	status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi
> index a5ebb3f9b18f..a83503e9c502 100644
> --- a/arch/arm64/boot/dts/tesla/fsd.dtsi
> +++ b/arch/arm64/boot/dts/tesla/fsd.dtsi
> @@ -493,6 +493,558 @@ clock_mfc: clock-controller@12810000 {
>  			clock-names = "fin_pll";
>  		};
>  
> +		mipicsis0: mipi-csis@12640000 {

Messed ordering. See DTS coding style.

Node names should be generic. See also an explanation and list of
examples (not exhaustive) in DT specification:
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation

What is csis?

> +			compatible = "tesla,fsd-mipi-csi2";
> +			reg = <0x0 0x12640000 0x0 0x124>;
> +			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&clock_csi CAM_CSI0_0_IPCLKPORT_I_ACLK>,
> +				<&clock_csi CAM_CSI0_0_IPCLKPORT_I_PCLK>;
> +			clock-names = "aclk", "pclk";
> +			samsung,syscon-csis = <&sysreg_cam 0x40c>;
> +			status = "disabled";
> +
> +			ports {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				port@0 {
> +					reg = <0>;
> +				};
> +
> +				port@1 {
> +					reg = <1>;
> +
> +					mipi_csis_0_out: endpoint {
> +						remote-endpoint = <&csis_in_0>;
> +					};
> +				};
> +			};
> +		};
> +
> +		csis0: csis@12641000 {
> +			compatible = "tesla,fsd-csis-media";
> +			reg = <0x0 0x12641000 0x0 0x44c>;
> +			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&clock_csi CAM_CSI0_0_IPCLKPORT_I_ACLK>,
> +				<&clock_csi CAM_CSI0_0_IPCLKPORT_I_PCLK>,
> +				<&clock_csi CAM_CSI_PLL>;
> +			clock-names = "aclk", "pclk", "pll";
> +			iommus = <&smmu_isp 0x0 0x0>;
> +			status = "disabled";
> +
> +			port {
> +				csis_in_0: endpoint {
> +					remote-endpoint = <&mipi_csis_0_out>;
> +				};
> +			};
> +		};
> +
> +		mipicsis1: mipi-csis@12650000 {
> +			compatible = "tesla,fsd-mipi-csi2";
> +			reg = <0x0 0x12650000 0x0 0x124>;
> +			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&clock_csi CAM_CSI0_1_IPCLKPORT_I_ACLK>,
> +				<&clock_csi CAM_CSI0_1_IPCLKPORT_I_PCLK>;
> +			clock-names = "aclk", "pclk";
> +			samsung,syscon-csis = <&sysreg_cam 0x40c>;
> +			status = "disabled";
> +
> +			ports {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				port@0 {
> +					reg = <0>;
> +				};
> +
> +				port@1 {
> +					reg = <1>;
> +
> +					mipi_csis_1_out: endpoint {
> +						remote-endpoint = <&csis_in_1>;
> +					};
> +				};
> +			};
> +		};
> +
> +		csis1: csis@12651000 {
> +			compatible = "tesla,fsd-csis-media";
> +			reg = <0x0 0x12651000 0x0 0x44c>;
> +			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&clock_csi CAM_CSI0_1_IPCLKPORT_I_ACLK>,
> +				<&clock_csi CAM_CSI0_1_IPCLKPORT_I_PCLK>,
> +				<&clock_csi CAM_CSI_PLL>;
> +			clock-names = "aclk", "pclk", "pll";
> +			iommus = <&smmu_isp 0x0 0x0>;
> +			status = "disabled";
> +
> +			port {
> +				csis_in_1: endpoint {
> +					remote-endpoint = <&mipi_csis_1_out>;
> +				};
> +			};
> +		};
> +
> +		mipicsis2: mipi-csis@12660000 {
> +			compatible = "tesla,fsd-mipi-csi2";
> +			reg = <0x0 0x12660000 0x0 0x124>;
> +			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&clock_csi CAM_CSI0_2_IPCLKPORT_I_ACLK>,
> +				<&clock_csi CAM_CSI0_2_IPCLKPORT_I_PCLK>;
> +			clock-names = "aclk", "pclk";
> +			samsung,syscon-csis = <&sysreg_cam 0x40c>;
> +			status = "disabled";
> +
> +			ports {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				port@0 {
> +					reg = <0>;
> +				};
> +
> +				port@1 {
> +					reg = <1>;
> +
> +					mipi_csis_2_out: endpoint {
> +						remote-endpoint = <&csis_in_2>;
> +					};
> +				};
> +			};
> +		};
> +
> +		csis2: csis@12661000 {


What is CSIS? Seems like copy paste from other Samsung code, but isn't
this just CSI?

What is the meaning of this CSIS acronym?


Best regards,
Krzysztof

RE: [PATCH v2 04/12] arm64: dts: fsd: Add CSI nodes

[Inbaraj E]

Hi Krzysztof,

Thanks for the review.

> 
> On 14/08/2025 16:09, Inbaraj E wrote:
> > There is a csi dma and csis interface that bundles together to allow
> 
> CSI DMA?
> What is CSIS?
> 
> > csi2 capture.
> 
> CSI2?

CSIS stands for Camera Serial Interface Slave.

Samsung v4.3 CSIS IP bundles both the CSIS link operation and the CSIS
DMA operation. The DMA-related operation are referred to as CSIS DMA and
are handled by the fsd-csis driver. The link related operations are
referred to simply as CSIS and are integrated into imx-mipi-csis driver.

I'll update the commit message and commit description accordingly,
and maintain consistency across the patches.

> 
> >
> > Signed-off-by: Inbaraj E <inbaraj.e@samsung.com>
> > ---
> >  arch/arm64/boot/dts/tesla/fsd-evb.dts |  96 +++++
> > +++ b/arch/arm64/boot/dts/tesla/fsd.dtsi
> > @@ -493,6 +493,558 @@ clock_mfc: clock-controller@12810000 {
> >  			clock-names = "fin_pll";
> >  		};
> >
> > +		mipicsis0: mipi-csis@12640000 {
> 
> Messed ordering. See DTS coding style.

I'll fix the ordering in next patchset.

> 
> Node names should be generic. See also an explanation and list of examples
> (not exhaustive) in DT specification:
> https://protect2.fireeye.com/v1/url?k=a30d23f8-c28636dd-a30ca8b7-
> 74fe485cbff6-ee12f8a711c584c8&q=1&e=b96506d8-2d5d-4303-b9e8-
> 0e1189db1585&u=https%3A%2F%2Fdevicetree-
> specification.readthedocs.io%2Fen%2Flatest%2Fchapter2-devicetree-
> basics.html%23generic-names-recommendation
> 

There is no generic name directly related to CSI apart from camera. That's
why I used mipi-csis. If preferred, I can move the name to csis or simply csi.
Please let me know which one is more appropriate.

Regards,
Inbaraj E

Re: [PATCH v2 04/12] arm64: dts: fsd: Add CSI nodes

[Krzysztof Kozlowski]

On 22/08/2025 15:57, Inbaraj E wrote:
> 
> Hi Krzysztof,
> 
> Thanks for the review.
> 
>>
>> On 14/08/2025 16:09, Inbaraj E wrote:
>>> There is a csi dma and csis interface that bundles together to allow
>>
>> CSI DMA?
>> What is CSIS?
>>
>>> csi2 capture.
>>
>> CSI2?
> 
> CSIS stands for Camera Serial Interface Slave.

Googling for "MIPI CSIS" gives me 0 results, so I still claim this is
not a generic name.

> 
> Samsung v4.3 CSIS IP bundles both the CSIS link operation and the CSIS
> DMA operation. The DMA-related operation are referred to as CSIS DMA and
> are handled by the fsd-csis driver. The link related operations are
> referred to simply as CSIS and are integrated into imx-mipi-csis driver.
> 
> I'll update the commit message and commit description accordingly,
> and maintain consistency across the patches.
> 
>>
>>>
>>> Signed-off-by: Inbaraj E <inbaraj.e@samsung.com>
>>> ---
>>>  arch/arm64/boot/dts/tesla/fsd-evb.dts |  96 +++++
>>> +++ b/arch/arm64/boot/dts/tesla/fsd.dtsi
>>> @@ -493,6 +493,558 @@ clock_mfc: clock-controller@12810000 {
>>>  			clock-names = "fin_pll";
>>>  		};
>>>
>>> +		mipicsis0: mipi-csis@12640000 {
>>
>> Messed ordering. See DTS coding style.
> 
> I'll fix the ordering in next patchset.
> 
>>
>> Node names should be generic. See also an explanation and list of examples
>> (not exhaustive) in DT specification:
>> https://protect2.fireeye.com/v1/url?k=a30d23f8-c28636dd-a30ca8b7-
>> 74fe485cbff6-ee12f8a711c584c8&q=1&e=b96506d8-2d5d-4303-b9e8-
>> 0e1189db1585&u=https%3A%2F%2Fdevicetree-
>> specification.readthedocs.io%2Fen%2Flatest%2Fchapter2-devicetree-
>> basics.html%23generic-names-recommendation
>>
> 
> There is no generic name directly related to CSI apart from camera. That's
> why I used mipi-csis. If preferred, I can move the name to csis or simply csi.
> Please let me know which one is more appropriate.

I don't think you really tried to solve this. How this device is called
in all other vendors?

Best regards,
Krzysztof

RE: [PATCH v2 04/12] arm64: dts: fsd: Add CSI nodes

[Inbaraj E]

Hi Krzysztof,

> >
> > CSIS stands for Camera Serial Interface Slave.
> 
> Googling for "MIPI CSIS" gives me 0 results, so I still claim this is not a generic
> name.

I checked other vendors (e.g: freescale), and they are using mipi-csi. I'll adopt for the
same.

> 
> >

Regards,
Inbaraj E

Re: [PATCH v2 04/12] arm64: dts: fsd: Add CSI nodes

[Krzysztof Kozlowski]

On 25/08/2025 15:05, Inbaraj E wrote:
> Hi Krzysztof,
> 
>>>
>>> CSIS stands for Camera Serial Interface Slave.
>>
>> Googling for "MIPI CSIS" gives me 0 results, so I still claim this is not a generic
>> name.
> 
> I checked other vendors (e.g: freescale), and they are using mipi-csi. I'll adopt for the
> same.
> 
>

Then it is just "csi"? Except that you have some other different nodes
called "csi" as well, so two different devices are "csi"?

Best regards,
Krzysztof

RE: [PATCH v2 04/12] arm64: dts: fsd: Add CSI nodes

[Inbaraj E]

Hi Krzysztof,


 >> Googling for "MIPI CSIS" gives me 0 results, so I still claim this is
> >> not a generic name.
> >
> > I checked other vendors (e.g: freescale), and they are using mipi-csi.
> > I'll adopt for the same.
> >
> >
> 
> Then it is just "csi"? 

For the CSIS MIPI CSI-2 Rx handled by imx-mipi-csis driver, I'll keep node name as "csi"

>Except that you have some other different nodes called
> "csi" as well, so two different devices are "csi"?

For CSIS video capture interface which is handled by fsd-csis driver I'll keep node
name as "csis".
 If "csis " and "csi" is kind of confusing in the same dt, then I'll keep
as "video".

is it fine?

Regards,
Inbaraj E

Re: [PATCH v2 04/12] arm64: dts: fsd: Add CSI nodes

[Laurent Pinchart]

On Tue, Aug 26, 2025 at 10:36:50AM +0200, Krzysztof Kozlowski wrote:
> On 25/08/2025 15:05, Inbaraj E wrote:
> > Hi Krzysztof,
> > 
> >>> CSIS stands for Camera Serial Interface Slave.
> >>
> >> Googling for "MIPI CSIS" gives me 0 results, so I still claim this is not a generic
> >> name.
> > 
> > I checked other vendors (e.g: freescale), and they are using mipi-csi. I'll adopt for the
> > same.
> 
> Then it is just "csi"? Except that you have some other different nodes
> called "csi" as well, so two different devices are "csi"?

This one is high on my list of unfortunate name clashes. Many NXP SoCs
(among others, I've seen that in other vendors too) have IP cores named
"Camera Sensor Interface" that they abbreviate to "CSI". They are
unrelated to the MIPI Camera Serial Interface. I won't blame NXP, as I
think they may have started using the acronym before MIPI CSI became a
big thing.

-- 
Regards,

Laurent Pinchart

[PATCH v2 05/12] media: imx-mipi-csis: Move clk to mipi_csis_info structure

[Inbaraj E]

clock names in NXP SoC's is different from the FSD SoC. Inorder to
extend this driver to use for FSD SoC. Move the clock names to
mipi_csis_info structure.

Signed-off-by: Inbaraj E <inbaraj.e@samsung.com>
---
 drivers/media/platform/nxp/imx-mipi-csis.c | 14 ++++++--------
 1 file changed, 6 insertions(+), 8 deletions(-)

diff --git a/drivers/media/platform/nxp/imx-mipi-csis.c b/drivers/media/platform/nxp/imx-mipi-csis.c
index 2beb5f43c2c0..4afa75734f05 100644
--- a/drivers/media/platform/nxp/imx-mipi-csis.c
+++ b/drivers/media/platform/nxp/imx-mipi-csis.c
@@ -267,6 +267,8 @@ static const struct mipi_csis_event mipi_csis_events[] = {
 
 #define MIPI_CSIS_NUM_EVENTS ARRAY_SIZE(mipi_csis_events)
 
+#define MIPI_CSIS_MAX_CLOCKS	4
+
 enum mipi_csis_clk {
 	MIPI_CSIS_CLK_PCLK,
 	MIPI_CSIS_CLK_WRAP,
@@ -274,13 +276,6 @@ enum mipi_csis_clk {
 	MIPI_CSIS_CLK_AXI,
 };
 
-static const char * const mipi_csis_clk_id[] = {
-	"pclk",
-	"wrap",
-	"phy",
-	"axi",
-};
-
 enum mipi_csis_version {
 	MIPI_CSIS_V3_3,
 	MIPI_CSIS_V3_6_3,
@@ -289,6 +284,7 @@ enum mipi_csis_version {
 struct mipi_csis_info {
 	enum mipi_csis_version version;
 	unsigned int num_clocks;
+	const char *clk_names[MIPI_CSIS_MAX_CLOCKS];
 };
 
 struct mipi_csis_device {
@@ -697,7 +693,7 @@ static int mipi_csis_clk_get(struct mipi_csis_device *csis)
 		return -ENOMEM;
 
 	for (i = 0; i < csis->info->num_clocks; i++)
-		csis->clks[i].id = mipi_csis_clk_id[i];
+		csis->clks[i].id = csis->info->clk_names[i];
 
 	ret = devm_clk_bulk_get(csis->dev, csis->info->num_clocks,
 				csis->clks);
@@ -1539,12 +1535,14 @@ static const struct of_device_id mipi_csis_of_match[] = {
 		.data = &(const struct mipi_csis_info){
 			.version = MIPI_CSIS_V3_3,
 			.num_clocks = 3,
+			.clk_names = {"pclk", "wrap", "phy"},
 		},
 	}, {
 		.compatible = "fsl,imx8mm-mipi-csi2",
 		.data = &(const struct mipi_csis_info){
 			.version = MIPI_CSIS_V3_6_3,
 			.num_clocks = 4,
+			.clk_names = {"pclk", "wrap", "phy", "axi"},
 		},
 	},
 	{ /* sentinel */ },
-- 
2.49.0

Re: [PATCH v2 05/12] media: imx-mipi-csis: Move clk to mipi_csis_info structure

[Laurent Pinchart]

Hi Inbaraj,

On Thu, Aug 14, 2025 at 07:39:36PM +0530, Inbaraj E wrote:
> clock names in NXP SoC's is different from the FSD SoC. Inorder to

s/clock/Clock/
s/Inorder/In order/

Is the difference really a matter of SoCs, or is it because the FSD SoC
uses a different version of the IP ?

I also suspect that the "phy" clock was added by mistake, and isn't
needed in NXP SoCs. Could you please check and confirm if the v3.3 and
v3.6.3 versions of the IP have an input PHY clock ?

> extend this driver to use for FSD SoC. Move the clock names to
> mipi_csis_info structure.
> 
> Signed-off-by: Inbaraj E <inbaraj.e@samsung.com>
> ---
>  drivers/media/platform/nxp/imx-mipi-csis.c | 14 ++++++--------
>  1 file changed, 6 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/media/platform/nxp/imx-mipi-csis.c b/drivers/media/platform/nxp/imx-mipi-csis.c
> index 2beb5f43c2c0..4afa75734f05 100644
> --- a/drivers/media/platform/nxp/imx-mipi-csis.c
> +++ b/drivers/media/platform/nxp/imx-mipi-csis.c
> @@ -267,6 +267,8 @@ static const struct mipi_csis_event mipi_csis_events[] = {
>  
>  #define MIPI_CSIS_NUM_EVENTS ARRAY_SIZE(mipi_csis_events)
>  
> +#define MIPI_CSIS_MAX_CLOCKS	4
> +
>  enum mipi_csis_clk {
>  	MIPI_CSIS_CLK_PCLK,
>  	MIPI_CSIS_CLK_WRAP,
> @@ -274,13 +276,6 @@ enum mipi_csis_clk {
>  	MIPI_CSIS_CLK_AXI,
>  };
>  
> -static const char * const mipi_csis_clk_id[] = {
> -	"pclk",
> -	"wrap",
> -	"phy",
> -	"axi",
> -};
> -
>  enum mipi_csis_version {
>  	MIPI_CSIS_V3_3,
>  	MIPI_CSIS_V3_6_3,
> @@ -289,6 +284,7 @@ enum mipi_csis_version {
>  struct mipi_csis_info {
>  	enum mipi_csis_version version;
>  	unsigned int num_clocks;
> +	const char *clk_names[MIPI_CSIS_MAX_CLOCKS];
>  };
>  
>  struct mipi_csis_device {
> @@ -697,7 +693,7 @@ static int mipi_csis_clk_get(struct mipi_csis_device *csis)
>  		return -ENOMEM;
>  
>  	for (i = 0; i < csis->info->num_clocks; i++)
> -		csis->clks[i].id = mipi_csis_clk_id[i];
> +		csis->clks[i].id = csis->info->clk_names[i];
>  
>  	ret = devm_clk_bulk_get(csis->dev, csis->info->num_clocks,
>  				csis->clks);
> @@ -1539,12 +1535,14 @@ static const struct of_device_id mipi_csis_of_match[] = {
>  		.data = &(const struct mipi_csis_info){
>  			.version = MIPI_CSIS_V3_3,
>  			.num_clocks = 3,
> +			.clk_names = {"pclk", "wrap", "phy"},
>  		},
>  	}, {
>  		.compatible = "fsl,imx8mm-mipi-csi2",
>  		.data = &(const struct mipi_csis_info){
>  			.version = MIPI_CSIS_V3_6_3,
>  			.num_clocks = 4,
> +			.clk_names = {"pclk", "wrap", "phy", "axi"},
>  		},
>  	},
>  	{ /* sentinel */ },

-- 
Regards,

Laurent Pinchart

RE: [PATCH v2 05/12] media: imx-mipi-csis: Move clk to mipi_csis_info structure

[Inbaraj E]

Hi Laurent,

Thanks for the review.

> 
> On Thu, Aug 14, 2025 at 07:39:36PM +0530, Inbaraj E wrote:
> > clock names in NXP SoC's is different from the FSD SoC. Inorder to
> 
> s/clock/Clock/
> s/Inorder/In order/
> 
I'll change in next patchset.

> Is the difference really a matter of SoCs, or is it because the FSD SoC uses a
> different version of the IP ?
> 

Yes, it is dependent on the version of the IP.  Thanks for pointing it out. I'll update commit
description accordingly.

> I also suspect that the "phy" clock was added by mistake, and isn't needed in
> NXP SoCs. Could you please check and confirm if the v3.3 and
> v3.6.3 versions of the IP have an input PHY clock ?

I don't have manuals for v3.3 and v3.6.3, So I cannot confirm  this. 

> 
> > extend this driver to use for FSD SoC. Move the clock names to
> > mipi_csis_info structure.
> >

Regards,
Inbaraj E

[PATCH v2 06/12] media: imx-mipi-csis: Move irq flag and handler to mipi_csis_info structure

[Inbaraj E]

FSD CSI IP has only one IRQ line, shared between imx-mipi-csis and
fsd-csi-media drivers. To extend this driver for FSD SoC support,
move the IRQ flag and IRQ handler to the device data(structure
mipi_csis_info).

Signed-off-by: Inbaraj E <inbaraj.e@samsung.com>
---
 drivers/media/platform/nxp/imx-mipi-csis.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/media/platform/nxp/imx-mipi-csis.c b/drivers/media/platform/nxp/imx-mipi-csis.c
index 4afa75734f05..a3e2c8ae332f 100644
--- a/drivers/media/platform/nxp/imx-mipi-csis.c
+++ b/drivers/media/platform/nxp/imx-mipi-csis.c
@@ -285,6 +285,8 @@ struct mipi_csis_info {
 	enum mipi_csis_version version;
 	unsigned int num_clocks;
 	const char *clk_names[MIPI_CSIS_MAX_CLOCKS];
+	unsigned int irq_flag;
+	irq_handler_t irq_handler;
 };
 
 struct mipi_csis_device {
@@ -1462,7 +1464,7 @@ static int mipi_csis_probe(struct platform_device *pdev)
 	mipi_csis_phy_reset(csis);
 
 	/* Now that the hardware is initialized, request the interrupt. */
-	ret = devm_request_irq(dev, irq, mipi_csis_irq_handler, 0,
+	ret = devm_request_irq(dev, irq, csis->info->irq_handler, csis->info->irq_flag,
 			       dev_name(dev), csis);
 	if (ret) {
 		dev_err(dev, "Interrupt request failed\n");
@@ -1536,6 +1538,8 @@ static const struct of_device_id mipi_csis_of_match[] = {
 			.version = MIPI_CSIS_V3_3,
 			.num_clocks = 3,
 			.clk_names = {"pclk", "wrap", "phy"},
+			.irq_flag = 0,
+			.irq_handler = mipi_csis_irq_handler,
 		},
 	}, {
 		.compatible = "fsl,imx8mm-mipi-csi2",
@@ -1543,6 +1547,8 @@ static const struct of_device_id mipi_csis_of_match[] = {
 			.version = MIPI_CSIS_V3_6_3,
 			.num_clocks = 4,
 			.clk_names = {"pclk", "wrap", "phy", "axi"},
+			.irq_flag = 0,
+			.irq_handler = mipi_csis_irq_handler,
 		},
 	},
 	{ /* sentinel */ },
-- 
2.49.0

[PATCH v2 07/12] media: imx-mipi-csis: Add support to configure specific vc

[Inbaraj E]

MIPI_CSIS_V3_3 and MIPI_CSIS_V3_6_3 support streaming only on VC0. The
MIPI_CSIS_V4_3 present in the FSD SoC supports streaming on any one VC
out of four VCs. To extend support for the FSD SoC, add the ability to
configure a specific VC. The FSD CSI Rx can configure any one VC and
start streaming.

Signed-off-by: Inbaraj E <inbaraj.e@samsung.com>
---
 drivers/media/platform/nxp/imx-mipi-csis.c | 17 +++++++++++------
 1 file changed, 11 insertions(+), 6 deletions(-)

diff --git a/drivers/media/platform/nxp/imx-mipi-csis.c b/drivers/media/platform/nxp/imx-mipi-csis.c
index a3e2c8ae332f..4f6c417fdf58 100644
--- a/drivers/media/platform/nxp/imx-mipi-csis.c
+++ b/drivers/media/platform/nxp/imx-mipi-csis.c
@@ -54,7 +54,7 @@
 
 /* CSIS common control */
 #define MIPI_CSIS_CMN_CTRL			0x04
-#define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW	BIT(16)
+#define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW(n)	BIT(((n) + 16))
 #define MIPI_CSIS_CMN_CTRL_INTER_MODE		BIT(10)
 #define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL	BIT(2)
 #define MIPI_CSIS_CMN_CTRL_RESET		BIT(1)
@@ -319,6 +319,7 @@ struct mipi_csis_device {
 		u32 hs_settle;
 		u32 clk_settle;
 	} debug;
+	unsigned int vc;
 };
 
 /* -----------------------------------------------------------------------------
@@ -544,9 +545,10 @@ static void __mipi_csis_set_format(struct mipi_csis_device *csis,
 				   const struct csis_pix_format *csis_fmt)
 {
 	u32 val;
+	unsigned int vc = csis->vc;
 
 	/* Color format */
-	val = mipi_csis_read(csis, MIPI_CSIS_ISP_CONFIG_CH(0));
+	val = mipi_csis_read(csis, MIPI_CSIS_ISP_CONFIG_CH(vc));
 	val &= ~(MIPI_CSIS_ISPCFG_ALIGN_32BIT | MIPI_CSIS_ISPCFG_FMT_MASK
 		| MIPI_CSIS_ISPCFG_PIXEL_MASK);
 
@@ -567,11 +569,11 @@ static void __mipi_csis_set_format(struct mipi_csis_device *csis,
 		val |= MIPI_CSIS_ISPCFG_PIXEL_MODE_DUAL;
 
 	val |= MIPI_CSIS_ISPCFG_FMT(csis_fmt->data_type);
-	mipi_csis_write(csis, MIPI_CSIS_ISP_CONFIG_CH(0), val);
+	mipi_csis_write(csis, MIPI_CSIS_ISP_CONFIG_CH(vc), val);
 
 	/* Pixel resolution */
 	val = format->width | (format->height << 16);
-	mipi_csis_write(csis, MIPI_CSIS_ISP_RESOL_CH(0), val);
+	mipi_csis_write(csis, MIPI_CSIS_ISP_RESOL_CH(vc), val);
 }
 
 static int mipi_csis_calculate_params(struct mipi_csis_device *csis,
@@ -631,6 +633,7 @@ static void mipi_csis_set_params(struct mipi_csis_device *csis,
 {
 	int lanes = csis->bus.num_data_lanes;
 	u32 val;
+	unsigned int vc = csis->vc;
 
 	val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL);
 	val &= ~MIPI_CSIS_CMN_CTRL_LANE_NR_MASK;
@@ -648,7 +651,7 @@ static void mipi_csis_set_params(struct mipi_csis_device *csis,
 	val = (0 << MIPI_CSIS_ISP_SYNC_HSYNC_LINTV_OFFSET)
 	    | (0 << MIPI_CSIS_ISP_SYNC_VSYNC_SINTV_OFFSET)
 	    | (0 << MIPI_CSIS_ISP_SYNC_VSYNC_EINTV_OFFSET);
-	mipi_csis_write(csis, MIPI_CSIS_ISP_SYNC_CH(0), val);
+	mipi_csis_write(csis, MIPI_CSIS_ISP_SYNC_CH(vc), val);
 
 	val = mipi_csis_read(csis, MIPI_CSIS_CLK_CTRL);
 	val |= MIPI_CSIS_CLK_CTRL_WCLK_SRC;
@@ -669,7 +672,7 @@ static void mipi_csis_set_params(struct mipi_csis_device *csis,
 	/* Update the shadow register. */
 	val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL);
 	mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL,
-			val | MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW |
+			val | MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW(vc) |
 			MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL);
 }
 
@@ -945,6 +948,8 @@ static int mipi_csis_s_stream(struct v4l2_subdev *sd, int enable)
 	struct v4l2_subdev_state *state;
 	int ret;
 
+	csis->vc = 0;
+
 	if (!enable) {
 		v4l2_subdev_disable_streams(csis->source.sd,
 					    csis->source.pad->index, BIT(0));
-- 
2.49.0

Re: [PATCH v2 07/12] media: imx-mipi-csis: Add support to configure specific vc

[Laurent Pinchart]

Hi Inbaraj,

On Thu, Aug 14, 2025 at 07:39:38PM +0530, Inbaraj E wrote:
> MIPI_CSIS_V3_3 and MIPI_CSIS_V3_6_3 support streaming only on VC0.

That doesn't appear to be true, at least for MIPI_CSIS_V3_6_3. I have a
patch series that adds VC support for v3.6.3 in the i.MX8MP, and it has
been susccessfully tested.

> The
> MIPI_CSIS_V4_3 present in the FSD SoC supports streaming on any one VC
> out of four VCs. To extend support for the FSD SoC, add the ability to
> configure a specific VC. The FSD CSI Rx can configure any one VC and
> start streaming.
> 
> Signed-off-by: Inbaraj E <inbaraj.e@samsung.com>
> ---
>  drivers/media/platform/nxp/imx-mipi-csis.c | 17 +++++++++++------
>  1 file changed, 11 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/media/platform/nxp/imx-mipi-csis.c b/drivers/media/platform/nxp/imx-mipi-csis.c
> index a3e2c8ae332f..4f6c417fdf58 100644
> --- a/drivers/media/platform/nxp/imx-mipi-csis.c
> +++ b/drivers/media/platform/nxp/imx-mipi-csis.c
> @@ -54,7 +54,7 @@
>  
>  /* CSIS common control */
>  #define MIPI_CSIS_CMN_CTRL			0x04
> -#define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW	BIT(16)
> +#define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW(n)	BIT(((n) + 16))
>  #define MIPI_CSIS_CMN_CTRL_INTER_MODE		BIT(10)
>  #define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL	BIT(2)
>  #define MIPI_CSIS_CMN_CTRL_RESET		BIT(1)
> @@ -319,6 +319,7 @@ struct mipi_csis_device {
>  		u32 hs_settle;
>  		u32 clk_settle;
>  	} debug;
> +	unsigned int vc;
>  };
>  
>  /* -----------------------------------------------------------------------------
> @@ -544,9 +545,10 @@ static void __mipi_csis_set_format(struct mipi_csis_device *csis,
>  				   const struct csis_pix_format *csis_fmt)
>  {
>  	u32 val;
> +	unsigned int vc = csis->vc;
>  
>  	/* Color format */
> -	val = mipi_csis_read(csis, MIPI_CSIS_ISP_CONFIG_CH(0));
> +	val = mipi_csis_read(csis, MIPI_CSIS_ISP_CONFIG_CH(vc));
>  	val &= ~(MIPI_CSIS_ISPCFG_ALIGN_32BIT | MIPI_CSIS_ISPCFG_FMT_MASK
>  		| MIPI_CSIS_ISPCFG_PIXEL_MASK);
>  
> @@ -567,11 +569,11 @@ static void __mipi_csis_set_format(struct mipi_csis_device *csis,
>  		val |= MIPI_CSIS_ISPCFG_PIXEL_MODE_DUAL;
>  
>  	val |= MIPI_CSIS_ISPCFG_FMT(csis_fmt->data_type);
> -	mipi_csis_write(csis, MIPI_CSIS_ISP_CONFIG_CH(0), val);
> +	mipi_csis_write(csis, MIPI_CSIS_ISP_CONFIG_CH(vc), val);
>  
>  	/* Pixel resolution */
>  	val = format->width | (format->height << 16);
> -	mipi_csis_write(csis, MIPI_CSIS_ISP_RESOL_CH(0), val);
> +	mipi_csis_write(csis, MIPI_CSIS_ISP_RESOL_CH(vc), val);
>  }
>  
>  static int mipi_csis_calculate_params(struct mipi_csis_device *csis,
> @@ -631,6 +633,7 @@ static void mipi_csis_set_params(struct mipi_csis_device *csis,
>  {
>  	int lanes = csis->bus.num_data_lanes;
>  	u32 val;
> +	unsigned int vc = csis->vc;
>  
>  	val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL);
>  	val &= ~MIPI_CSIS_CMN_CTRL_LANE_NR_MASK;
> @@ -648,7 +651,7 @@ static void mipi_csis_set_params(struct mipi_csis_device *csis,
>  	val = (0 << MIPI_CSIS_ISP_SYNC_HSYNC_LINTV_OFFSET)
>  	    | (0 << MIPI_CSIS_ISP_SYNC_VSYNC_SINTV_OFFSET)
>  	    | (0 << MIPI_CSIS_ISP_SYNC_VSYNC_EINTV_OFFSET);
> -	mipi_csis_write(csis, MIPI_CSIS_ISP_SYNC_CH(0), val);
> +	mipi_csis_write(csis, MIPI_CSIS_ISP_SYNC_CH(vc), val);
>  
>  	val = mipi_csis_read(csis, MIPI_CSIS_CLK_CTRL);
>  	val |= MIPI_CSIS_CLK_CTRL_WCLK_SRC;
> @@ -669,7 +672,7 @@ static void mipi_csis_set_params(struct mipi_csis_device *csis,
>  	/* Update the shadow register. */
>  	val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL);
>  	mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL,
> -			val | MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW |
> +			val | MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW(vc) |
>  			MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL);
>  }
>  
> @@ -945,6 +948,8 @@ static int mipi_csis_s_stream(struct v4l2_subdev *sd, int enable)
>  	struct v4l2_subdev_state *state;
>  	int ret;
>  
> +	csis->vc = 0;
> +

Dynamic VC selection belongs to this patch, not patch 09/12. 09/12 does
too many different things, it has to be split into one patch per
feature.

>  	if (!enable) {
>  		v4l2_subdev_disable_streams(csis->source.sd,
>  					    csis->source.pad->index, BIT(0));

-- 
Regards,

Laurent Pinchart

RE: [PATCH v2 07/12] media: imx-mipi-csis: Add support to configure specific vc

[Inbaraj E]

Hi Laurent,

Thanks for the review.

> 
> Hi Inbaraj,
> 
> On Thu, Aug 14, 2025 at 07:39:38PM +0530, Inbaraj E wrote:
> > MIPI_CSIS_V3_3 and MIPI_CSIS_V3_6_3 support streaming only on VC0.
> 
> That doesn't appear to be true, at least for MIPI_CSIS_V3_6_3. I have a patch
> series that adds VC support for v3.6.3 in the i.MX8MP, and it has been
> susccessfully tested.
> 

Thanks for the patches. I'll add Tesla FSD CSIS support on top of
Your patch.

> >
> > +	csis->vc = 0;
> > +
> 
> Dynamic VC selection belongs to this patch, not patch 09/12. 09/12 does too
> many different things, it has to be split into one patch per feature.
> 

I'll break down the patches by feature. 

Regards,
Inbaraj E

[PATCH v2 08/12] media: imx-mipi-csis: Add support to dump all vc regs

[Inbaraj E]

Extend support to dump all 4 virtual channel register.

Signed-off-by: Inbaraj E <inbaraj.e@samsung.com>
---
 drivers/media/platform/nxp/imx-mipi-csis.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/media/platform/nxp/imx-mipi-csis.c b/drivers/media/platform/nxp/imx-mipi-csis.c
index 4f6c417fdf58..c1653a738854 100644
--- a/drivers/media/platform/nxp/imx-mipi-csis.c
+++ b/drivers/media/platform/nxp/imx-mipi-csis.c
@@ -876,11 +876,26 @@ static int mipi_csis_dump_regs(struct mipi_csis_device *csis)
 		{ MIPI_CSIS_DPHY_SCTRL_L, "DPHY_SCTRL_L" },
 		{ MIPI_CSIS_DPHY_SCTRL_H, "DPHY_SCTRL_H" },
 		{ MIPI_CSIS_ISP_CONFIG_CH(0), "ISP_CONFIG_CH0" },
+		{ MIPI_CSIS_ISP_CONFIG_CH(1), "ISP_CONFIG_CH1" },
+		{ MIPI_CSIS_ISP_CONFIG_CH(2), "ISP_CONFIG_CH2" },
+		{ MIPI_CSIS_ISP_CONFIG_CH(3), "ISP_CONFIG_CH3" },
 		{ MIPI_CSIS_ISP_RESOL_CH(0), "ISP_RESOL_CH0" },
+		{ MIPI_CSIS_ISP_RESOL_CH(1), "ISP_RESOL_CH1" },
+		{ MIPI_CSIS_ISP_RESOL_CH(2), "ISP_RESOL_CH2" },
+		{ MIPI_CSIS_ISP_RESOL_CH(3), "ISP_RESOL_CH3" },
 		{ MIPI_CSIS_SDW_CONFIG_CH(0), "SDW_CONFIG_CH0" },
+		{ MIPI_CSIS_SDW_CONFIG_CH(1), "SDW_CONFIG_CH1" },
+		{ MIPI_CSIS_SDW_CONFIG_CH(2), "SDW_CONFIG_CH2" },
+		{ MIPI_CSIS_SDW_CONFIG_CH(3), "SDW_CONFIG_CH3" },
 		{ MIPI_CSIS_SDW_RESOL_CH(0), "SDW_RESOL_CH0" },
+		{ MIPI_CSIS_SDW_RESOL_CH(1), "SDW_RESOL_CH1" },
+		{ MIPI_CSIS_SDW_RESOL_CH(2), "SDW_RESOL_CH2" },
+		{ MIPI_CSIS_SDW_RESOL_CH(3), "SDW_RESOL_CH3" },
 		{ MIPI_CSIS_DBG_CTRL, "DBG_CTRL" },
 		{ MIPI_CSIS_FRAME_COUNTER_CH(0), "FRAME_COUNTER_CH0" },
+		{ MIPI_CSIS_FRAME_COUNTER_CH(1), "FRAME_COUNTER_CH1" },
+		{ MIPI_CSIS_FRAME_COUNTER_CH(2), "FRAME_COUNTER_CH2" },
+		{ MIPI_CSIS_FRAME_COUNTER_CH(3), "FRAME_COUNTER_CH3" },
 	};
 
 	unsigned int i;
-- 
2.49.0

Re: [PATCH v2 08/12] media: imx-mipi-csis: Add support to dump all vc regs

[Laurent Pinchart]

Hi Inbaraj,

Please see [1] and in particular [2]. I would like to get that series
merged for v6.18, but it's missing reviews. If you want to speed it up,
you can review the patches :-)

[1] https://lore.kernel.org/linux-media/20250608235840.23871-1-laurent.pinchart@ideasonboard.com
[2] https://lore.kernel.org/linux-media/20250608235840.23871-9-laurent.pinchart@ideasonboard.com/

On Thu, Aug 14, 2025 at 07:39:39PM +0530, Inbaraj E wrote:
> Extend support to dump all 4 virtual channel register.
> 
> Signed-off-by: Inbaraj E <inbaraj.e@samsung.com>
> ---
>  drivers/media/platform/nxp/imx-mipi-csis.c | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
> 
> diff --git a/drivers/media/platform/nxp/imx-mipi-csis.c b/drivers/media/platform/nxp/imx-mipi-csis.c
> index 4f6c417fdf58..c1653a738854 100644
> --- a/drivers/media/platform/nxp/imx-mipi-csis.c
> +++ b/drivers/media/platform/nxp/imx-mipi-csis.c
> @@ -876,11 +876,26 @@ static int mipi_csis_dump_regs(struct mipi_csis_device *csis)
>  		{ MIPI_CSIS_DPHY_SCTRL_L, "DPHY_SCTRL_L" },
>  		{ MIPI_CSIS_DPHY_SCTRL_H, "DPHY_SCTRL_H" },
>  		{ MIPI_CSIS_ISP_CONFIG_CH(0), "ISP_CONFIG_CH0" },
> +		{ MIPI_CSIS_ISP_CONFIG_CH(1), "ISP_CONFIG_CH1" },
> +		{ MIPI_CSIS_ISP_CONFIG_CH(2), "ISP_CONFIG_CH2" },
> +		{ MIPI_CSIS_ISP_CONFIG_CH(3), "ISP_CONFIG_CH3" },
>  		{ MIPI_CSIS_ISP_RESOL_CH(0), "ISP_RESOL_CH0" },
> +		{ MIPI_CSIS_ISP_RESOL_CH(1), "ISP_RESOL_CH1" },
> +		{ MIPI_CSIS_ISP_RESOL_CH(2), "ISP_RESOL_CH2" },
> +		{ MIPI_CSIS_ISP_RESOL_CH(3), "ISP_RESOL_CH3" },
>  		{ MIPI_CSIS_SDW_CONFIG_CH(0), "SDW_CONFIG_CH0" },
> +		{ MIPI_CSIS_SDW_CONFIG_CH(1), "SDW_CONFIG_CH1" },
> +		{ MIPI_CSIS_SDW_CONFIG_CH(2), "SDW_CONFIG_CH2" },
> +		{ MIPI_CSIS_SDW_CONFIG_CH(3), "SDW_CONFIG_CH3" },
>  		{ MIPI_CSIS_SDW_RESOL_CH(0), "SDW_RESOL_CH0" },
> +		{ MIPI_CSIS_SDW_RESOL_CH(1), "SDW_RESOL_CH1" },
> +		{ MIPI_CSIS_SDW_RESOL_CH(2), "SDW_RESOL_CH2" },
> +		{ MIPI_CSIS_SDW_RESOL_CH(3), "SDW_RESOL_CH3" },
>  		{ MIPI_CSIS_DBG_CTRL, "DBG_CTRL" },
>  		{ MIPI_CSIS_FRAME_COUNTER_CH(0), "FRAME_COUNTER_CH0" },
> +		{ MIPI_CSIS_FRAME_COUNTER_CH(1), "FRAME_COUNTER_CH1" },
> +		{ MIPI_CSIS_FRAME_COUNTER_CH(2), "FRAME_COUNTER_CH2" },
> +		{ MIPI_CSIS_FRAME_COUNTER_CH(3), "FRAME_COUNTER_CH3" },
>  	};
>  
>  	unsigned int i;

-- 
Regards,

Laurent Pinchart

RE: [PATCH v2 08/12] media: imx-mipi-csis: Add support to dump all vc regs

[Inbaraj E]

Hi Laurent,

Thanks for the review.

> 
> Please see [1] and in particular [2]. I would like to get that series merged for
> v6.18, but it's missing reviews. If you want to speed it up, you can review the
> patches :-)

I'll rebase my patches on top of your changes, test and provide review comment.

> 
> [1] https://lore.kernel.org/linux-media/20250608235840.23871-1-
> laurent.pinchart@ideasonboard.com
> [2] https://lore.kernel.org/linux-media/20250608235840.23871-9-
> laurent.pinchart@ideasonboard.com/


Regards,
Inbaraj E

[PATCH v2 09/12] media: imx-mipi-csis: Add support for FSD CSI Rx

[Inbaraj E]

The FSD SoC features a newer version(v4.3) of the CSI-2 receiver IP,
similar to the one found in the i.MX7 and i.MX8MM, with the following
differences.

- Ability to select any one VC for streaming from the four available
VCs.
- Built-in DMA support

Signed-off-by: Inbaraj E <inbaraj.e@samsung.com>
---
 drivers/media/platform/nxp/imx-mipi-csis.c | 304 +++++++++++++++++++--
 1 file changed, 276 insertions(+), 28 deletions(-)

diff --git a/drivers/media/platform/nxp/imx-mipi-csis.c b/drivers/media/platform/nxp/imx-mipi-csis.c
index c1653a738854..2ff2693dacf7 100644
--- a/drivers/media/platform/nxp/imx-mipi-csis.c
+++ b/drivers/media/platform/nxp/imx-mipi-csis.c
@@ -35,6 +35,8 @@
 #include <media/v4l2-fwnode.h>
 #include <media/v4l2-mc.h>
 #include <media/v4l2-subdev.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regmap.h>
 
 #define CSIS_DRIVER_NAME			"imx-mipi-csis"
 
@@ -45,6 +47,9 @@
 #define MIPI_CSIS_DEF_PIX_WIDTH			640
 #define MIPI_CSIS_DEF_PIX_HEIGHT		480
 
+/* CSIS V4_3 SYSREG macros */
+#define FSD_NO_CSI_PER_PHY_V4_3			4
+#define FSD_CSIS_RESETEN_DPHY_MASK_V4_3(phy)	BIT_MASK(phy)
 /* Register map definition */
 
 /* CSIS version */
@@ -55,7 +60,11 @@
 /* CSIS common control */
 #define MIPI_CSIS_CMN_CTRL			0x04
 #define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW(n)	BIT(((n) + 16))
-#define MIPI_CSIS_CMN_CTRL_INTER_MODE		BIT(10)
+#define MIPI_CSIS_CMN_CTRL_DESKEW_ENABLE	BIT(12)
+#define MIPI_CSIS_CMN_CTRL_INTER_MODE(n)	((n) << 10)
+#define MIPI_CSIS_CMN_CTRL_INTER_MODE_MASK	GENMASK(11, 10)
+#define MIPI_CSIS_CMN_CTRL_LANE_NUM(n)		((n) << 8)
+#define MIPI_CSIS_CMN_CTRL_LANE_NUM_MASK	GENMASK(9, 8)
 #define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL	BIT(2)
 #define MIPI_CSIS_CMN_CTRL_RESET		BIT(1)
 #define MIPI_CSIS_CMN_CTRL_ENABLE		BIT(0)
@@ -64,13 +73,11 @@
 #define MIPI_CSIS_CMN_CTRL_LANE_NR_MASK		(3 << 8)
 
 /* CSIS clock control */
-#define MIPI_CSIS_CLK_CTRL			0x08
-#define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH3(x)	((x) << 28)
-#define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH2(x)	((x) << 24)
-#define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH1(x)	((x) << 20)
-#define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH0(x)	((x) << 16)
-#define MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MSK	(0xf << 4)
-#define MIPI_CSIS_CLK_CTRL_WCLK_SRC		BIT(0)
+#define MIPI_CSIS_CLK_CTRL				0x08
+#define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH(n, val)	((val) << (16 + ((n) * 4)))
+#define MIPI_CSIS_CLK_CTRL_CLKGATE_EN(n)		(1 << ((n) + 4))
+#define MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MSK		(0xf << 4)
+#define MIPI_CSIS_CLK_CTRL_WCLK_SRC			BIT(0)
 
 /* CSIS Interrupt mask */
 #define MIPI_CSIS_INT_MSK			0x10
@@ -100,9 +107,9 @@
 #define MIPI_CSIS_INT_SRC_NON_IMAGE_DATA	(0xf << 28)
 #define MIPI_CSIS_INT_SRC_FRAME_START		BIT(24)
 #define MIPI_CSIS_INT_SRC_FRAME_END		BIT(20)
-#define MIPI_CSIS_INT_SRC_ERR_SOT_HS		BIT(16)
-#define MIPI_CSIS_INT_SRC_ERR_LOST_FS		BIT(12)
-#define MIPI_CSIS_INT_SRC_ERR_LOST_FE		BIT(8)
+#define MIPI_CSIS_INT_SRC_ERR_SOT_HS(n)		BIT((16 + (n)))
+#define MIPI_CSIS_INT_SRC_ERR_LOST_FS(n)	BIT((12 + (n)))
+#define MIPI_CSIS_INT_SRC_ERR_LOST_FE(n)	BIT((8 + (n)))
 #define MIPI_CSIS_INT_SRC_ERR_OVER		BIT(4)
 #define MIPI_CSIS_INT_SRC_ERR_WRONG_CFG		BIT(3)
 #define MIPI_CSIS_INT_SRC_ERR_ECC		BIT(2)
@@ -110,6 +117,12 @@
 #define MIPI_CSIS_INT_SRC_ERR_UNKNOWN		BIT(0)
 #define MIPI_CSIS_INT_SRC_ERRORS		0xfffff
 
+/* CSIS Interrupt mask1 */
+#define MIPI_CSIS_INT_MSK1			0x18
+
+/* CSIS Interrupt source1 */
+#define MIPI_CSIS_INT_SRC1			0x1C
+
 /* D-PHY status control */
 #define MIPI_CSIS_DPHY_STATUS			0x20
 #define MIPI_CSIS_DPHY_STATUS_ULPS_DAT		BIT(8)
@@ -123,6 +136,7 @@
 #define MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE_MASK	GENMASK(31, 24)
 #define MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE(n)	((n) << 22)
 #define MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE_MASK	GENMASK(23, 22)
+#define MIPI_CSIS_DPHY_CMN_CTRL_S_BYTE_CLK_EN	BIT(21)
 #define MIPI_CSIS_DPHY_CMN_CTRL_DPDN_SWAP_CLK	BIT(6)
 #define MIPI_CSIS_DPHY_CMN_CTRL_DPDN_SWAP_DAT	BIT(5)
 #define MIPI_CSIS_DPHY_CMN_CTRL_ENABLE_DAT	BIT(1)
@@ -170,7 +184,10 @@
 /* D-PHY Slave Control register Low */
 #define MIPI_CSIS_DPHY_SCTRL_L			0x38
 /* D-PHY Slave Control register High */
-#define MIPI_CSIS_DPHY_SCTRL_H			0x3c
+#define MIPI_CSIS_DPHY_SCTRL_H					0x3c
+#define MIPI_CSIS_DPHY_SCTRL_H_SKEW_CAL_MAX_SKEW_CODE_CTRL	(0x24 << 2)
+#define MIPI_CSIS_DPHY_SCTRL_H_SKEW_CAL_MAX_SKEW_CODE_CTRL_MASK GENMASK(7, 2)
+#define MIPI_CSIS_DPHY_SCTRL_H_SKEW_CAL_EN			BIT(1)
 
 /* ISP Configuration register */
 #define MIPI_CSIS_ISP_CONFIG_CH(n)		(0x40 + (n) * 0x10)
@@ -223,6 +240,12 @@
 
 #define MIPI_CSIS_FRAME_COUNTER_CH(n)		(0x0100 + (n) * 4)
 
+/* VC Passing register */
+#define MIPI_CSIS_VC_PASSING_REG	0x120
+#define MIPI_CSIS_VC_PASSING(n)		((n) << 8)
+#define MIPI_CSIS_VC_PASSING_MASK	GENMASK(9, 8)
+#define MIPI_CSIS_VC_PASSING_EN		BIT(7)
+
 /* Non-image packet data buffers */
 #define MIPI_CSIS_PKTDATA_ODD			0x2000
 #define MIPI_CSIS_PKTDATA_EVEN			0x3000
@@ -239,9 +262,18 @@ struct mipi_csis_event {
 
 static const struct mipi_csis_event mipi_csis_events[] = {
 	/* Errors */
-	{ false, MIPI_CSIS_INT_SRC_ERR_SOT_HS,		"SOT Error" },
-	{ false, MIPI_CSIS_INT_SRC_ERR_LOST_FS,		"Lost Frame Start Error" },
-	{ false, MIPI_CSIS_INT_SRC_ERR_LOST_FE,		"Lost Frame End Error" },
+	{ false, MIPI_CSIS_INT_SRC_ERR_SOT_HS(0),	"SOT Lane0 Error" },
+	{ false, MIPI_CSIS_INT_SRC_ERR_SOT_HS(1),       "SOT Lane1 Error" },
+	{ false, MIPI_CSIS_INT_SRC_ERR_SOT_HS(2),       "SOT Lane2 Error" },
+	{ false, MIPI_CSIS_INT_SRC_ERR_SOT_HS(3),       "SOT Lane3 Error" },
+	{ false, MIPI_CSIS_INT_SRC_ERR_LOST_FS(0),	"Lost Frame Start Error vc0" },
+	{ false, MIPI_CSIS_INT_SRC_ERR_LOST_FS(1),      "Lost Frame Start Error vc1" },
+	{ false, MIPI_CSIS_INT_SRC_ERR_LOST_FS(2),      "Lost Frame Start Error vc2" },
+	{ false, MIPI_CSIS_INT_SRC_ERR_LOST_FS(3),      "Lost Frame Start Error vc3" },
+	{ false, MIPI_CSIS_INT_SRC_ERR_LOST_FE(0),	"Lost Frame End Error vc0" },
+	{ false, MIPI_CSIS_INT_SRC_ERR_LOST_FE(1),      "Lost Frame End Error vc1" },
+	{ false, MIPI_CSIS_INT_SRC_ERR_LOST_FE(2),      "Lost Frame End Error vc2" },
+	{ false, MIPI_CSIS_INT_SRC_ERR_LOST_FE(3),      "Lost Frame End Error vc3" },
 	{ false, MIPI_CSIS_INT_SRC_ERR_OVER,		"FIFO Overflow Error" },
 	{ false, MIPI_CSIS_INT_SRC_ERR_WRONG_CFG,	"Wrong Configuration Error" },
 	{ false, MIPI_CSIS_INT_SRC_ERR_ECC,		"ECC Error" },
@@ -266,6 +298,7 @@ static const struct mipi_csis_event mipi_csis_events[] = {
 };
 
 #define MIPI_CSIS_NUM_EVENTS ARRAY_SIZE(mipi_csis_events)
+#define MIPI_CSIS_INT_SRC_NUM_EVENTS_V4_3	17
 
 #define MIPI_CSIS_MAX_CLOCKS	4
 
@@ -279,6 +312,7 @@ enum mipi_csis_clk {
 enum mipi_csis_version {
 	MIPI_CSIS_V3_3,
 	MIPI_CSIS_V3_6_3,
+	MIPI_CSIS_V4_3,
 };
 
 struct mipi_csis_info {
@@ -292,6 +326,8 @@ struct mipi_csis_info {
 struct mipi_csis_device {
 	struct device *dev;
 	void __iomem *regs;
+	struct regmap *sysreg_map;
+	unsigned int phy_rst_off;
 	struct clk_bulk_data *clks;
 	struct reset_control *mrst;
 	struct regulator *mipi_phy_regulator;
@@ -352,6 +388,11 @@ static const struct csis_pix_format mipi_csis_formats[] = {
 		.output = MEDIA_BUS_FMT_RGB888_1X24,
 		.data_type = MIPI_CSI2_DT_RGB888,
 		.width = 24,
+	}, {
+		.code = MEDIA_BUS_FMT_RGB888_1X24,
+		.output = MEDIA_BUS_FMT_RGB888_1X24,
+		.data_type = MIPI_CSI2_DT_RGB888,
+		.width = 24,
 	},
 	/* RAW (Bayer and greyscale) formats. */
 	{
@@ -508,7 +549,11 @@ static inline void mipi_csis_write(struct mipi_csis_device *csis, u32 reg,
 static void mipi_csis_enable_interrupts(struct mipi_csis_device *csis, bool on)
 {
 	mipi_csis_write(csis, MIPI_CSIS_INT_MSK, on ? 0xffffffff : 0);
-	mipi_csis_write(csis, MIPI_CSIS_DBG_INTR_MSK, on ? 0xffffffff : 0);
+
+	if (csis->info->version == MIPI_CSIS_V4_3)
+		mipi_csis_write(csis, MIPI_CSIS_INT_MSK1, on ? 0xffffffff : 0);
+	else
+		mipi_csis_write(csis, MIPI_CSIS_DBG_INTR_MSK, on ? 0xffffffff : 0);
 }
 
 static void mipi_csis_sw_reset(struct mipi_csis_device *csis)
@@ -537,6 +582,8 @@ static void mipi_csis_system_enable(struct mipi_csis_device *csis, int on)
 		mask = (1 << (csis->bus.num_data_lanes + 1)) - 1;
 		val |= (mask & MIPI_CSIS_DPHY_CMN_CTRL_ENABLE);
 	}
+	if (csis->info->version == MIPI_CSIS_V4_3)
+		val |= MIPI_CSIS_DPHY_CMN_CTRL_S_BYTE_CLK_EN;
 	mipi_csis_write(csis, MIPI_CSIS_DPHY_CMN_CTRL, val);
 }
 
@@ -549,7 +596,10 @@ static void __mipi_csis_set_format(struct mipi_csis_device *csis,
 
 	/* Color format */
 	val = mipi_csis_read(csis, MIPI_CSIS_ISP_CONFIG_CH(vc));
-	val &= ~(MIPI_CSIS_ISPCFG_ALIGN_32BIT | MIPI_CSIS_ISPCFG_FMT_MASK
+	if (csis->info->version == MIPI_CSIS_V4_3)
+		val &= ~(MIPI_CSIS_ISPCFG_FMT_MASK | MIPI_CSIS_ISPCFG_PIXEL_MASK);
+	else
+		val &= ~(MIPI_CSIS_ISPCFG_ALIGN_32BIT | MIPI_CSIS_ISPCFG_FMT_MASK
 		| MIPI_CSIS_ISPCFG_PIXEL_MASK);
 
 	/*
@@ -595,7 +645,7 @@ static int mipi_csis_calculate_params(struct mipi_csis_device *csis,
 
 	lane_rate = link_freq * 2;
 
-	if (lane_rate < 80000000 || lane_rate > 1500000000) {
+	if (lane_rate < 80000000 || lane_rate > 1600000000) {
 		dev_dbg(csis->dev, "Out-of-bound lane rate %u\n", lane_rate);
 		return -EINVAL;
 	}
@@ -639,7 +689,11 @@ static void mipi_csis_set_params(struct mipi_csis_device *csis,
 	val &= ~MIPI_CSIS_CMN_CTRL_LANE_NR_MASK;
 	val |= (lanes - 1) << MIPI_CSIS_CMN_CTRL_LANE_NR_OFFSET;
 	if (csis->info->version == MIPI_CSIS_V3_3)
-		val |= MIPI_CSIS_CMN_CTRL_INTER_MODE;
+		val |= MIPI_CSIS_CMN_CTRL_INTER_MODE(1);
+	else if (csis->info->version == MIPI_CSIS_V4_3) {
+		val |= MIPI_CSIS_CMN_CTRL_INTER_MODE(3);
+		val |= MIPI_CSIS_CMN_CTRL_DESKEW_ENABLE;
+	}
 	mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL, val);
 
 	__mipi_csis_set_format(csis, format, csis_fmt);
@@ -648,15 +702,23 @@ static void mipi_csis_set_params(struct mipi_csis_device *csis,
 			MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE(csis->hs_settle) |
 			MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE(csis->clk_settle));
 
-	val = (0 << MIPI_CSIS_ISP_SYNC_HSYNC_LINTV_OFFSET)
-	    | (0 << MIPI_CSIS_ISP_SYNC_VSYNC_SINTV_OFFSET)
-	    | (0 << MIPI_CSIS_ISP_SYNC_VSYNC_EINTV_OFFSET);
+	if (csis->info->version == MIPI_CSIS_V4_3)
+		val = 0x20 << MIPI_CSIS_ISP_SYNC_HSYNC_LINTV_OFFSET;
+	else
+		val = (0 << MIPI_CSIS_ISP_SYNC_HSYNC_LINTV_OFFSET)
+			| (0 << MIPI_CSIS_ISP_SYNC_VSYNC_SINTV_OFFSET)
+			| (0 << MIPI_CSIS_ISP_SYNC_VSYNC_EINTV_OFFSET);
 	mipi_csis_write(csis, MIPI_CSIS_ISP_SYNC_CH(vc), val);
 
 	val = mipi_csis_read(csis, MIPI_CSIS_CLK_CTRL);
-	val |= MIPI_CSIS_CLK_CTRL_WCLK_SRC;
-	val |= MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH0(15);
-	val &= ~MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MSK;
+	if (csis->info->version == MIPI_CSIS_V4_3) {
+		val |= MIPI_CSIS_CLK_CTRL_CLKGATE_EN(vc);
+		val |= MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH(vc, 0x07);
+	} else {
+		val |= MIPI_CSIS_CLK_CTRL_WCLK_SRC;
+		val |= MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH(vc, 15);
+		val &= ~MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MSK;
+	}
 	mipi_csis_write(csis, MIPI_CSIS_CLK_CTRL, val);
 
 	mipi_csis_write(csis, MIPI_CSIS_DPHY_BCTRL_L,
@@ -676,6 +738,24 @@ static void mipi_csis_set_params(struct mipi_csis_device *csis,
 			MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL);
 }
 
+static int mipi_csis_get_sysreg(struct mipi_csis_device *csis)
+{
+	unsigned int args;
+
+	if (csis->info->version != MIPI_CSIS_V4_3)
+		return 0;
+
+	csis->sysreg_map = syscon_regmap_lookup_by_phandle_args(
+			csis->dev->of_node, "samsung,syscon-csis", 1, &args);
+
+	if (IS_ERR(csis->sysreg_map))
+		return PTR_ERR(csis->sysreg_map);
+
+	csis->phy_rst_off = args;
+
+	return 0;
+}
+
 static int mipi_csis_clk_enable(struct mipi_csis_device *csis)
 {
 	return clk_bulk_prepare_enable(csis->info->num_clocks, csis->clks);
@@ -715,11 +795,71 @@ static int mipi_csis_clk_get(struct mipi_csis_device *csis)
 	return ret;
 }
 
+static void mipi_csis_dphy_reset_release_v4_3(struct mipi_csis_device *csis)
+{
+	unsigned int idx = 0, val = 0x0;
+
+	/* There are 4 CSIs per each D-PHY i/f */
+	idx = csis->vc;
+
+	regmap_read(csis->sysreg_map, csis->phy_rst_off, &val);
+
+	val &= ~FSD_CSIS_RESETEN_DPHY_MASK_V4_3(idx);
+	regmap_write(csis->sysreg_map, csis->phy_rst_off, val);
+
+	usleep_range(500, 1000);
+
+	val |= FSD_CSIS_RESETEN_DPHY_MASK_V4_3(idx);
+	regmap_write(csis->sysreg_map, csis->phy_rst_off, val);
+}
+
+static void mipi_csis_dphy_init_v4_3(struct mipi_csis_device *csis)
+{
+	u32 val = 0;
+
+	mipi_csis_dphy_reset_release_v4_3(csis);
+
+	val = readl(csis->regs + MIPI_CSIS_DPHY_SCTRL_H);
+
+	val |= MIPI_CSIS_DPHY_SCTRL_H_SKEW_CAL_EN;
+	val |= MIPI_CSIS_DPHY_SCTRL_H_SKEW_CAL_MAX_SKEW_CODE_CTRL;
+	writel(val, csis->regs + MIPI_CSIS_DPHY_SCTRL_H);
+}
+
+static void mipi_csis_set_vc_passing(struct mipi_csis_device *csis)
+{
+	u32 val;
+	unsigned int vc = csis->vc;
+
+	val = readl(csis->regs + MIPI_CSIS_VC_PASSING_REG);
+
+	val &= ~MIPI_CSIS_VC_PASSING_MASK;
+	val |= MIPI_CSIS_VC_PASSING(vc);
+	val |= MIPI_CSIS_VC_PASSING_EN;
+	writel(val, csis->regs + MIPI_CSIS_VC_PASSING_REG);
+}
+
+static void mipi_csis_get_irq_status(struct mipi_csis_device *csis,
+		unsigned int *sts)
+{
+	*sts = readl(csis->regs + MIPI_CSIS_INT_SRC1);
+}
+
+static void mipi_csis_clear_irq_status(struct mipi_csis_device *csis,
+		unsigned int *sts)
+{
+	writel(*sts, csis->regs + MIPI_CSIS_INT_SRC1);
+}
+
 static void mipi_csis_start_stream(struct mipi_csis_device *csis,
 				   const struct v4l2_mbus_framefmt *format,
 				   const struct csis_pix_format *csis_fmt)
 {
 	mipi_csis_sw_reset(csis);
+	if (csis->info->version == MIPI_CSIS_V4_3) {
+		mipi_csis_dphy_init_v4_3(csis);
+		mipi_csis_set_vc_passing(csis);
+	}
 	mipi_csis_set_params(csis, format, csis_fmt);
 	mipi_csis_system_enable(csis, true);
 	mipi_csis_enable_interrupts(csis, true);
@@ -743,6 +883,31 @@ static void mipi_csis_queue_event_sof(struct mipi_csis_device *csis)
 	v4l2_event_queue(csis->sd.devnode, &event);
 }
 
+static irqreturn_t mipi_csis_irq_handler_v4_3(int irq, void *dev_id)
+{
+	struct mipi_csis_device *csis = dev_id;
+	unsigned long flags;
+	u32 status;
+	unsigned int i;
+
+	status = mipi_csis_read(csis, MIPI_CSIS_INT_SRC);
+
+	spin_lock_irqsave(&csis->slock, flags);
+	if ((status & MIPI_CSIS_INT_SRC_ERRORS)) {
+		for (i = 0; i < MIPI_CSIS_INT_SRC_NUM_EVENTS_V4_3; i++) {
+			struct mipi_csis_event *event = &csis->events[i];
+
+			if (status & event->mask)
+				event->counter++;
+		}
+	}
+	spin_unlock_irqrestore(&csis->slock, flags);
+
+	mipi_csis_write(csis, MIPI_CSIS_INT_SRC, status);
+
+	return IRQ_NONE;
+}
+
 static irqreturn_t mipi_csis_irq_handler(int irq, void *dev_id)
 {
 	struct mipi_csis_device *csis = dev_id;
@@ -950,6 +1115,34 @@ static void mipi_csis_debugfs_exit(struct mipi_csis_device *csis)
  * V4L2 subdev operations
  */
 
+static int mipi_csis_get_vc(struct mipi_csis_device *csis)
+{
+	struct v4l2_mbus_frame_desc fd = { };
+	int ret;
+
+	ret = v4l2_subdev_call(csis->source.sd, pad, get_frame_desc, csis->source.pad->index, &fd);
+	if (ret < 0 && ret != -ENOIOCTLCMD) {
+		dev_err(csis->dev, "get_frame_desc failed on source subdev\n");
+		return ret;
+	}
+
+	/* If remote subdev does not implement ..get_frame_desc default to VC0 */
+	if (ret == -ENOIOCTLCMD)
+		return 0;
+
+	if (fd.type != V4L2_MBUS_FRAME_DESC_TYPE_CSI2) {
+		dev_err(csis->dev, "get_frame_desc returned invalid bus type %d\n", fd.type);
+		return -EINVAL;
+	}
+
+	if (!fd.num_entries) {
+		dev_err(csis->dev, "get_frame_desc returned zero enteries\n");
+		return -EINVAL;
+	}
+
+	return fd.entry[0].bus.csi2.vc;
+}
+
 static struct mipi_csis_device *sd_to_mipi_csis_device(struct v4l2_subdev *sdev)
 {
 	return container_of(sdev, struct mipi_csis_device, sd);
@@ -963,8 +1156,6 @@ static int mipi_csis_s_stream(struct v4l2_subdev *sd, int enable)
 	struct v4l2_subdev_state *state;
 	int ret;
 
-	csis->vc = 0;
-
 	if (!enable) {
 		v4l2_subdev_disable_streams(csis->source.sd,
 					    csis->source.pad->index, BIT(0));
@@ -1015,6 +1206,39 @@ static int mipi_csis_s_stream(struct v4l2_subdev *sd, int enable)
 	return ret;
 }
 
+static void mipi_csis_read_vc_frame_counter(struct mipi_csis_device *csis,
+		u32 *current_frame_counter)
+{
+	unsigned int vc = csis->vc;
+	*current_frame_counter = readl(csis->regs + MIPI_CSIS_FRAME_COUNTER_CH(vc));
+}
+
+static long mipi_csis_command(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
+{
+	struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd);
+	long ret = 0;
+
+	switch (cmd) {
+	case 1:
+		mipi_csis_system_enable(csis, true);
+		break;
+	case 2:
+		mipi_csis_get_irq_status(csis, arg);
+		break;
+	case 3:
+		mipi_csis_clear_irq_status(csis, arg);
+		break;
+	case 5:
+		mipi_csis_read_vc_frame_counter(csis, arg);
+		break;
+	default:
+		dev_err(csis->dev, "Invalid command\n");
+		ret = -1;
+	}
+
+	return ret;
+}
+
 static int mipi_csis_enum_mbus_code(struct v4l2_subdev *sd,
 				    struct v4l2_subdev_state *sd_state,
 				    struct v4l2_subdev_mbus_code_enum *code)
@@ -1122,6 +1346,7 @@ static int mipi_csis_set_fmt(struct v4l2_subdev *sd,
 static int mipi_csis_get_frame_desc(struct v4l2_subdev *sd, unsigned int pad,
 				    struct v4l2_mbus_frame_desc *fd)
 {
+	struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd);
 	struct v4l2_mbus_frame_desc_entry *entry = &fd->entry[0];
 	const struct csis_pix_format *csis_fmt;
 	const struct v4l2_mbus_framefmt *fmt;
@@ -1143,7 +1368,7 @@ static int mipi_csis_get_frame_desc(struct v4l2_subdev *sd, unsigned int pad,
 
 	entry->flags = 0;
 	entry->pixelcode = csis_fmt->code;
-	entry->bus.csi2.vc = 0;
+	entry->bus.csi2.vc = csis->vc;
 	entry->bus.csi2.dt = csis_fmt->data_type;
 
 	return 0;
@@ -1198,6 +1423,7 @@ static const struct v4l2_subdev_core_ops mipi_csis_core_ops = {
 	.log_status	= mipi_csis_log_status,
 	.subscribe_event =  mipi_csis_subscribe_event,
 	.unsubscribe_event = v4l2_event_subdev_unsubscribe,
+	.command = mipi_csis_command,
 };
 
 static const struct v4l2_subdev_video_ops mipi_csis_video_ops = {
@@ -1232,6 +1458,7 @@ static int mipi_csis_link_setup(struct media_entity *entity,
 	struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
 	struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd);
 	struct v4l2_subdev *remote_sd;
+	int ret;
 
 	dev_dbg(csis->dev, "link setup %s -> %s", remote_pad->entity->name,
 		local_pad->entity->name);
@@ -1248,6 +1475,14 @@ static int mipi_csis_link_setup(struct media_entity *entity,
 
 		csis->source.sd = remote_sd;
 		csis->source.pad = remote_pad;
+
+		ret = mipi_csis_get_vc(csis);
+
+		if (ret < 0)
+			return -EBUSY;
+
+		csis->vc = ret;
+
 	} else {
 		csis->source.sd = NULL;
 		csis->source.pad = NULL;
@@ -1472,6 +1707,10 @@ static int mipi_csis_probe(struct platform_device *pdev)
 	if (irq < 0)
 		return irq;
 
+	ret = mipi_csis_get_sysreg(csis);
+	if (ret < 0)
+		return ret;
+
 	ret = mipi_csis_phy_init(csis);
 	if (ret < 0)
 		return ret;
@@ -1570,6 +1809,15 @@ static const struct of_device_id mipi_csis_of_match[] = {
 			.irq_flag = 0,
 			.irq_handler = mipi_csis_irq_handler,
 		},
+	}, {
+		.compatible = "tesla,fsd-mipi-csi2",
+		.data = &(const struct mipi_csis_info){
+			.version = MIPI_CSIS_V4_3,
+			.num_clocks = 2,
+			.clk_names = { "aclk", "pclk"},
+			.irq_flag = IRQF_SHARED,
+			.irq_handler = mipi_csis_irq_handler_v4_3,
+		},
 	},
 	{ /* sentinel */ },
 };
-- 
2.49.0

[PATCH v2 10/12] dt-bindings: media: fsd: Document CSIS DMA controller

[Inbaraj E]

Document bindings for the FSD CSIS DMA controller.

Signed-off-by: Inbaraj E <inbaraj.e@samsung.com>
---
 .../bindings/media/tesla,fsd-csis-media.yaml  | 74 +++++++++++++++++++
 1 file changed, 74 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/media/tesla,fsd-csis-media.yaml

diff --git a/Documentation/devicetree/bindings/media/tesla,fsd-csis-media.yaml b/Documentation/devicetree/bindings/media/tesla,fsd-csis-media.yaml
new file mode 100644
index 000000000000..ce6c2e58ed4e
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/tesla,fsd-csis-media.yaml
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/tesla,fsd-csis-media.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Tesla FSD SoC MIPI CSI-2 DMA (Bridge device) receiver
+
+maintainers:
+  - Inbaraj E <inbaraj.e@samsung.com>
+
+description: |-
+  The FSD MIPI CSI-2 (Camera Serial Interface 2) have internal DMA engine to
+  capture frames originating from the sensor.
+
+properties:
+  compatible:
+    const: tesla,fsd-csis-media
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    maxItems: 3
+
+  clock-names:
+    items:
+      - const: aclk
+      - const: pclk
+      - const: pll
+
+  iommus:
+    maxItems: 1
+
+  port:
+    $ref: /schemas/graph.yaml#/properties/port
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - iommus
+  - port
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/fsd-clk.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    csi0: csi@12641000 {
+        compatible = "tesla,fsd-csis-media";
+        reg = <0x12661000 0x44c>;
+        interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&clock_csi CAM_CSI0_0_IPCLKPORT_I_ACLK>,
+                 <&clock_csi CAM_CSI0_0_IPCLKPORT_I_PCLK>,
+                 <&clock_csi CAM_CSI_PLL>;
+        clock-names = "aclk", "pclk", "pll";
+        iommus = <&smmu_isp 0x0 0x0>;
+
+        port {
+            csi_in_0: endpoint {
+                remote-endpoint = <&mipi_csis_0_out>;
+            };
+        };
+    };
+
+...
-- 
2.49.0

Re: [PATCH v2 10/12] dt-bindings: media: fsd: Document CSIS DMA controller

[Krzysztof Kozlowski]

On 14/08/2025 16:09, Inbaraj E wrote:
> Document bindings for the FSD CSIS DMA controller.
> 
> Signed-off-by: Inbaraj E <inbaraj.e@samsung.com>
> ---
>  .../bindings/media/tesla,fsd-csis-media.yaml  | 74 +++++++++++++++++++

Your patchset is organized in total mess. First clock, then media
bindings, then arm64,  then media drivers, then media bindings, then
arm64... Please organize it in standard way - about independent
subsystems I mentioned, so within media first bindings, then driver. Not
intermixed.



>  1 file changed, 74 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/media/tesla,fsd-csis-media.yaml
> 
> diff --git a/Documentation/devicetree/bindings/media/tesla,fsd-csis-media.yaml b/Documentation/devicetree/bindings/media/tesla,fsd-csis-media.yaml
> new file mode 100644
> index 000000000000..ce6c2e58ed4e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/tesla,fsd-csis-media.yaml
> @@ -0,0 +1,74 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/media/tesla,fsd-csis-media.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Tesla FSD SoC MIPI CSI-2 DMA (Bridge device) receiver
> +
> +maintainers:
> +  - Inbaraj E <inbaraj.e@samsung.com>
> +
> +description: |-

Drop |-

> +  The FSD MIPI CSI-2 (Camera Serial Interface 2) have internal DMA engine to
> +  capture frames originating from the sensor.
> +
> +properties:
> +  compatible:
> +    const: tesla,fsd-csis-media
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  clocks:
> +    maxItems: 3
> +
> +  clock-names:
> +    items:
> +      - const: aclk
> +      - const: pclk
> +      - const: pll
> +
> +  iommus:
> +    maxItems: 1
> +
> +  port:
> +    $ref: /schemas/graph.yaml#/properties/port

Don't you need second port to CSIS block? I guess this one is input from
the sensor?

> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - clocks
> +  - clock-names
> +  - iommus
> +  - port



Best regards,
Krzysztof

RE: [PATCH v2 10/12] dt-bindings: media: fsd: Document CSIS DMA controller

[Inbaraj E]

Hi Krzysztof,

Thanks for the review.

> 
> On 14/08/2025 16:09, Inbaraj E wrote:
> > Document bindings for the FSD CSIS DMA controller.
> >
> > Signed-off-by: Inbaraj E <inbaraj.e@samsung.com>
> > ---
> >  .../bindings/media/tesla,fsd-csis-media.yaml  | 74
> > +++++++++++++++++++
> 
> Your patchset is organized in total mess. First clock, then media bindings,
> then arm64,  then media drivers, then media bindings, then arm64... Please
> organize it in standard way - about independent subsystems I mentioned, so
> within media first bindings, then driver. Not intermixed.

I'll update in next patchset.

> 
> 
> 
> >  1 file changed, 74 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/media/tesla,fsd-csis-media.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/media/tesla,fsd-csis-media.yaml
> > b/Documentation/devicetree/bindings/media/tesla,fsd-csis-media.yaml
> > new file mode 100644
> > index 000000000000..ce6c2e58ed4e
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/media/tesla,fsd-csis-
> media.yam
> > +++ l
> > @@ -0,0 +1,74 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +$id:
> > +https://protect2.fireeye.com/v1/url?k=21cb70d9-4129ed84-21cafb96-
> 000b
> > +abd9f1ba-63c99c5193b8964e&q=1&e=f7087d49-8d33-4468-9323-
> 67fa9fa72e40&
> >
> +u=http%3A%2F%2Fdevicetree.org%2Fschemas%2Fmedia%2Ftesla%2Cfsd-
> csis-me
> > +dia.yaml%23
> > +$schema:
> > +https://protect2.fireeye.com/v1/url?k=4db8909d-2d5a0dc0-4db91bd2-
> 000b
> > +abd9f1ba-be3588ecc45596c1&q=1&e=f7087d49-8d33-4468-9323-
> 67fa9fa72e40&
> > +u=http%3A%2F%2Fdevicetree.org%2Fmeta-schemas%2Fcore.yaml%23
> > +
> > +title: Tesla FSD SoC MIPI CSI-2 DMA (Bridge device) receiver
> > +
> > +maintainers:
> > +  - Inbaraj E <inbaraj.e@samsung.com>
> > +
> > +description: |-
> 
> Drop |-
> 
> > +  The FSD MIPI CSI-2 (Camera Serial Interface 2) have internal DMA
> > + engine to  capture frames originating from the sensor.
> > +
> > +properties:
> > +  compatible:
> > +    const: tesla,fsd-csis-media
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  interrupts:
> > +    maxItems: 1
> > +
> > +  clocks:
> > +    maxItems: 3
> > +
> > +  clock-names:
> > +    items:
> > +      - const: aclk
> > +      - const: pclk
> > +      - const: pll
> > +
> > +  iommus:
> > +    maxItems: 1
> > +
> > +  port:
> > +    $ref: /schemas/graph.yaml#/properties/port
> 
> Don't you need second port to CSIS block?

No, one port is sufficient.
This port represent CSIS DMA and connected to CSIS (imx-mipi-csis node)

 I guess this one is input from the
> sensor?

No, it is input from CSIS(imx-mipi-csis).

Regards,
Inbaraj E

Re: [PATCH v2 10/12] dt-bindings: media: fsd: Document CSIS DMA controller

[Krzysztof Kozlowski]

On 14/08/2025 16:09, Inbaraj E wrote:
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - clocks
> +  - clock-names
> +  - iommus
> +  - port

Also, you miss here supplies (as required).

Best regards,
Krzysztof

RE: [PATCH v2 10/12] dt-bindings: media: fsd: Document CSIS DMA controller

[Inbaraj E]

Hi Krzysztof,

Thanks for the review.

> On 14/08/2025 16:09, Inbaraj E wrote:
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - interrupts
> > +  - clocks
> > +  - clock-names
> > +  - iommus
> > +  - port
> 
> Also, you miss here supplies (as required).

According to the HW design of FSD SoC, the control to manage CSIS power is given to
a separate CPU where custom firmware runs. Therefore. The Linux side does not control
the CSIS power supplies directly and are hence not included in the device tree.
 

Regards,
Inbaraj E

Re: [PATCH v2 10/12] dt-bindings: media: fsd: Document CSIS DMA controller

[Krzysztof Kozlowski]

On 23/08/2025 04:39, Inbaraj E wrote:
> Hi Krzysztof,
> 
> Thanks for the review.
> 
>> On 14/08/2025 16:09, Inbaraj E wrote:
>>> +
>>> +required:
>>> +  - compatible
>>> +  - reg
>>> +  - interrupts
>>> +  - clocks
>>> +  - clock-names
>>> +  - iommus
>>> +  - port
>>
>> Also, you miss here supplies (as required).
> 
> According to the HW design of FSD SoC, the control to manage CSIS power is given to
> a separate CPU where custom firmware runs. Therefore. The Linux side does not control
> the CSIS power supplies directly and are hence not included in the device tree.

Usually this still means you vote for enabling these resources, at least
for other vendors it is like that. Unless you want to say these are
essentially always on and CANNOT be disabled ever.

Best regards,
Krzysztof

RE: [PATCH v2 10/12] dt-bindings: media: fsd: Document CSIS DMA controller

[Inbaraj E]

Hi Krzysztof,

> > According to the HW design of FSD SoC, the control to manage CSIS
> > power is given to a separate CPU where custom firmware runs.
> > Therefore. The Linux side does not control the CSIS power supplies directly
> and are hence not included in the device tree.
> 
> Usually this still means you vote for enabling these resources, at least for
> other vendors it is like that. Unless you want to say these are essentially
> always on and CANNOT be disabled ever.

Yes, we want IP to remain enabled permanently, So we are not adding power supply
control in linux.

Regards,
Inbaraj E

Re: [PATCH v2 10/12] dt-bindings: media: fsd: Document CSIS DMA controller

[Krzysztof Kozlowski]

On 25/08/2025 14:01, Inbaraj E wrote:
> Hi Krzysztof,
> 
>>> According to the HW design of FSD SoC, the control to manage CSIS
>>> power is given to a separate CPU where custom firmware runs.
>>> Therefore. The Linux side does not control the CSIS power supplies directly
>> and are hence not included in the device tree.
>>
>> Usually this still means you vote for enabling these resources, at least for
>> other vendors it is like that. Unless you want to say these are essentially
>> always on and CANNOT be disabled ever.
> 
> Yes, we want IP to remain enabled permanently, So we are not adding power supply
> control in linux.

Please describe it in the description: part of the binding.

Best regards,
Krzysztof

Re: [PATCH v2 10/12] dt-bindings: media: fsd: Document CSIS DMA controller

[Laurent Pinchart]

Hi Krzysztof,

On Mon, Aug 18, 2025 at 10:45:17AM +0200, Krzysztof Kozlowski wrote:
> On 14/08/2025 16:09, Inbaraj E wrote:
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - interrupts
> > +  - clocks
> > +  - clock-names
> > +  - iommus
> > +  - port
> 
> Also, you miss here supplies (as required).

Did you perhaps mean power-domains ? As far as I understand this is an
IP core internal to an SoC, so *-supply would be quite uncommon.

-- 
Regards,

Laurent Pinchart

Re: [PATCH v2 10/12] dt-bindings: media: fsd: Document CSIS DMA controller

[Krzysztof Kozlowski]

On 24/08/2025 23:15, Laurent Pinchart wrote:
> Hi Krzysztof,
> 
> On Mon, Aug 18, 2025 at 10:45:17AM +0200, Krzysztof Kozlowski wrote:
>> On 14/08/2025 16:09, Inbaraj E wrote:
>>> +
>>> +required:
>>> +  - compatible
>>> +  - reg
>>> +  - interrupts
>>> +  - clocks
>>> +  - clock-names
>>> +  - iommus
>>> +  - port
>>
>> Also, you miss here supplies (as required).
> 
> Did you perhaps mean power-domains ? As far as I understand this is an
> IP core internal to an SoC, so *-supply would be quite uncommon.

Yes, power domains.


Best regards,
Krzysztof

[PATCH v2 11/12] arm64: defconfig: Enable FSD CSIS DMA driver

[Inbaraj E]

Enable CSIS DMA driver support for FSD based platforms.

Signed-off-by: Inbaraj E <inbaraj.e@samsung.com>
---
 arch/arm64/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 58f87d09366c..7f7e1fadb74f 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -878,6 +878,7 @@ CONFIG_VIDEO_RENESAS_VSP1=m
 CONFIG_VIDEO_RCAR_DRIF=m
 CONFIG_VIDEO_ROCKCHIP_RGA=m
 CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC=m
+CONFIG_VIDEO_FSD_CSIS=m
 CONFIG_VIDEO_SAMSUNG_S5P_JPEG=m
 CONFIG_VIDEO_SAMSUNG_S5P_MFC=m
 CONFIG_VIDEO_SUN6I_CSI=m
-- 
2.49.0

Re: [PATCH v2 11/12] arm64: defconfig: Enable FSD CSIS DMA driver

[Krzysztof Kozlowski]

On 14/08/2025 16:09, Inbaraj E wrote:
> Enable CSIS DMA driver support for FSD based platforms.

Tesla FSD

You are changing defconfig for all platforms, it's not your personal or
company defconfig.


Best regards,
Krzysztof

RE: [PATCH v2 11/12] arm64: defconfig: Enable FSD CSIS DMA driver

[Inbaraj E]

Hi Krzysztof,

Thanks for the review.

> 
> Tesla FSD
> 
> You are changing defconfig for all platforms, it's not your personal or
> company defconfig.

I noticed that Exynos and NXP driver configs are added in the defconfig.
Could you please clarify why I shouldn't add my driver config in defconfig?

> 
> 

Regards,
Inbaraj E

Re: [PATCH v2 11/12] arm64: defconfig: Enable FSD CSIS DMA driver

[Krzysztof Kozlowski]

On 23/08/2025 04:05, Inbaraj E wrote:
> Hi Krzysztof,
> 
> Thanks for the review.
> 
>>
>> Tesla FSD
>>
>> You are changing defconfig for all platforms, it's not your personal or
>> company defconfig.
> 
> I noticed that Exynos and NXP driver configs are added in the defconfig.
> Could you please clarify why I shouldn't add my driver config in defconfig?

No, I gave you rationale why your commit description is poor.

Best regards,
Krzysztof

RE: [PATCH v2 11/12] arm64: defconfig: Enable FSD CSIS DMA driver

[Inbaraj E]

Hi Krzysztof,

.
> >
> > I noticed that Exynos and NXP driver configs are added in the defconfig.
> > Could you please clarify why I shouldn't add my driver config in defconfig?
> 
> No, I gave you rationale why your commit description is poor.

I'll update the commit description in next patchset.

> 
> Best regards,
> Krzysztof

Regards,
Inbaraj E

[PATCH v2 12/12] media: fsd-csis: Add support for FSD CSIS DMA

[Inbaraj E]

FSD CSIS IP bundles DMA engine for receiving frames from MIPI-CSI2 bus.
Add support internal DMA controller to capture the frames.

Signed-off-by: Inbaraj E <inbaraj.e@samsung.com>
---
 MAINTAINERS                                   |    8 +
 drivers/media/platform/samsung/Kconfig        |    1 +
 drivers/media/platform/samsung/Makefile       |    1 +
 .../media/platform/samsung/fsd-csis/Kconfig   |   18 +
 .../media/platform/samsung/fsd-csis/Makefile  |    3 +
 .../platform/samsung/fsd-csis/fsd-csis.c      | 1709 +++++++++++++++++
 6 files changed, 1740 insertions(+)
 create mode 100644 drivers/media/platform/samsung/fsd-csis/Kconfig
 create mode 100644 drivers/media/platform/samsung/fsd-csis/Makefile
 create mode 100644 drivers/media/platform/samsung/fsd-csis/fsd-csis.c

diff --git a/MAINTAINERS b/MAINTAINERS
index bd62ad58a47f..1e17fb0581d2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3334,6 +3334,14 @@ S:	Maintained
 F:	Documentation/devicetree/bindings/media/samsung,s5p-mfc.yaml
 F:	drivers/media/platform/samsung/s5p-mfc/
 
+ARM/SAMSUNG FSD BRIDGE DRIVER
+M:	Inbaraj E <inbaraj.e@samsung.com>
+L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+L:	linux-media@vger.kernel.org
+S:	Maintained
+F:	Documentation/devicetree/bindings/media/tesla,fsd-csis-media.yaml
+F:	drivers/media/platform/samsung/fsd-csis/fsd-csis.c
+
 ARM/SOCFPGA ARCHITECTURE
 M:	Dinh Nguyen <dinguyen@kernel.org>
 S:	Maintained
diff --git a/drivers/media/platform/samsung/Kconfig b/drivers/media/platform/samsung/Kconfig
index 0e34c5fc1dfc..4cebe2ae24a3 100644
--- a/drivers/media/platform/samsung/Kconfig
+++ b/drivers/media/platform/samsung/Kconfig
@@ -4,6 +4,7 @@ comment "Samsung media platform drivers"
 
 source "drivers/media/platform/samsung/exynos-gsc/Kconfig"
 source "drivers/media/platform/samsung/exynos4-is/Kconfig"
+source "drivers/media/platform/samsung/fsd-csis/Kconfig"
 source "drivers/media/platform/samsung/s3c-camif/Kconfig"
 source "drivers/media/platform/samsung/s5p-g2d/Kconfig"
 source "drivers/media/platform/samsung/s5p-jpeg/Kconfig"
diff --git a/drivers/media/platform/samsung/Makefile b/drivers/media/platform/samsung/Makefile
index 21fea3330e4b..fde1b9626713 100644
--- a/drivers/media/platform/samsung/Makefile
+++ b/drivers/media/platform/samsung/Makefile
@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-only
 obj-y += exynos-gsc/
 obj-y += exynos4-is/
+obj-y += fsd-csis/
 obj-y += s3c-camif/
 obj-y += s5p-g2d/
 obj-y += s5p-jpeg/
diff --git a/drivers/media/platform/samsung/fsd-csis/Kconfig b/drivers/media/platform/samsung/fsd-csis/Kconfig
new file mode 100644
index 000000000000..99803e924682
--- /dev/null
+++ b/drivers/media/platform/samsung/fsd-csis/Kconfig
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# FSD MIPI CSI-2 Rx controller configurations
+
+config VIDEO_FSD_CSIS
+	tristate "FSD SoC MIPI-CSI2 media controller driver"
+	depends on VIDEO_DEV && VIDEO_V4L2_SUBDEV_API
+	depends on HAS_DMA
+	depends on OF
+	select VIDEOBUF2_DMA_CONTIG
+	select V4L2_FWNODE
+	help
+	  This is a video4linux2 driver for FSD SoC MIPI-CSI2 Rx.
+	  The driver provides interface for capturing frames.
+
+	  To compile this driver as a module, choose M here. The module
+	  will be called fsd-csis.
+
diff --git a/drivers/media/platform/samsung/fsd-csis/Makefile b/drivers/media/platform/samsung/fsd-csis/Makefile
new file mode 100644
index 000000000000..eba8c0c6a7cc
--- /dev/null
+++ b/drivers/media/platform/samsung/fsd-csis/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+obj-$(CONFIG_VIDEO_FSD_CSIS) += fsd-csis.o
diff --git a/drivers/media/platform/samsung/fsd-csis/fsd-csis.c b/drivers/media/platform/samsung/fsd-csis/fsd-csis.c
new file mode 100644
index 000000000000..74f46038d506
--- /dev/null
+++ b/drivers/media/platform/samsung/fsd-csis/fsd-csis.c
@@ -0,0 +1,1709 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2022-2025 Samsung Electronics Co., Ltd.
+ *             https://www.samsung.com
+ *
+ * FSD CSIS V4L2 Capture driver for FSD SoC.
+ */
+
+#include <linux/clk.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+#include <media/v4l2-device.h>
+#include <media/v4l2-ioctl.h>
+#include <media/videobuf2-dma-contig.h>
+#include <media/v4l2-mc.h>
+
+#define FSD_CSIS_DMA_COHERENT_MASK_SIZE		32
+#define FSD_CSIS_NB_MIN_CH			2
+#define FSD_CSIS_NB_VC				4
+#define FSD_CSIS_MEDIA_NUM_PADS			2
+#define FSD_CSIS_NB_DMA_OUT_CH			8
+#define FSD_CSIS_MAX_VC				4
+#define FSD_CSIS_NB_CLOCK			2
+#define FSD_CSIS_NB_OF_BUFS_ON_DMA_CHANNELS	2
+#define FSD_CSIS_DMA_LINE_ALIGN_SIZE		128
+#define FSD_CSIS_DMA_CH_OFFSET			0x100
+
+/**
+ * (Interrupt Source & mask register 1)
+ */
+#define FSD_CSIS_DMA_OTF_OVERLAP_MASK	GENMASK(17, 14)
+#define FSD_CSIS_DMA_ABORT_DONE_MASK	BIT(13)
+#define FSD_CSIS_DMA_ERROR_MASK		BIT(12)
+#define FSD_CSIS_INT_SRC1_ERR_ALL_MASK	(FSD_CSIS_DMA_ERROR_MASK | \
+					FSD_CSIS_DMA_ABORT_DONE_MASK | \
+					FSD_CSIS_DMA_ERROR_MASK)
+#define FDS_CSIS_DMA_FRM_END_MASK	GENMASK(11, 8)
+#define FSD_CSIS_DMA_FRM_START_MASK	GENMASK(7, 4)
+#define FSD_CSIS_LINE_END_MASK		GENMASK(3, 0)
+#define FSD_CSIS_DMA_CH0_MASK		0x4111U
+
+/* DMA Reg offsets */
+#define FSD_CSIS_DMA0_CTRL	0x0
+#define FSD_CSIS_DMA_CTRL(vc)	(FSD_CSIS_DMA0_CTRL + (vc) * FSD_CSIS_DMA_CH_OFFSET)
+#define FSD_CSIS_DMA_DISABLE	BIT(0)
+
+#define FSD_CSIS_DMA0_FMT	0x4
+#define FSD_CSIS_DMA_FMT(vc)	(FSD_CSIS_DMA0_FMT + (vc) * FSD_CSIS_DMA_CH_OFFSET)
+#define FSD_CSIS_DMA_DIM	BIT(15)
+#define FSD_CSIS_DMA_DUMP	BIT(13)
+
+#define FSD_CSIS_DMA0_ADDR1     0x10
+#define FSD_CSIS_DMA_ADDR1(vc)	(FSD_CSIS_DMA0_ADDR1 + (vc) * FSD_CSIS_DMA_CH_OFFSET)
+
+#define FSD_CSIS_DMA0_ACT_CTRL		0x30
+#define FSD_CSIS_DMA_ACT_CTRL(vc)	(FSD_CSIS_DMA0_ACT_CTRL + (vc) * FSD_CSIS_DMA_CH_OFFSET)
+#define FSD_CSIS_ACTIVE_DMA_PACK_MASK		GENMASK(17, 16)
+#define FSD_CSIS_ACTIVE_DMA_PACK(n)		((n) << 16)
+#define FSD_CSIS_ACTIVE_DMA_FRAMEPTR_MASK	GENMASK(4, 2)
+
+#define FSD_CSIS_DMA_ERR_CODE		0x404
+#define FSD_CSIS_DMAFIFO_FULL_MASK	BIT_MASK(5)
+#define FSD_CSIS_TRXFIFO_FULL_MASK	BIT_MASK(4)
+
+#define FSD_CSIS_DMA_CLK_CTRL			0x408
+#define FSD_CSIS_DMA_CLK_GATE_TRAIL_MASK	GENMASK(4, 1)
+#define FSD_CSIS_DMA_CLK_GATE_TRAIL(n)		((n) << 1)
+#define FSD_CSIS_DMA_CLK_GATE_EN		BIT(0)
+
+enum CSIS_DMA_PACK {
+	DMA_PACK_NORMAL,
+	DMA_PACK_10,
+	DMA_PACK_12,
+	DMA_PACK_14,
+	DMA_PACK_18,
+	DMA_PACK_20,
+};
+
+static const char * const fsd_csis_clk_id[] = {
+	"aclk",
+	"pclk",
+};
+
+struct fsd_csis_pixfmt {
+	u32 fourcc;
+	const u32 *codes;
+	int bpp;
+	bool is_yuv;
+};
+
+struct fsd_csis_vb2_buffer {
+	struct vb2_v4l2_buffer vb;
+	struct list_head list;
+	const struct fsd_csis_pixfmt *fmt;
+	unsigned long sequence_num;
+};
+
+struct fsd_csis {
+	struct device *dev;
+	const struct fsd_csis_info *info;
+	struct clk_bulk_data *clks;
+	struct clk *pll;
+	struct media_device mdev;
+	struct v4l2_device v4l2_dev;
+	struct v4l2_async_notifier notifier;
+	struct media_pipeline pipe;
+
+	/* source node */
+	struct {
+		struct v4l2_subdev *subdev;
+		struct media_pad *pad;
+	} source;
+
+	/* Internal subdev */
+	struct {
+		struct v4l2_subdev sd;
+		struct media_pad pad[FSD_CSIS_MEDIA_NUM_PADS];
+	} subdev;
+
+	struct video_device *vdev;
+	struct media_pad vdev_pad;
+	struct vb2_queue q;
+	struct mutex vdev_mutex;
+	struct mutex mutex_csis_dma_reg;
+	spinlock_t lock_buf;
+	void __iomem *dma_base;
+	int irq;
+	u64 frame_addr[FSD_CSIS_NB_DMA_OUT_CH];
+	struct fsd_csis_vb2_buffer *frame[FSD_CSIS_NB_DMA_OUT_CH];
+	struct v4l2_pix_format vdev_fmt;
+	const struct fsd_csis_pixfmt *vdev_cc;
+	struct v4l2_rect vdev_compose;
+	u32 num_reqbufs;
+	u8 prev_dma_ptr;
+	u8 current_dma_ptr;
+	u8 number_of_ready_bufs;
+	u32 prev_frame_counter;
+	u32 current_frame_counter;
+	unsigned int num_active_fmt;
+	struct list_head ready_q;
+	spinlock_t q_lock;
+	unsigned int current_vc;
+	unsigned long sequence;
+	u32 dma_error;
+	struct mutex mutex;
+	int is_streaming;
+};
+
+static inline u32 get_bits(u32 value, u32 mask)
+{
+	return (((value) & (mask)) >> (ffs(mask) - 1));
+}
+
+static inline u32 bytes_per_line(u32 width, int bpp)
+{
+	return (ALIGN((width * bpp), FSD_CSIS_DMA_LINE_ALIGN_SIZE) >> 3);
+}
+
+static inline uint8_t fsd_csis_current_dma_ptr(struct fsd_csis *csis)
+
+{
+	return (readl(csis->dma_base + FSD_CSIS_DMA_ACT_CTRL(csis->current_vc))
+			& 0x01C) >> 2;
+}
+
+#define FSD_CSIS_MODULE_NAME	"fsd-csis-media"
+#define FSD_CSIS_MODULE_VERSION	"0.0.1"
+
+#define FSD_CSIS_DEF_MBUS_CODE		MEDIA_BUS_FMT_RGB888_1X24
+#define FSD_CSIS_DEF_PIX_FORMAT		V4L2_PIX_FMT_RGB24
+#define FSD_CSIS_DEF_PIX_WIDTH		1280
+#define FSD_CSIS_DEF_PIX_HEIGHT		964
+
+#define FSD_CSIS_PAD_SINK	0
+#define FSD_CSIS_PAD_SRC	1
+#define FSD_CSIS_PADS_NUM	2
+
+#define FSD_CSIS_BUS_FMTS(fmt...) ((const u32[]) {fmt, 0 })
+
+static const struct v4l2_mbus_framefmt fsd_csis_default_format = {
+	.width = 640,
+	.height = 480,
+	.code = MEDIA_BUS_FMT_UYVY8_1X16,
+	.field = V4L2_FIELD_NONE,
+};
+
+static const struct fsd_csis_pixfmt pixel_formats[] = {
+	/* YUV formats start here */
+	{
+		.fourcc = V4L2_PIX_FMT_UYVY,
+		.codes  = FSD_CSIS_BUS_FMTS(
+			MEDIA_BUS_FMT_UYVY8_2X8,
+			MEDIA_BUS_FMT_UYVY8_1X16
+		),
+		.is_yuv    = true,
+		.bpp    = 16,
+	}, {
+		.fourcc = V4L2_PIX_FMT_YUYV,
+		.codes  = FSD_CSIS_BUS_FMTS(
+			MEDIA_BUS_FMT_YUYV8_2X8,
+			MEDIA_BUS_FMT_YUYV8_1X16
+		),
+		.is_yuv    = true,
+		.bpp    = 16,
+	}, {
+		.fourcc = V4L2_PIX_FMT_SBGGR8,
+		.codes  = FSD_CSIS_BUS_FMTS(MEDIA_BUS_FMT_SBGGR8_1X8),
+		.bpp    = 8,
+	}, {
+		.fourcc = V4L2_PIX_FMT_SGBRG8,
+		.codes  = FSD_CSIS_BUS_FMTS(MEDIA_BUS_FMT_SGBRG8_1X8),
+		.bpp    = 8,
+	}, {
+		.fourcc = V4L2_PIX_FMT_SGRBG8,
+		.codes  = FSD_CSIS_BUS_FMTS(MEDIA_BUS_FMT_SGRBG8_1X8),
+		.bpp    = 8,
+	}, {
+		.fourcc = V4L2_PIX_FMT_SRGGB8,
+		.codes  = FSD_CSIS_BUS_FMTS(MEDIA_BUS_FMT_SRGGB8_1X8),
+		.bpp    = 8,
+	}, {
+		.fourcc = V4L2_PIX_FMT_SBGGR10,
+		.codes  = FSD_CSIS_BUS_FMTS(MEDIA_BUS_FMT_SBGGR10_1X10),
+		.bpp    = 16,
+	}, {
+		.fourcc = V4L2_PIX_FMT_SGBRG10,
+		.codes  = FSD_CSIS_BUS_FMTS(MEDIA_BUS_FMT_SGBRG10_1X10),
+		.bpp    = 16,
+	}, {
+		.fourcc = V4L2_PIX_FMT_SGRBG10,
+		.codes  = FSD_CSIS_BUS_FMTS(MEDIA_BUS_FMT_SGRBG10_1X10),
+		.bpp    = 16,
+	}, {
+		.fourcc = V4L2_PIX_FMT_SRGGB10,
+		.codes  = FSD_CSIS_BUS_FMTS(MEDIA_BUS_FMT_SRGGB10_1X10),
+		.bpp    = 16,
+	}, {
+		.fourcc = V4L2_PIX_FMT_SBGGR12,
+		.codes  = FSD_CSIS_BUS_FMTS(MEDIA_BUS_FMT_SBGGR12_1X12),
+		.bpp    = 16,
+	}, {
+		.fourcc = V4L2_PIX_FMT_SGBRG12,
+		.codes  = FSD_CSIS_BUS_FMTS(MEDIA_BUS_FMT_SGBRG12_1X12),
+		.bpp    = 16,
+	}, {
+		.fourcc = V4L2_PIX_FMT_SGRBG12,
+		.codes  = FSD_CSIS_BUS_FMTS(MEDIA_BUS_FMT_SGRBG12_1X12),
+		.bpp    = 16,
+	}, {
+		.fourcc = V4L2_PIX_FMT_SRGGB12,
+		.codes  = FSD_CSIS_BUS_FMTS(MEDIA_BUS_FMT_SRGGB12_1X12),
+		.bpp    = 16,
+	}, {
+		.fourcc = V4L2_PIX_FMT_SBGGR14,
+		.codes  = FSD_CSIS_BUS_FMTS(MEDIA_BUS_FMT_SBGGR14_1X14),
+		.bpp    = 16,
+	}, {
+		.fourcc = V4L2_PIX_FMT_SGBRG14,
+		.codes  = FSD_CSIS_BUS_FMTS(MEDIA_BUS_FMT_SGBRG14_1X14),
+		.bpp    = 16,
+	}, {
+		.fourcc = V4L2_PIX_FMT_SGRBG14,
+		.codes  = FSD_CSIS_BUS_FMTS(MEDIA_BUS_FMT_SGRBG14_1X14),
+		.bpp    = 16,
+	}, {
+		.fourcc = V4L2_PIX_FMT_SRGGB14,
+		.codes  = FSD_CSIS_BUS_FMTS(MEDIA_BUS_FMT_SRGGB14_1X14),
+		.bpp    = 16,
+	}, {
+		.fourcc = V4L2_PIX_FMT_GREY,
+		.codes  = FSD_CSIS_BUS_FMTS(MEDIA_BUS_FMT_Y8_1X8),
+		.bpp    = 8,
+	}, {
+		.fourcc = V4L2_PIX_FMT_Y10,
+		.codes  = FSD_CSIS_BUS_FMTS(MEDIA_BUS_FMT_Y10_1X10),
+		.bpp    = 16,
+	}, {
+		.fourcc = V4L2_PIX_FMT_Y12,
+		.codes  = FSD_CSIS_BUS_FMTS(MEDIA_BUS_FMT_Y12_1X12),
+		.bpp    = 16,
+	}, {
+		.fourcc = V4L2_PIX_FMT_Y14,
+		.codes  = FSD_CSIS_BUS_FMTS(MEDIA_BUS_FMT_Y14_1X14),
+		.bpp    = 16,
+	}, {
+		.fourcc	= V4L2_PIX_FMT_RGB24,
+		.codes	= FSD_CSIS_BUS_FMTS(MEDIA_BUS_FMT_RGB888_1X24),
+		.bpp	= 24,
+	}
+};
+
+static void fsd_csis_dma_enable(struct fsd_csis *csis, bool en_dma)
+{
+	unsigned int dma_ctrl, vc = csis->current_vc;
+
+	dma_ctrl = readl(csis->dma_base + FSD_CSIS_DMA_CTRL(vc));
+	dma_ctrl |= FSD_CSIS_DMA_DISABLE;
+
+	if (en_dma)
+		dma_ctrl &= ~FSD_CSIS_DMA_DISABLE;
+
+	writel(dma_ctrl, csis->dma_base + FSD_CSIS_DMA_CTRL(vc));
+}
+
+static void fsd_csis_set_dma_clk(struct fsd_csis *csis)
+{
+	unsigned int dma_clk_ctrl;
+
+	dma_clk_ctrl = readl(csis->dma_base + FSD_CSIS_DMA_CLK_CTRL);
+
+	dma_clk_ctrl &= ~FSD_CSIS_DMA_CLK_GATE_EN;
+	dma_clk_ctrl &= ~FSD_CSIS_DMA_CLK_GATE_TRAIL_MASK;
+	dma_clk_ctrl |= FSD_CSIS_DMA_CLK_GATE_TRAIL(0x7);
+
+	writel(dma_clk_ctrl, csis->dma_base + FSD_CSIS_DMA_CLK_CTRL);
+}
+
+static void fsd_csis_set_pack(struct fsd_csis *csis, u32 vc,
+		enum CSIS_DMA_PACK dma_pack)
+{
+	u32 dma_fmt;
+
+	dma_fmt = readl(csis->dma_base + FSD_CSIS_DMA_CTRL(vc));
+	dma_fmt &= ~FSD_CSIS_ACTIVE_DMA_PACK_MASK;
+	dma_fmt |= FSD_CSIS_ACTIVE_DMA_PACK(dma_pack);
+	writel(dma_fmt, csis->dma_base + FSD_CSIS_DMA_CTRL(vc));
+}
+
+static void fsd_csis_set_dma_dump(struct fsd_csis *csis, unsigned int vc,
+		bool set_dump)
+{
+	u32 dma_fmt;
+
+	dma_fmt = readl(csis->dma_base + FSD_CSIS_DMA_CTRL(vc));
+	dma_fmt &= ~FSD_CSIS_DMA_DUMP;
+
+	if (set_dump)
+		dma_fmt |= FSD_CSIS_DMA_DUMP;
+
+	writel(dma_fmt, csis->dma_base + FSD_CSIS_DMA_CTRL(vc));
+}
+
+static void fsd_csis_set_dma_dimension(struct fsd_csis *csis, u32 vc, bool set_dim)
+{
+	u32 dma_fmt;
+
+	dma_fmt = readl(csis->dma_base + FSD_CSIS_DMA_FMT(vc));
+	dma_fmt &= ~FSD_CSIS_DMA_DIM;
+
+	if (set_dim)
+		dma_fmt |= FSD_CSIS_DMA_DIM;
+
+	writel(dma_fmt, csis->dma_base + FSD_CSIS_DMA_FMT(vc));
+}
+
+static void fsd_csis_set_dma_format(struct fsd_csis *csis,
+		const struct fsd_csis_pixfmt *cc)
+{
+	unsigned int fourcc = cc->fourcc;
+
+	switch (fourcc) {
+	case V4L2_PIX_FMT_SBGGR10:
+	case V4L2_PIX_FMT_SGBRG10:
+	case V4L2_PIX_FMT_SGRBG10:
+	case V4L2_PIX_FMT_SRGGB10:
+		fsd_csis_set_pack(csis, csis->current_vc, DMA_PACK_10);
+		break;
+	case V4L2_PIX_FMT_SBGGR12:
+	case V4L2_PIX_FMT_SGBRG12:
+	case V4L2_PIX_FMT_SGRBG12:
+	case V4L2_PIX_FMT_SRGGB12:
+		fsd_csis_set_pack(csis, csis->current_vc, DMA_PACK_12);
+		break;
+	case V4L2_PIX_FMT_SBGGR14P:
+		fsd_csis_set_pack(csis, csis->current_vc, DMA_PACK_14);
+		break;
+	case V4L2_PIX_FMT_BGR666:
+		fsd_csis_set_pack(csis, csis->current_vc, DMA_PACK_18);
+		break;
+	case V4L2_PIX_FMT_UYVY:
+		fsd_csis_set_pack(csis, csis->current_vc, DMA_PACK_NORMAL);
+		break;
+	default:
+		dev_err(csis->dev, "Set DMA format %x not supported\n", fourcc);
+		break;
+	}
+
+	fsd_csis_set_dma_dump(csis, csis->current_vc, false);
+	fsd_csis_set_dma_dimension(csis, csis->current_vc, false);
+}
+
+static inline struct fsd_csis *notifier_to_csis(struct v4l2_async_notifier *n)
+{
+	return container_of(n, struct fsd_csis, notifier);
+}
+
+static int fsd_queue_setup(struct vb2_queue *vq,
+		unsigned int *nbuffers, unsigned int *nplanes,
+		unsigned int sizes[], struct device *alloc_devs[])
+{
+	struct fsd_csis *csis = vb2_get_drv_priv(vq);
+	struct v4l2_pix_format *pix = &csis->vdev_fmt;
+	unsigned int size = pix->sizeimage;
+
+	if (*nplanes) {
+		if (sizes[0] < size)
+			return -EINVAL;
+		size = sizes[0];
+	}
+
+	*nplanes = 1;
+	sizes[0] = size;
+
+	dev_info(csis->dev, "nbuffers %d size %d\n", *nbuffers, sizes[0]);
+
+	return 0;
+}
+
+static int fsd_buffer_prepare(struct vb2_buffer *vb)
+{
+	struct fsd_csis *csis = vb2_get_drv_priv(vb->vb2_queue);
+	struct fsd_csis_vb2_buffer *buf = container_of(vb, struct fsd_csis_vb2_buffer,
+			vb.vb2_buf);
+	unsigned long size;
+
+	if (WARN_ON(!csis->vdev_cc))
+		return -EINVAL;
+
+	if (vb2_plane_size(vb, 0) < size) {
+		dev_info(csis->dev, "Data will not fit into plane (%lu < %lu)\n",
+				vb2_plane_size(vb, 0), size);
+		return -EINVAL;
+	}
+
+	vb2_set_plane_payload(&buf->vb.vb2_buf, 0, size);
+
+	return 0;
+}
+
+static void fsd_buffer_queue(struct vb2_buffer *vb)
+{
+	unsigned long flags;
+	struct fsd_csis *csis = vb2_get_drv_priv(vb->vb2_queue);
+	struct fsd_csis_vb2_buffer *buf =
+		container_of(vb, struct fsd_csis_vb2_buffer, vb.vb2_buf);
+
+	spin_lock_irqsave(&csis->q_lock, flags);
+	list_add_tail(&buf->list, &csis->ready_q);
+	buf->sequence_num = csis->sequence++;
+	spin_unlock_irqrestore(&csis->q_lock, flags);
+}
+
+static void fsd_csis_dma_set_vid_base_addr(struct fsd_csis *csis, int frm_no,
+		unsigned long addr)
+{
+	unsigned int dma_addr;
+
+	dma_addr = FSD_CSIS_DMA_ADDR1(csis->current_vc);
+	dma_addr = dma_addr + (frm_no * 4);
+	mutex_lock(&csis->mutex_csis_dma_reg);
+	writel(addr, csis->dma_base + dma_addr);
+	mutex_unlock(&csis->mutex_csis_dma_reg);
+}
+
+static void fsd_csis_add_to_ring_buffer(struct fsd_csis *csis,
+		struct fsd_csis_vb2_buffer *buf, uint8_t index)
+{
+	uint8_t modulo_addr;
+	unsigned int i;
+
+	for (i = 0; i < FSD_CSIS_NB_DMA_OUT_CH;
+			i += FSD_CSIS_NB_OF_BUFS_ON_DMA_CHANNELS) {
+		modulo_addr = (index + i) % FSD_CSIS_NB_DMA_OUT_CH;
+		csis->frame[modulo_addr] = buf;
+		csis->frame_addr[modulo_addr] =
+			vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0);
+		fsd_csis_dma_set_vid_base_addr(csis, modulo_addr,
+				csis->frame_addr[modulo_addr]);
+	}
+}
+
+static int fsd_csis_get_vc(struct fsd_csis *csis)
+{
+	struct v4l2_mbus_frame_desc fd = { };
+	struct media_pad *remote_pad;
+	int ret;
+
+	remote_pad = media_pad_remote_pad_unique(&csis->subdev.pad[FSD_CSIS_PAD_SINK]);
+	ret = v4l2_subdev_call(csis->source.subdev, pad, get_frame_desc, remote_pad->index, &fd);
+	if (ret < 0 && ret != -ENOIOCTLCMD) {
+		dev_err(csis->dev, "get_frame_desc failed on source subdev\n");
+		return ret;
+	}
+
+	/* If remote subdev does not implement ..get_frame_desc default to VC0 */
+	if (ret == -ENOIOCTLCMD)
+		return 0;
+
+	if (!fd.num_entries) {
+		dev_err(csis->dev, "get_frame_desc returned zero entries\n");
+		return -EINVAL;
+	}
+
+	return fd.entry[0].bus.csi2.vc;
+}
+
+static int fsd_start_streaming(struct vb2_queue *q, unsigned int count)
+{
+	struct fsd_csis *csis = vb2_get_drv_priv(q);
+	struct fsd_csis_vb2_buffer *buf, *tmp;
+	unsigned long flags;
+	uint8_t i;
+	int ret;
+
+	mutex_lock(&csis->mdev.graph_mutex);
+
+	ret = __video_device_pipeline_start(csis->vdev, &csis->pipe);
+	if (ret)
+		goto err_unlock;
+
+	ret = fsd_csis_get_vc(csis);
+
+	if (ret < 0)
+		goto err_unlock;
+
+	csis->current_vc = ret;
+
+	ret = v4l2_subdev_enable_streams(&csis->subdev.sd, FSD_CSIS_PAD_SRC,
+					BIT(0));
+	if (ret) {
+		dev_err(csis->dev, "stream on failed in subdev\n");
+		goto err_stop;
+	}
+
+	mutex_unlock(&csis->mdev.graph_mutex);
+	fsd_csis_set_dma_clk(csis);
+	fsd_csis_set_dma_format(csis, csis->vdev_cc);
+
+	for (i = 0; i < FSD_CSIS_NB_OF_BUFS_ON_DMA_CHANNELS; i++) {
+
+		spin_lock_irqsave(&csis->q_lock, flags);
+		if (list_empty(&csis->ready_q)) {
+			spin_unlock_irqrestore(&csis->q_lock, flags);
+			dev_err(csis->dev, "Failed to fill buffer address!\n");
+			return -EIO;
+		}
+
+		buf = list_entry(csis->ready_q.next, struct fsd_csis_vb2_buffer, list);
+		list_del(&buf->list);
+		fsd_csis_add_to_ring_buffer(csis, buf, i);
+		spin_unlock_irqrestore(&csis->q_lock, flags);
+	}
+
+	fsd_csis_dma_enable(csis, true);
+
+	return 0;
+err_stop:
+	v4l2_subdev_disable_streams(&csis->subdev.sd, FSD_CSIS_PAD_SRC,
+					BIT(0));
+	__video_device_pipeline_stop(csis->vdev);
+err_unlock:
+	mutex_unlock(&csis->mdev.graph_mutex);
+
+	spin_lock_irqsave(&csis->q_lock, flags);
+	list_for_each_entry_safe(buf, tmp, &csis->ready_q, list) {
+		list_del(&buf->list);
+		vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_QUEUED);
+	}
+	spin_unlock_irqrestore(&csis->q_lock, flags);
+
+	dev_err(csis->dev, "pipeline start failed with %d\n", ret);
+	return ret;
+}
+
+/**
+ * fsd_stop_streaming() - stop streaming for CSI context
+ * @q: pointer to vb2_queue in use
+ * Return: none
+ */
+static void fsd_stop_streaming(struct vb2_queue *q)
+{
+	unsigned long flags;
+	struct fsd_csis *csis = vb2_get_drv_priv(q);
+	struct fsd_csis_vb2_buffer *buf, *tmp;
+	unsigned int timeout_cnt = 0;
+	int i;
+	void __iomem *dma_act_ctrl = 0;
+
+	fsd_csis_dma_enable(csis, false);
+
+	dma_act_ctrl = csis->dma_base + FSD_CSIS_DMA_ACT_CTRL(csis->current_vc);
+
+	while ((readl(dma_act_ctrl) & 0x1) == 0x0) {
+		if (timeout_cnt > 50) {
+			dev_dbg(csis->dev, "DMA did not finish in 500ms.\n");
+			break;
+		}
+		usleep_range(10000, 20000); /* Wait min 10ms, max 20ms */
+		timeout_cnt++;
+	}
+
+	mutex_lock(&csis->mdev.graph_mutex);
+	v4l2_subdev_disable_streams(&csis->subdev.sd, FSD_CSIS_PAD_SRC,
+					BIT(0));
+	__video_device_pipeline_stop(csis->vdev);
+	mutex_unlock(&csis->mdev.graph_mutex);
+	/*
+	 * If still DMA operation exists after disabled irq, it will
+	 * update dma_done part in interrupt source register. For next
+	 * streaming session, this could be interpreted as current session's
+	 * first frame done. To prevent this incorrect dma_done receiving,
+	 * clearing interrupt source register here.
+	 */
+
+	/* Release all active buffers */
+	spin_lock_irqsave(&csis->q_lock, flags);
+	list_for_each_entry_safe(buf, tmp, &csis->ready_q, list) {
+		list_del(&buf->list);
+		vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
+	}
+	spin_unlock_irqrestore(&csis->q_lock, flags);
+
+	for (i = 0; i < FSD_CSIS_NB_OF_BUFS_ON_DMA_CHANNELS; i++) {
+		buf = csis->frame[i];
+		if (buf)
+			vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
+	}
+}
+
+static int fsd_csis_video_open(struct file *file)
+{
+	struct fsd_csis *csis = video_drvdata(file);
+	int ret;
+	struct vb2_queue *q = &csis->q;
+
+	if (vb2_is_busy(q)) {
+		dev_err(csis->dev, "device busy\n");
+		return -EBUSY;
+	}
+
+	ret = pm_runtime_resume_and_get(csis->dev);
+	if (ret < 0)
+		return ret;
+
+	ret = v4l2_fh_open(file);
+
+	if (ret) {
+		dev_err(csis->dev, "v4l2_fh_open failed\n");
+		goto err;
+	}
+
+	return ret;
+
+err:
+	pm_runtime_put(csis->dev);
+	return ret;
+}
+
+static void fsd_csis_irq_worker(struct fsd_csis *csis)
+{
+	struct fsd_csis_vb2_buffer *buf_from;
+	struct fsd_csis_vb2_buffer *buf_to;
+	struct v4l2_subdev *subdev = csis->source.subdev;
+	uint8_t i;
+	void __iomem *dma_act_ctrl;
+	unsigned long flags;
+
+	dma_act_ctrl = csis->dma_base + FSD_CSIS_DMA_ACT_CTRL(csis->current_vc);
+	csis->current_dma_ptr = readl(dma_act_ctrl);
+	csis->current_dma_ptr = get_bits(csis->current_dma_ptr,
+					FSD_CSIS_ACTIVE_DMA_FRAMEPTR_MASK);
+
+	v4l2_subdev_call(subdev, core, command, 5,
+			&csis->current_frame_counter);
+
+	if (csis->dma_error) {
+		dev_err(csis->dev, "prev_dma: %d, cur_dma: %d, prev_frm: %d, cur_frm: %d\n",
+				csis->prev_dma_ptr, csis->current_dma_ptr,
+				csis->prev_frame_counter, csis->current_frame_counter);
+		csis->prev_dma_ptr = csis->current_dma_ptr;
+		goto update_prev_counters;
+	}
+
+	if (csis->current_dma_ptr >= csis->prev_dma_ptr)
+		csis->number_of_ready_bufs =
+			csis->current_dma_ptr - csis->prev_dma_ptr;
+	else
+		csis->number_of_ready_bufs =
+			FSD_CSIS_NB_DMA_OUT_CH - csis->prev_dma_ptr
+			+ csis->current_dma_ptr;
+
+
+	if ((csis->number_of_ready_bufs >= FSD_CSIS_NB_OF_BUFS_ON_DMA_CHANNELS)
+			|| ((csis->current_frame_counter - csis->prev_frame_counter)
+				>= FSD_CSIS_NB_DMA_OUT_CH)) {
+		/* In case of CSIS_NB_OF_BUFS_ON_DMA_CHANNELS or CSIS_NUM_DMA_OUT_CH number
+		 * of frames delays or more, set how many recent frames are ready to be read
+		 * in the next interrupt. This cannot be more than
+		 * CSIS_NB_OF_BUFS_ON_DMA_CHANNELS-1 frames.
+		 */
+		csis->number_of_ready_bufs = FSD_CSIS_NB_OF_BUFS_ON_DMA_CHANNELS - 1;
+		csis->prev_dma_ptr = (csis->current_dma_ptr -
+					FSD_CSIS_NB_OF_BUFS_ON_DMA_CHANNELS)
+					& (FSD_CSIS_NB_DMA_OUT_CH - 1);
+		dev_err(csis->dev, "interrupt delayed %d frames\n",
+					csis->number_of_ready_bufs);
+	}
+
+	if (csis->number_of_ready_bufs == 0) {
+		dev_err(csis->dev, "Interrupt burst number_of_ready_bufs: %d\n",
+							csis->number_of_ready_bufs);
+		goto update_prev_counters;
+	} else {
+		if (csis->number_of_ready_bufs > 1) {
+			/*
+			 * Interrupt has been missed. Do not populate DMA_ACT_CTRL pointer.
+			 * Notify buffers ready until (DMA_ACT_CTRL - 1) pointer.
+			 * Because,the delayed interrupt might be arrived in DMA active
+			 * time.
+			 */
+			csis->number_of_ready_bufs--;
+			dev_err(csis->dev, "interrupt got delayed %d frames\n",
+						csis->number_of_ready_bufs);
+		}
+	}
+
+	for (i = 0; i < csis->number_of_ready_bufs; i++) {
+		bool is_same_modulo;
+
+		csis->prev_dma_ptr = (csis->prev_dma_ptr + 1) % FSD_CSIS_NB_DMA_OUT_CH;
+		is_same_modulo = !((csis->prev_dma_ptr - (csis->current_dma_ptr + 1)) %
+					FSD_CSIS_NB_OF_BUFS_ON_DMA_CHANNELS);
+
+		spin_lock_irqsave(&csis->q_lock, flags);
+
+		/*
+		 * Before dequeuing buffer from DMA at least
+		 * one buffer should be ready in vb2_queue
+		 */
+		if (list_empty(&csis->ready_q)) {
+			spin_unlock_irqrestore(&csis->q_lock, flags);
+			csis->prev_dma_ptr = csis->current_dma_ptr;
+			goto update_prev_counters;
+
+		} else {
+
+			buf_from = list_entry(csis->ready_q.next,
+					struct fsd_csis_vb2_buffer, list);
+			list_del(&buf_from->list);
+		}
+
+		spin_unlock_irqrestore(&csis->q_lock, flags);
+
+		buf_to = csis->frame[csis->prev_dma_ptr];
+
+		if (is_same_modulo) {
+			if (csis->current_dma_ptr != fsd_csis_current_dma_ptr(csis)) {
+				spin_lock_irqsave(&csis->q_lock, flags);
+				list_add_tail(&buf_from->list, &csis->ready_q);
+				spin_unlock_irqrestore(&csis->q_lock, flags);
+				continue;
+			}
+		}
+
+		fsd_csis_add_to_ring_buffer(csis, buf_from, csis->prev_dma_ptr);
+
+		if (buf_to) {
+			buf_to->vb.vb2_buf.timestamp = ktime_get_ns();
+			vb2_buffer_done(&buf_to->vb.vb2_buf,
+					VB2_BUF_STATE_DONE);
+		}
+
+	}
+
+update_prev_counters:
+	csis->prev_frame_counter = csis->current_frame_counter;
+
+}
+
+static irqreturn_t csis_irq_handler(int irq_csis, void *data)
+{
+	struct fsd_csis *csis = data;
+	struct v4l2_subdev *subdev = csis->source.subdev;
+	unsigned int vc;
+	unsigned int int_src1 = 0x0;
+	unsigned int int1_err = 0x0;
+	unsigned int dma_error = 0x0, dma_err_code = 0x0, dma_error_vc = 0x0;
+	unsigned int err = 0x0;
+	unsigned int dma_frame_end = 0x0, dma_frame_end_vc = 0x0, dma_frame_start = 0x0;
+	int i;
+
+	vc = csis->current_vc;
+
+	v4l2_subdev_call(subdev, core, command, 2, &int_src1);
+	int1_err = get_bits(int_src1, FSD_CSIS_INT_SRC1_ERR_ALL_MASK);
+
+	dma_frame_start = get_bits(int_src1, FSD_CSIS_DMA_FRM_START_MASK);
+	dma_frame_end = get_bits(int_src1, FDS_CSIS_DMA_FRM_END_MASK);
+
+	if (int1_err) {
+		err = get_bits(int_src1, FSD_CSIS_DMA_OTF_OVERLAP_MASK);
+		if (err)
+			dev_err(csis->dev, "DMA OTF OVERLAP %x\n", err);
+
+		dma_error = get_bits(int_src1, FSD_CSIS_DMA_ERROR_MASK);
+
+		if (dma_error) {
+			dev_err(csis->dev, "DMA ERROR %x\n", dma_error);
+			dma_err_code = readl(csis->dma_base + FSD_CSIS_DMA_ERR_CODE);
+			dev_err(csis->dev, "Error code %x", dma_err_code);
+		}
+	}
+
+	if (dma_frame_end || dma_error) {
+
+		for (i = 0; i < FSD_CSIS_MAX_VC; i++) {
+			dma_frame_end_vc = (dma_frame_end >> i) & 0x01;
+			if (dma_error) {
+				dma_error_vc = int_src1 & (FSD_CSIS_DMA_CH0_MASK << i);
+				dma_error_vc |= ((dma_err_code & (FSD_CSIS_DMAFIFO_FULL_MASK |
+								FSD_CSIS_TRXFIFO_FULL_MASK |
+								0x01 << i)) << 18);
+			}
+
+			if (dma_frame_end_vc || dma_error_vc) {
+				csis->dma_error = dma_error_vc;
+				fsd_csis_irq_worker(csis);
+			}
+		}
+	}
+
+	v4l2_subdev_call(subdev, core, command, 3, &int_src1);
+
+	return IRQ_HANDLED;
+}
+
+static int fsd_csis_video_release(struct file *file)
+{
+	struct fsd_csis *csis = video_drvdata(file);
+	int ret;
+
+	ret = vb2_fop_release(file);
+
+	if (ret)
+		return ret;
+
+	pm_runtime_put(csis->dev);
+
+	return ret;
+}
+
+static int fsd_csis_video_querycap(struct file *file, void *priv,
+					struct v4l2_capability *cap)
+{
+	struct fsd_csis *csis = video_drvdata(file);
+
+	strscpy(cap->driver, FSD_CSIS_MODULE_NAME, sizeof(cap->driver));
+	strscpy(cap->card, FSD_CSIS_MODULE_NAME, sizeof(cap->card));
+
+	snprintf(cap->bus_info, sizeof(cap->bus_info),
+			"platform:%s", dev_name(csis->dev));
+	return 0;
+}
+
+static int fsd_csis_video_enum_fmt_vid_cap(struct file *file, void *priv,
+					struct v4l2_fmtdesc *f)
+{
+	unsigned int index = f->index;
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(pixel_formats); i++) {
+		const struct fsd_csis_pixfmt *fmt = &pixel_formats[i];
+
+		if (f->mbus_code) {
+			unsigned int j;
+
+			if (!fmt->codes)
+				continue;
+
+			for (j = 0; fmt->codes[j]; j++) {
+				if (f->mbus_code == fmt->codes[j])
+					break;
+			}
+
+			if (!fmt->codes[j])
+				continue;
+		}
+
+		if (index == 0) {
+			f->pixelformat = fmt->fourcc;
+			return 0;
+		}
+
+		index--;
+	}
+
+	return -EINVAL;
+}
+
+/*
+ * Search in the pixel_formats[] array for an entry with the given fourcc
+ * return it.
+ */
+static const struct fsd_csis_pixfmt *fsd_csis_find_pixel_format(u32 fourcc)
+{
+	const struct fsd_csis_pixfmt *fmt;
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(pixel_formats); i++) {
+		fmt = &pixel_formats[i];
+
+		if (fmt->fourcc == fourcc)
+			return fmt;
+	}
+
+	return NULL;
+}
+
+/*
+ * Search in the pixel_formats[] array for an entry with the given media
+ * bus code and return it.
+ */
+static const struct fsd_csis_pixfmt *fsd_csis_find_mbus_format(u32 code)
+{
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(pixel_formats); i++) {
+		const struct fsd_csis_pixfmt *fmt = &pixel_formats[i];
+		unsigned int j;
+
+		if (!fmt->codes)
+			continue;
+
+		for (j = 0; fmt->codes[j]; j++) {
+			if (code == fmt->codes[j])
+				return fmt;
+		}
+	}
+
+	return NULL;
+}
+
+static int fsd_csis_mbus_fmt_to_pix_fmt(struct v4l2_pix_format *pix,
+					const struct v4l2_mbus_framefmt *mbus,
+					const struct fsd_csis_pixfmt *cc)
+{
+	u32 width;
+	u32 stride;
+
+	if (!cc) {
+		cc = fsd_csis_find_mbus_format(mbus->code);
+		if (!cc)
+			return -EINVAL;
+	}
+
+	/* Round up width for minimum burst size */
+	width = round_up(mbus->width, 8);
+
+	/* Round up stride for IDMAC line start address alignment */
+	stride = round_up((width * cc->bpp) >> 3, 8);
+
+	pix->width = width;
+	pix->height = mbus->height;
+	pix->pixelformat = cc->fourcc;
+	pix->colorspace = mbus->colorspace;
+	pix->xfer_func = mbus->xfer_func;
+	pix->ycbcr_enc = mbus->ycbcr_enc;
+	pix->quantization = mbus->quantization;
+	pix->field = mbus->field;
+	pix->bytesperline = stride;
+	pix->sizeimage = stride * pix->height;
+
+	return 0;
+}
+
+static const struct fsd_csis_pixfmt *__fsd_csis_video_try_fmt_vid_cap(
+		struct fsd_csis *csis, struct v4l2_pix_format *pixfmt)
+{
+	struct v4l2_mbus_framefmt fmt_src;
+	const struct fsd_csis_pixfmt *cc;
+	struct v4l2_rect *compose = &csis->vdev_compose;
+
+	/*
+	 * Find the pixel format, default to the first supported format if not
+	 * found.
+	 */
+	cc = fsd_csis_find_pixel_format(pixfmt->pixelformat);
+
+	if (!cc) {
+		pixfmt->pixelformat = FSD_CSIS_DEF_PIX_FORMAT;
+		pixfmt->height = FSD_CSIS_DEF_PIX_HEIGHT;
+		pixfmt->width = FSD_CSIS_DEF_PIX_WIDTH;
+		pixfmt->colorspace = V4L2_COLORSPACE_SRGB;
+		pixfmt->field = V4L2_FIELD_NONE;
+		cc = fsd_csis_find_pixel_format(pixfmt->pixelformat);
+	}
+
+	v4l2_fill_mbus_format(&fmt_src, pixfmt, cc->codes[0]);
+	fsd_csis_mbus_fmt_to_pix_fmt(pixfmt, &fmt_src, cc);
+
+	compose->width = fmt_src.width;
+	compose->height = fmt_src.height;
+
+	csis->vdev_fmt = *pixfmt;
+	return cc;
+}
+
+static int fsd_csis_video_try_fmt_vid_cap(struct file *file, void *fh,
+						struct v4l2_format *f)
+{
+	struct fsd_csis *csis = video_drvdata(file);
+
+	__fsd_csis_video_try_fmt_vid_cap(csis, &f->fmt.pix);
+	return 0;
+}
+
+static int fsd_csis_video_s_fmt_vid_cap(struct file *file, void *priv,
+		struct v4l2_format *f)
+{
+	struct fsd_csis *csis = video_drvdata(file);
+	struct v4l2_subdev *sd = &csis->subdev.sd;
+	const struct fsd_csis_pixfmt *cc;
+	struct vb2_queue *q = &csis->q;
+	int ret;
+	struct v4l2_subdev_format fmt = {
+		.which = V4L2_SUBDEV_FORMAT_ACTIVE,
+		.pad = 0,
+	};
+
+	if (vb2_is_busy(q)) {
+		dev_err(csis->dev, "%s queue busy\n", __func__);
+		return -EBUSY;
+	}
+
+	cc = __fsd_csis_video_try_fmt_vid_cap(csis, &f->fmt.pix);
+	v4l2_fill_mbus_format(&fmt.format, &f->fmt.pix, cc->codes[0]);
+	ret = v4l2_subdev_call(sd, pad, set_fmt, sd->active_state, &fmt);
+
+	if (ret < 0) {
+		dev_err(csis->dev, "subdev format set failed %d\n", ret);
+		return ret;
+	}
+
+	csis->vdev_cc = cc;
+	csis->vdev_fmt = f->fmt.pix;
+	return 0;
+}
+
+static int fsd_csis_video_g_fmt_vid_cap(struct file *file, void *priv,
+		struct v4l2_format *f)
+{
+	struct fsd_csis *csis = video_drvdata(file);
+
+	f->fmt.pix = csis->vdev_fmt;
+
+	return 0;
+}
+
+static const struct vb2_ops fsd_csis_video_qops = {
+	.queue_setup            = fsd_queue_setup,
+	.buf_prepare            = fsd_buffer_prepare,
+	.buf_queue              = fsd_buffer_queue,
+	.start_streaming        = fsd_start_streaming,
+	.stop_streaming         = fsd_stop_streaming,
+	.wait_prepare           = vb2_ops_wait_prepare,
+	.wait_finish            = vb2_ops_wait_finish,
+};
+
+static const struct v4l2_ioctl_ops fsd_csis_video_ioctl_ops = {
+	.vidioc_querycap      = fsd_csis_video_querycap,
+
+	.vidioc_enum_fmt_vid_cap  = fsd_csis_video_enum_fmt_vid_cap,
+
+	.vidioc_try_fmt_vid_cap   = fsd_csis_video_try_fmt_vid_cap,
+	.vidioc_s_fmt_vid_cap     = fsd_csis_video_s_fmt_vid_cap,
+	.vidioc_g_fmt_vid_cap     = fsd_csis_video_g_fmt_vid_cap,
+
+	.vidioc_reqbufs       = vb2_ioctl_reqbufs,
+	.vidioc_querybuf      = vb2_ioctl_querybuf,
+	.vidioc_qbuf          = vb2_ioctl_qbuf,
+	.vidioc_expbuf        = vb2_ioctl_expbuf,
+	.vidioc_dqbuf         = vb2_ioctl_dqbuf,
+	.vidioc_prepare_buf   = vb2_ioctl_prepare_buf,
+	.vidioc_create_bufs   = vb2_ioctl_create_bufs,
+	.vidioc_streamon      = vb2_ioctl_streamon,
+	.vidioc_streamoff     = vb2_ioctl_streamoff,
+};
+
+/**
+ * V4L2 File operations
+ */
+static const struct v4l2_file_operations fsd_csis_video_fops = {
+	.owner          = THIS_MODULE,
+	.open           = fsd_csis_video_open,
+	.release        = fsd_csis_video_release,
+	.read           = vb2_fop_read,
+	.poll           = vb2_fop_poll,
+	.unlocked_ioctl = video_ioctl2,
+	.mmap           = vb2_fop_mmap,
+};
+
+static int fsd_csi_notify_bound(struct v4l2_async_notifier *notifier,
+				struct v4l2_subdev *subdev,
+				struct v4l2_async_connection *asd)
+{
+	struct fsd_csis *csis = notifier_to_csis(notifier);
+	struct media_pad *sink = &csis->subdev.pad[FSD_CSIS_PAD_SINK];
+	struct media_pad *source;
+	int ret;
+
+	dev_dbg(csis->dev, "Hooked csis subdevice: %s to parent\n",
+			subdev->name);
+
+	ret = v4l2_create_fwnode_links_to_pad(subdev, sink, MEDIA_LNK_FL_ENABLED);
+
+	if (ret)
+		return ret;
+
+	source = media_pad_remote_pad_unique(sink);
+	if (IS_ERR(source)) {
+		dev_err(csis->dev, "No connected source pad\n");
+		return PTR_ERR(source);
+	}
+
+	csis->source.subdev = subdev;
+	csis->source.pad = source;
+
+	return 0;
+}
+
+static const struct v4l2_async_notifier_operations fsd_csi_notify_ops = {
+	.bound = fsd_csi_notify_bound,
+};
+
+static const struct media_device_ops fsd_csis_media_ops = {
+	.link_notify = v4l2_pipeline_link_notify,
+};
+
+static const struct media_entity_operations fsd_csis_entity_ops = {
+	.link_validate  = v4l2_subdev_link_validate,
+	.get_fwnode_pad = v4l2_subdev_get_fwnode_pad_1_to_1,
+};
+
+static int fsd_csis_media_dev_init(struct fsd_csis *csis)
+{
+	int ret;
+
+
+	strscpy(csis->mdev.model, "fsd-csis-media", sizeof(csis->mdev.model));
+	csis->mdev.ops = &fsd_csis_media_ops;
+	csis->mdev.dev = csis->dev;
+
+	csis->v4l2_dev.mdev = &csis->mdev;
+	strscpy(csis->v4l2_dev.name, "fsd-csis-media",
+			sizeof(csis->v4l2_dev.name));
+	snprintf(csis->mdev.bus_info, sizeof(csis->mdev.bus_info),
+			"platform:%s", dev_name(csis->mdev.dev));
+
+	media_device_init(&csis->mdev);
+
+	ret = v4l2_device_register(csis->dev, &csis->v4l2_dev);
+
+	if (ret < 0) {
+		v4l2_err(&csis->v4l2_dev,
+				"Failed to register v4l2_device: %d\n", ret);
+		goto cleanup;
+	}
+
+	return 0;
+
+cleanup:
+	media_device_cleanup(&csis->mdev);
+
+	return ret;
+}
+
+static void fsd_csis_media_cleanup(struct fsd_csis *csis)
+{
+	v4l2_device_unregister(&csis->v4l2_dev);
+	media_device_unregister(&csis->mdev);
+	v4l2_subdev_cleanup(&csis->subdev.sd);
+	media_device_cleanup(&csis->mdev);
+}
+
+static int fsd_csis_video_init(struct fsd_csis *csis)
+{
+	struct video_device *vdev;
+	struct vb2_queue *vq;
+	int ret;
+
+	mutex_init(&csis->vdev_mutex);
+	INIT_LIST_HEAD(&csis->ready_q);
+	spin_lock_init(&csis->q_lock);
+
+	/* Allocate and initialize the video device.*/
+	vdev = video_device_alloc();
+	if (!vdev)
+		return -ENOMEM;
+
+	vdev->fops = &fsd_csis_video_fops;
+	vdev->ioctl_ops = &fsd_csis_video_ioctl_ops;
+	vdev->minor = -1;
+	vdev->release = video_device_release;
+	vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
+	vdev->lock = &csis->vdev_mutex;
+	vdev->queue = &csis->q;
+
+	snprintf(vdev->name, sizeof(vdev->name), "%s capture", csis->subdev.sd.name);
+
+	video_set_drvdata(vdev, csis);
+	csis->vdev = vdev;
+
+	/* Initialize the video device pad. */
+	csis->vdev_pad.flags = MEDIA_PAD_FL_SINK;
+
+	ret = media_entity_pads_init(&vdev->entity, 1, &csis->vdev_pad);
+	if (ret) {
+		video_device_release(vdev);
+		return ret;
+	}
+
+	/* Initialize the vb2 queue. */
+	vq = &csis->q;
+	vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
+	vq->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF;
+	vq->drv_priv = csis;
+	vq->buf_struct_size = sizeof(struct fsd_csis_vb2_buffer);
+	vq->ops = &fsd_csis_video_qops;
+	vq->mem_ops = &vb2_dma_contig_memops;
+	vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
+	vq->lock = &csis->vdev_mutex;
+	vq->min_reqbufs_allocation = FSD_CSIS_NB_OF_BUFS_ON_DMA_CHANNELS + 1;
+	vq->min_queued_buffers = FSD_CSIS_NB_MIN_CH;
+	vq->dev = csis->dev;
+
+	ret = vb2_queue_init(vq);
+	if (ret) {
+		dev_err(csis->dev, "vb2_queue_init failed\n");
+		video_device_release(vdev);
+		return ret;
+	}
+
+	return 0;
+}
+
+static void fsd_csis_video_init_format(struct fsd_csis *csis)
+{
+
+	csis->vdev_fmt.width = FSD_CSIS_DEF_PIX_WIDTH;
+	csis->vdev_fmt.height = FSD_CSIS_DEF_PIX_HEIGHT;
+	csis->vdev_fmt.pixelformat = FSD_CSIS_DEF_PIX_FORMAT;
+	csis->vdev_fmt.colorspace = V4L2_COLORSPACE_SRGB;
+	csis->vdev_fmt.field = V4L2_FIELD_NONE;
+
+	csis->vdev_cc = fsd_csis_find_pixel_format(csis->vdev_fmt.pixelformat);
+
+	csis->vdev_fmt.bytesperline = bytes_per_line(FSD_CSIS_DEF_PIX_WIDTH,
+					csis->vdev_cc->bpp);
+	csis->vdev_fmt.sizeimage = csis->vdev_fmt.bytesperline *
+					csis->vdev_fmt.height;
+}
+
+static int fsd_csis_video_register(struct fsd_csis *csis)
+{
+	struct v4l2_subdev *sd = &csis->subdev.sd;
+	struct v4l2_device *v4l2_dev = sd->v4l2_dev;
+	struct video_device *vdev = csis->vdev;
+	int ret;
+
+	vdev->v4l2_dev = v4l2_dev;
+
+	/* Initialize the default format and compose rectangle. */
+	fsd_csis_video_init_format(csis);
+
+	/* Register the video device. */
+	ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1);
+	if (ret) {
+		dev_err(csis->dev, "Failed to register video device\n");
+		return ret;
+	}
+
+	dev_info(csis->dev, "Registered %s as /dev/%s\n", vdev->name,
+			video_device_node_name(vdev));
+
+	/* Create the link from the CSI subdev to the video device. */
+	ret = media_create_pad_link(&sd->entity, FSD_CSIS_PAD_SRC,
+			&vdev->entity, 0, MEDIA_LNK_FL_IMMUTABLE |
+			MEDIA_LNK_FL_ENABLED);
+	if (ret) {
+		dev_err(csis->dev, "failed to create link to device node\n");
+		video_unregister_device(vdev);
+		return ret;
+	}
+
+	return 0;
+}
+
+static void fsd_csis_video_unregister(struct fsd_csis *csis)
+{
+	media_entity_cleanup(&csis->vdev->entity);
+	video_unregister_device(csis->vdev);
+}
+
+static int fsd_csis_registered(struct v4l2_subdev *sd)
+{
+	struct fsd_csis *csis = v4l2_get_subdevdata(sd);
+	int ret;
+
+	ret = fsd_csis_video_init(csis);
+	if (ret)
+		return ret;
+
+	ret = fsd_csis_video_register(csis);
+	if (ret)
+		return ret;
+
+	ret = v4l2_device_register_subdev_nodes(&csis->v4l2_dev);
+	if (ret)
+		goto err_unregister;
+
+	ret = media_device_register(&csis->mdev);
+	if (ret)
+		goto err_unregister;
+
+	return 0;
+
+err_unregister:
+	fsd_csis_video_unregister(csis);
+
+	return ret;
+}
+
+static void fsd_csis_unregistered(struct v4l2_subdev *sd)
+{
+	struct fsd_csis *csis = v4l2_get_subdevdata(sd);
+
+	fsd_csis_video_unregister(csis);
+}
+
+static int fsd_csis_sd_set_fmt(struct v4l2_subdev *sd,
+				struct v4l2_subdev_state *sd_state,
+				struct v4l2_subdev_format *sdformat)
+{
+	struct fsd_csis *csis = v4l2_get_subdevdata(sd);
+	struct v4l2_subdev *subdev = csis->source.subdev;
+	struct v4l2_mbus_framefmt *fmt;
+	const struct fsd_csis_pixfmt *cc;
+
+	if (sdformat->which == V4L2_SUBDEV_FORMAT_ACTIVE && csis->is_streaming)
+		return -EBUSY;
+
+	if (sdformat->pad == FSD_CSIS_PAD_SRC)
+		return v4l2_subdev_get_fmt(sd, sd_state, sdformat);
+
+	if (sdformat->pad != FSD_CSIS_PAD_SINK)
+		return -EINVAL;
+
+	cc = fsd_csis_find_mbus_format(sdformat->format.code);
+	if (!cc)
+		cc = fsd_csis_find_mbus_format(FSD_CSIS_DEF_MBUS_CODE);
+
+	fmt = v4l2_subdev_state_get_format(sd_state, sdformat->pad);
+
+	fmt->code = cc->codes[0];
+	fmt->width = sdformat->format.width;
+	fmt->height = sdformat->format.height;
+	fmt->field = V4L2_FIELD_NONE;
+
+	sdformat->format = *fmt;
+
+	/* Propagate the format from sink to source. */
+	fmt = v4l2_subdev_state_get_format(sd_state, FSD_CSIS_PAD_SRC);
+	*fmt = sdformat->format;
+
+	return v4l2_subdev_call(subdev, pad, set_fmt, subdev->active_state, sdformat);
+}
+
+static int __fsd_csis_sd_set_routing(struct v4l2_subdev *sd,
+					struct v4l2_subdev_state *state,
+					struct v4l2_subdev_krouting *routing)
+{
+	struct v4l2_subdev_route *route;
+	int ret;
+
+	ret = v4l2_subdev_routing_validate(sd, routing,
+			V4L2_SUBDEV_ROUTING_ONLY_1_TO_1);
+	if (ret)
+		return ret;
+
+	ret = v4l2_subdev_set_routing(sd, state, routing);
+	if (ret)
+		return ret;
+
+	for_each_active_route(&state->routing, route) {
+		const struct v4l2_mbus_framefmt *def_fmt;
+		struct v4l2_mbus_framefmt *fmt;
+
+		def_fmt = &fsd_csis_default_format;
+
+		fmt = v4l2_subdev_state_get_format(state, route->sink_pad,
+				route->sink_stream);
+		*fmt = *def_fmt;
+		fmt = v4l2_subdev_state_get_format(state, route->source_pad,
+				route->source_stream);
+		*fmt = *def_fmt;
+	}
+
+	return 0;
+}
+
+static int fsd_csis_sd_set_routing(struct v4l2_subdev *sd,
+					struct v4l2_subdev_state *state,
+					enum v4l2_subdev_format_whence which,
+					struct v4l2_subdev_krouting *routing)
+{
+	struct fsd_csis *csis = v4l2_get_subdevdata(sd);
+
+	if (which == V4L2_SUBDEV_FORMAT_ACTIVE && csis->is_streaming)
+		return -EBUSY;
+
+	return __fsd_csis_sd_set_routing(sd, state, routing);
+}
+
+static int fsd_csis_sd_enable_streams(struct v4l2_subdev *sd,
+					struct v4l2_subdev_state *state,
+					u32 pad, u64 streams_mask)
+{
+
+	struct fsd_csis *csis = v4l2_get_subdevdata(sd);
+
+	return v4l2_subdev_enable_streams(csis->source.subdev,
+					FSD_CSIS_PAD_SRC, BIT(0));
+}
+
+static int fsd_csis_sd_disable_streams(struct v4l2_subdev *sd,
+					struct v4l2_subdev_state *state,
+					u32 pad, u64 streams_mask)
+{
+	struct fsd_csis *csis = v4l2_get_subdevdata(sd);
+
+	return v4l2_subdev_disable_streams(csis->source.subdev,
+					FSD_CSIS_PAD_SRC, BIT(0));
+}
+
+static int fsd_csis_init_state(struct v4l2_subdev *sd,
+				struct v4l2_subdev_state *state)
+{
+	struct v4l2_subdev_route routes[] = {
+		{
+			.sink_pad = FSD_CSIS_PAD_SINK,
+			.sink_stream = 0,
+			.source_pad = FSD_CSIS_PAD_SRC,
+			.source_stream = 0,
+			.flags = V4L2_SUBDEV_ROUTE_FL_ACTIVE,
+		},
+	};
+
+	struct v4l2_subdev_krouting routing = {
+		.len_routes = ARRAY_SIZE(routes),
+		.num_routes = ARRAY_SIZE(routes),
+		.routes = routes,
+	};
+
+	return __fsd_csis_sd_set_routing(sd, state, &routing);
+}
+
+static const struct v4l2_subdev_internal_ops fsd_csis_internal_ops = {
+	.init_state	= fsd_csis_init_state,
+	.registered	= fsd_csis_registered,
+	.unregistered	= fsd_csis_unregistered,
+};
+
+static const struct v4l2_subdev_pad_ops fsd_csis_pad_ops = {
+	.get_fmt		= v4l2_subdev_get_fmt,
+	.set_fmt		= fsd_csis_sd_set_fmt,
+	.set_routing		= fsd_csis_sd_set_routing,
+	.enable_streams		= fsd_csis_sd_enable_streams,
+	.disable_streams	= fsd_csis_sd_disable_streams,
+};
+
+static const struct v4l2_subdev_ops fsd_csis_subdev_ops = {
+	.pad = &fsd_csis_pad_ops,
+};
+
+static int fsd_csis_media_init(struct fsd_csis *csis)
+{
+	struct v4l2_subdev *sd = &csis->subdev.sd;
+	int ret, i;
+
+	/* add media device */
+	ret = fsd_csis_media_dev_init(csis);
+	if (ret)
+		return ret;
+
+	v4l2_subdev_init(sd, &fsd_csis_subdev_ops);
+	v4l2_set_subdevdata(sd, csis);
+	sd->internal_ops = &fsd_csis_internal_ops;
+	sd->entity.ops = &fsd_csis_entity_ops;
+	sd->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
+	sd->dev = csis->dev;
+	sd->owner = THIS_MODULE;
+	sd->flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
+	snprintf(sd->name, sizeof(sd->name), "csis");
+
+	for (i = 0; i < FSD_CSIS_PADS_NUM; i++)
+		csis->subdev.pad[i].flags = (i == FSD_CSIS_PAD_SINK) ?
+			MEDIA_PAD_FL_SINK : MEDIA_PAD_FL_SOURCE;
+
+	ret = media_entity_pads_init(&sd->entity, FSD_CSIS_PADS_NUM,
+					csis->subdev.pad);
+
+	if (ret)
+		goto error;
+
+	ret = v4l2_subdev_init_finalize(sd);
+	if (ret)
+		goto error;
+
+	ret = v4l2_device_register_subdev(&csis->v4l2_dev, sd);
+	if (ret)
+		goto error;
+
+	return 0;
+error:
+	fsd_csis_media_cleanup(csis);
+	return ret;
+}
+
+static int fsd_csis_async_register(struct fsd_csis *csis)
+{
+	struct v4l2_async_connection *asd;
+	struct fwnode_handle *ep;
+	int ret;
+
+	v4l2_async_nf_init(&csis->notifier, &csis->v4l2_dev);
+
+	ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(csis->dev), 0, 0,
+						FWNODE_GRAPH_ENDPOINT_NEXT);
+
+	if (ep) {
+		asd = v4l2_async_nf_add_fwnode_remote(&csis->notifier, ep,
+						struct v4l2_async_connection);
+		fwnode_handle_put(ep);
+
+		if (IS_ERR(asd)) {
+			ret = PTR_ERR(asd);
+			/* OK if asd already exists */
+			if (ret != -EEXIST)
+				goto error;
+		}
+	}
+
+	csis->notifier.ops = &fsd_csi_notify_ops;
+
+	ret = v4l2_async_nf_register(&csis->notifier);
+	if (ret)
+		goto error;
+
+	return 0;
+
+error:
+	v4l2_async_nf_cleanup(&csis->notifier);
+	return ret;
+}
+
+static int fsd_csis_enable_pll(struct fsd_csis *csis)
+{
+	csis->pll = devm_clk_get(csis->dev, "pll");
+
+	if (IS_ERR(csis->pll))
+		return PTR_ERR(csis->pll);
+
+	return clk_prepare_enable(csis->pll);
+}
+
+static int fsd_csis_clk_get(struct fsd_csis *csis)
+{
+	int i;
+
+	csis->clks = devm_kcalloc(csis->dev, FSD_CSIS_NB_CLOCK, sizeof(*csis->clks), GFP_KERNEL);
+
+	if (!csis->clks)
+		return -ENOMEM;
+
+	for (i = 0; i < FSD_CSIS_NB_CLOCK; i++)
+		csis->clks[i].id = fsd_csis_clk_id[i];
+
+	return devm_clk_bulk_get(csis->dev, FSD_CSIS_NB_CLOCK, csis->clks);
+}
+
+static int fsd_csis_runtime_suspend(struct device *dev)
+{
+	struct fsd_csis *csis = dev_get_drvdata(dev);
+
+	clk_bulk_disable_unprepare(FSD_CSIS_NB_CLOCK, csis->clks);
+
+	return 0;
+}
+
+static int fsd_csis_runtime_resume(struct device *dev)
+{
+	struct fsd_csis *csis = dev_get_drvdata(dev);
+
+	return clk_bulk_prepare_enable(FSD_CSIS_NB_CLOCK, csis->clks);
+}
+
+static const struct dev_pm_ops fsd_csis_pm_ops = {
+	SET_RUNTIME_PM_OPS(fsd_csis_runtime_suspend, fsd_csis_runtime_resume,
+			NULL)
+};
+
+static int fsd_csis_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct fsd_csis *csis;
+	int ret = 0;
+	int irq;
+
+	csis = devm_kzalloc(dev, sizeof(*csis), GFP_KERNEL);
+	if (!csis)
+		return -ENOMEM;
+
+	csis->dev = dev;
+	csis->info = of_device_get_match_data(dev);
+
+	csis->dma_base = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(csis->dma_base))
+		return PTR_ERR(csis->dma_base);
+
+	irq = platform_get_irq(pdev, 0);
+	if (irq < 0)
+		return irq;
+
+	ret = devm_request_irq(dev, irq,
+			csis_irq_handler, IRQF_SHARED, pdev->name, csis);
+
+	ret = fsd_csis_clk_get(csis);
+	if (ret < 0)
+		return ret;
+
+	pm_runtime_enable(dev);
+	if (!pm_runtime_enabled(dev)) {
+		ret = fsd_csis_runtime_resume(dev);
+		if (ret < 0)
+			return ret;
+	}
+
+	platform_set_drvdata(pdev, csis);
+
+	ret = fsd_csis_enable_pll(csis);
+	if (ret)
+		return ret;
+
+	ret = fsd_csis_media_init(csis);
+	if (ret)
+		return ret;
+
+	ret = fsd_csis_async_register(csis);
+	if (ret)
+		goto err_media_cleanup;
+
+	return 0;
+
+err_media_cleanup:
+	fsd_csis_media_cleanup(csis);
+
+	return ret;
+}
+
+static void fsd_csis_remove(struct platform_device *pdev)
+{
+	struct fsd_csis *csis = platform_get_drvdata(pdev);
+
+	fsd_csis_media_cleanup(csis);
+
+	v4l2_async_nf_unregister(&csis->notifier);
+	v4l2_async_nf_cleanup(&csis->notifier);
+	v4l2_async_unregister_subdev(&csis->subdev.sd);
+
+	if (!pm_runtime_enabled(csis->dev))
+		fsd_csis_runtime_suspend(csis->dev);
+
+	pm_runtime_disable(csis->dev);
+	pm_runtime_set_suspended(csis->dev);
+}
+
+static const struct of_device_id fsd_csis_of_match[] = {
+	{ .compatible = "tesla,fsd-csis-media", },
+	{ },
+};
+
+MODULE_DEVICE_TABLE(of, fsd_csis_of_match);
+
+static struct platform_driver fsd_csis_driver = {
+	.probe		= fsd_csis_probe,
+	.remove		= fsd_csis_remove,
+	.driver		= {
+		.name		= FSD_CSIS_MODULE_NAME,
+		.of_match_table = of_match_ptr(fsd_csis_of_match),
+		.pm		= &fsd_csis_pm_ops,
+	},
+};
+
+module_platform_driver(fsd_csis_driver);
+
+MODULE_DESCRIPTION("FSD CSIS Driver");
+MODULE_AUTHOR("Inbaraj E <inbaraj.e@samsung.com>");
+MODULE_LICENSE("GPL");
+
-- 
2.49.0

Re: [PATCH v2 12/12] media: fsd-csis: Add support for FSD CSIS DMA

[Krzysztof Kozlowski]

On 14/08/2025 16:09, Inbaraj E wrote:
> FSD CSIS IP bundles DMA engine for receiving frames from MIPI-CSI2 bus.
> Add support internal DMA controller to capture the frames.
> 
> Signed-off-by: Inbaraj E <inbaraj.e@samsung.com>

I commented on order of patches and got more surprise - final driver
patch after DTS defconfig. It's really wrong order.

> ---
>  MAINTAINERS                                   |    8 +
>  drivers/media/platform/samsung/Kconfig        |    1 +
>  drivers/media/platform/samsung/Makefile       |    1 +
>  .../media/platform/samsung/fsd-csis/Kconfig   |   18 +
>  .../media/platform/samsung/fsd-csis/Makefile  |    3 +
>  .../platform/samsung/fsd-csis/fsd-csis.c      | 1709 +++++++++++++++++
>  6 files changed, 1740 insertions(+)
>  create mode 100644 drivers/media/platform/samsung/fsd-csis/Kconfig
>  create mode 100644 drivers/media/platform/samsung/fsd-csis/Makefile
>  create mode 100644 drivers/media/platform/samsung/fsd-csis/fsd-csis.c
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index bd62ad58a47f..1e17fb0581d2 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -3334,6 +3334,14 @@ S:	Maintained
>  F:	Documentation/devicetree/bindings/media/samsung,s5p-mfc.yaml
>  F:	drivers/media/platform/samsung/s5p-mfc/
>  
> +ARM/SAMSUNG FSD BRIDGE DRIVER

TESLA FSD BRIDGE DRIVER
(because ARM/foo are only SoC maintainer entries)

> +M:	Inbaraj E <inbaraj.e@samsung.com>
> +L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)

Replace above list with samsung-soc list.

> +L:	linux-media@vger.kernel.org
> +S:	Maintained
> +F:	Documentation/devicetree/bindings/media/tesla,fsd-csis-media.yaml
> +F:	drivers/media/platform/samsung/fsd-csis/fsd-csis.c
> +
>  ARM/SOCFPGA ARCHITECTURE
>  M:	Dinh Nguyen <dinguyen@kernel.org>
>  S:	Maintained
> diff --git a/drivers/media/platform/samsung/Kconfig b/drivers/media/platform/samsung/Kconfig
> index 0e34c5fc1dfc..4cebe2ae24a3 100644
> --- a/drivers/media/platform/samsung/Kconfig
> +++ b/drivers/media/platform/samsung/Kconfig
> @@ -4,6 +4,7 @@ comment "Samsung media platform drivers"
>  
>  source "drivers/media/platform/samsung/exynos-gsc/Kconfig"
>  source "drivers/media/platform/samsung/exynos4-is/Kconfig"
> +source "drivers/media/platform/samsung/fsd-csis/Kconfig"
>  source "drivers/media/platform/samsung/s3c-camif/Kconfig"
>  source "drivers/media/platform/samsung/s5p-g2d/Kconfig"
>  source "drivers/media/platform/samsung/s5p-jpeg/Kconfig"
> diff --git a/drivers/media/platform/samsung/Makefile b/drivers/media/platform/samsung/Makefile
> index 21fea3330e4b..fde1b9626713 100644
> --- a/drivers/media/platform/samsung/Makefile
> +++ b/drivers/media/platform/samsung/Makefile
> @@ -1,6 +1,7 @@
>  # SPDX-License-Identifier: GPL-2.0-only
>  obj-y += exynos-gsc/
>  obj-y += exynos4-is/
> +obj-y += fsd-csis/
>  obj-y += s3c-camif/
>  obj-y += s5p-g2d/
>  obj-y += s5p-jpeg/
> diff --git a/drivers/media/platform/samsung/fsd-csis/Kconfig b/drivers/media/platform/samsung/fsd-csis/Kconfig
> new file mode 100644
> index 000000000000..99803e924682
> --- /dev/null
> +++ b/drivers/media/platform/samsung/fsd-csis/Kconfig
> @@ -0,0 +1,18 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +#
> +# FSD MIPI CSI-2 Rx controller configurations
> +
> +config VIDEO_FSD_CSIS

VIDEO_TSLA_FSD_CSIS

> +	tristate "FSD SoC MIPI-CSI2 media controller driver"
> +	depends on VIDEO_DEV && VIDEO_V4L2_SUBDEV_API
> +	depends on HAS_DMA
> +	depends on OF

OF seems unneeded dependency

But you miss ARCH_TESLA_FSD instead.


> +	select VIDEOBUF2_DMA_CONTIG
> +	select V4L2_FWNODE
> +	help
> +	  This is a video4linux2 driver for FSD SoC MIPI-CSI2 Rx.

Tesla FSD

> +	  The driver provides interface for capturing frames.
> +
> +	  To compile this driver as a module, choose M here. The module
> +	  will be called fsd-csis.
> +
> diff --git a/drivers/media/platform/samsung/fsd-csis/Makefile b/drivers/media/platform/samsung/fsd-csis/Makefile
> new file mode 100644
> index 000000000000..eba8c0c6a7cc
> --- /dev/null
> +++ b/drivers/media/platform/samsung/fsd-csis/Makefile
> @@ -0,0 +1,3 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +
> +obj-$(CONFIG_VIDEO_FSD_CSIS) += fsd-csis.o
> diff --git a/drivers/media/platform/samsung/fsd-csis/fsd-csis.c b/drivers/media/platform/samsung/fsd-csis/fsd-csis.c
> new file mode 100644
> index 000000000000..74f46038d506
> --- /dev/null
> +++ b/drivers/media/platform/samsung/fsd-csis/fsd-csis.c
> @@ -0,0 +1,1709 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2022-2025 Samsung Electronics Co., Ltd.
> + *             https://www.samsung.com
> + *
> + * FSD CSIS V4L2 Capture driver for FSD SoC.

"Tesla FSD" in both places

> + */
> +
> +#include <linux/clk.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/regmap.h>
> +#include <media/v4l2-device.h>
> +#include <media/v4l2-ioctl.h>
> +#include <media/videobuf2-dma-contig.h>
> +#include <media/v4l2-mc.h>

How can you depend on OF if there is no single OF header?

> +
> +#define FSD_CSIS_DMA_COHERENT_MASK_SIZE		32
> +#define FSD_CSIS_NB_MIN_CH			2
> +#define FSD_CSIS_NB_VC				4
> +#define FSD_CSIS_MEDIA_NUM_PADS			2
> +#define FSD_CSIS_NB_DMA_OUT_CH			8
> +#define FSD_CSIS_MAX_VC				4
> +#define FSD_CSIS_NB_CLOCK			2
> +#define FSD_CSIS_NB_OF_BUFS_ON_DMA_CHANNELS	2
> +#define FSD_CSIS_DMA_LINE_ALIGN_SIZE		128
> +#define FSD_CSIS_DMA_CH_OFFSET			0x100

...

> +
> +static int fsd_csis_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct fsd_csis *csis;
> +	int ret = 0;
> +	int irq;
> +
> +	csis = devm_kzalloc(dev, sizeof(*csis), GFP_KERNEL);
> +	if (!csis)
> +		return -ENOMEM;
> +
> +	csis->dev = dev;
> +	csis->info = of_device_get_match_data(dev);
> +
> +	csis->dma_base = devm_platform_ioremap_resource(pdev, 0);
> +	if (IS_ERR(csis->dma_base))
> +		return PTR_ERR(csis->dma_base);
> +
> +	irq = platform_get_irq(pdev, 0);
> +	if (irq < 0)
> +		return irq;
> +
> +	ret = devm_request_irq(dev, irq,
> +			csis_irq_handler, IRQF_SHARED, pdev->name, csis);

Please align these (checkpatch --strict)

> +
> +	ret = fsd_csis_clk_get(csis);
> +	if (ret < 0)
> +		return ret;
> +
> +	pm_runtime_enable(dev);
> +	if (!pm_runtime_enabled(dev)) {

That's odd code. Why?

> +		ret = fsd_csis_runtime_resume(dev);

Even more questions why?

> +		if (ret < 0)
> +			return ret;
> +	}
> +
> +	platform_set_drvdata(pdev, csis);
> +
> +	ret = fsd_csis_enable_pll(csis);
> +	if (ret)
> +		return ret;
> +
> +	ret = fsd_csis_media_init(csis);
> +	if (ret)
> +		return ret;

I think you miss clean up of csis->pll completely. Just use
devm_clk_get_enabled and convert everything here to devm.


> +
> +	ret = fsd_csis_async_register(csis);
> +	if (ret)
> +		goto err_media_cleanup;
> +
> +	return 0;
> +
> +err_media_cleanup:
> +	fsd_csis_media_cleanup(csis);

Also this...

> +
> +	return ret;
> +}
> +
> +static void fsd_csis_remove(struct platform_device *pdev)
> +{
> +	struct fsd_csis *csis = platform_get_drvdata(pdev);
> +
> +	fsd_csis_media_cleanup(csis);
> +
> +	v4l2_async_nf_unregister(&csis->notifier);
> +	v4l2_async_nf_cleanup(&csis->notifier);
> +	v4l2_async_unregister_subdev(&csis->subdev.sd);
> +
> +	if (!pm_runtime_enabled(csis->dev))
> +		fsd_csis_runtime_suspend(csis->dev);
> +
> +	pm_runtime_disable(csis->dev);
> +	pm_runtime_set_suspended(csis->dev);
> +}
> +
> +static const struct of_device_id fsd_csis_of_match[] = {
> +	{ .compatible = "tesla,fsd-csis-media", },
> +	{ },
> +};
> +
> +MODULE_DEVICE_TABLE(of, fsd_csis_of_match);
> +
> +static struct platform_driver fsd_csis_driver = {
> +	.probe		= fsd_csis_probe,
> +	.remove		= fsd_csis_remove,
> +	.driver		= {
> +		.name		= FSD_CSIS_MODULE_NAME,
> +		.of_match_table = of_match_ptr(fsd_csis_of_match),

Drop of_match_ptr, it is not really correct.

> +		.pm		= &fsd_csis_pm_ops,
> +	},
> +};
> +
> +module_platform_driver(fsd_csis_driver);
> +
> +MODULE_DESCRIPTION("FSD CSIS Driver");
> +MODULE_AUTHOR("Inbaraj E <inbaraj.e@samsung.com>");
> +MODULE_LICENSE("GPL");
> +


Best regards,
Krzysztof

RE: [PATCH v2 12/12] media: fsd-csis: Add support for FSD CSIS DMA

[Inbaraj E]

Hi Krzysztof,

Thanks for the review.

> 
> On 14/08/2025 16:09, Inbaraj E wrote:
> > FSD CSIS IP bundles DMA engine for receiving frames from MIPI-CSI2 bus.
> > Add support internal DMA controller to capture the frames.
> >
> > Signed-off-by: Inbaraj E <inbaraj.e@samsung.com>
> 
> I commented on order of patches and got more surprise - final driver patch
> after DTS defconfig. It's really wrong order.

I'll fix in next patchset.

> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -3334,6 +3334,14 @@ S:	Maintained
> >  F:	Documentation/devicetree/bindings/media/samsung,s5p-mfc.yaml
> >  F:	drivers/media/platform/samsung/s5p-mfc/
> >
> > +ARM/SAMSUNG FSD BRIDGE DRIVER
> 
> TESLA FSD BRIDGE DRIVER
> (because ARM/foo are only SoC maintainer entries)
> 

I'll change in next patchset.

> > +M:	Inbaraj E <inbaraj.e@samsung.com>
> > +L:	linux-arm-kernel@lists.infradead.org (moderated for non-
> subscribers)
> 
> Replace above list with samsung-soc list.
> 

I'll change in next patchset.
 
> > +L:	linux-media@vger.kernel.org
> > +S:	Maintained
> >  source "drivers/media/platform/samsung/exynos-gsc/Kconfig"
> >  source "drivers/media/platform/samsung/exynos4-is/Kconfig"
> > +
> > +config VIDEO_FSD_CSIS
> 
> VIDEO_TSLA_FSD_CSIS

I'll change in next patchset.

> 
> > +	tristate "FSD SoC MIPI-CSI2 media controller driver"
> > +	depends on VIDEO_DEV && VIDEO_V4L2_SUBDEV_API
> > +	depends on HAS_DMA
> > +	depends on OF
> 
> OF seems unneeded dependency
> 
> But you miss ARCH_TESLA_FSD instead.
> 
> 

I'll remove OF and add ARCH_TESLA_FSD in next patchset.

> > +	select VIDEOBUF2_DMA_CONTIG
> > +	select V4L2_FWNODE
> > +	help
> > +	  This is a video4linux2 driver for FSD SoC MIPI-CSI2 Rx.
> 
> Tesla FSD

I'll add in next patchset.

> > new file mode 100644
> > index 000000000000..74f46038d506
> > --- /dev/null
> > +++ b/drivers/media/platform/samsung/fsd-csis/fsd-csis.c
> > @@ -0,0 +1,1709 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Copyright (c) 2022-2025 Samsung Electronics Co., Ltd.
> > + *             https://www.samsung.com
> > + *
> > + * FSD CSIS V4L2 Capture driver for FSD SoC.
> 
> "Tesla FSD" in both places

I'll change in next patchset.

> 
> > + */
> > +
> > +#include <linux/clk.h>
> > +#include <linux/pm_runtime.h>
> > +#include <linux/regmap.h>
> > +#include <media/v4l2-device.h>
> > +#include <media/v4l2-ioctl.h>
> > +#include <media/videobuf2-dma-contig.h> #include <media/v4l2-mc.h>
> 
> How can you depend on OF if there is no single OF header?

> > +
> > +	ret = devm_request_irq(dev, irq,
> > +			csis_irq_handler, IRQF_SHARED, pdev->name, csis);
> 
> Please align these (checkpatch --strict)

I'll fix in next patchset

> 
> > +
> > +	ret = fsd_csis_clk_get(csis);
> > +	if (ret < 0)
> > +		return ret;
> > +
> > +	pm_runtime_enable(dev);
> > +	if (!pm_runtime_enabled(dev)) {
> 
> That's odd code. Why?
> 
> > +		ret = fsd_csis_runtime_resume(dev);
> 
> Even more questions why?

If CONFIG_PM is enabled, the clocks are enabled manually in the
driver through fsd_csis_runtime_resume API.

If CONFIG_PM is enabled, the clocks are managed through the PM
runtime framework.

Can you please help me understand what wrong here?

> 
> > +		if (ret < 0)
> > +			return ret;
> > +	}
> > +
> > +	platform_set_drvdata(pdev, csis);
> > +
> > +	ret = fsd_csis_enable_pll(csis);
> > +	if (ret)
> > +		return ret;
> > +
> > +	ret = fsd_csis_media_init(csis);
> > +	if (ret)
> > +		return ret;
> 
> I think you miss clean up of csis->pll completely. Just use
> devm_clk_get_enabled and convert everything here to devm.
> 
> 

I'll fix in next patchset.

> > +
> > +	ret = fsd_csis_async_register(csis);
> > +	if (ret)
> > +		goto err_media_cleanup;
> > +
> > +	return 0;
> > +
> > +err_media_cleanup:
> > +	fsd_csis_media_cleanup(csis);
> 
> Also this...
> 

if fsd_csis_media_init fails, the cleanup is handled internally.
Here, cleanup is used only for fsd_csis_async_register failure.

can you please help me understand what is wrong here?
 
> > +
> > +	return ret;
> > +}
> > +
> > +static void fsd_csis_remove(struct platform_device *pdev) {
> > +	struct fsd_csis *csis = platform_get_drvdata(pdev);
> > +
> > +static struct platform_driver fsd_csis_driver = {
> > +	.probe		= fsd_csis_probe,
> > +	.remove		= fsd_csis_remove,
> > +	.driver		= {
> > +		.name		= FSD_CSIS_MODULE_NAME,
> > +		.of_match_table = of_match_ptr(fsd_csis_of_match),
> 
> Drop of_match_ptr, it is not really correct.

Will drop in next patchset.

Regards,
Inbaraj E

Re: [PATCH v2 12/12] media: fsd-csis: Add support for FSD CSIS DMA

[Krzysztof Kozlowski]

On 23/08/2025 13:49, Inbaraj E wrote:
>>
>>> +
>>> +	ret = fsd_csis_clk_get(csis);
>>> +	if (ret < 0)
>>> +		return ret;
>>> +
>>> +	pm_runtime_enable(dev);
>>> +	if (!pm_runtime_enabled(dev)) {
>>
>> That's odd code. Why?
>>
>>> +		ret = fsd_csis_runtime_resume(dev);
>>
>> Even more questions why?
> 
> If CONFIG_PM is enabled, the clocks are enabled manually in the
> driver through fsd_csis_runtime_resume API.
> 
> If CONFIG_PM is enabled, the clocks are managed through the PM
> runtime framework.
> 
> Can you please help me understand what wrong here?

I think I see such code for the first time, so wrong is doing something
common in completely unusual way.

> 
>>
>>> +		if (ret < 0)
>>> +			return ret;
>>> +	}
>>> +
>>> +	platform_set_drvdata(pdev, csis);
>>> +
>>> +	ret = fsd_csis_enable_pll(csis);
>>> +	if (ret)
>>> +		return ret;
>>> +
>>> +	ret = fsd_csis_media_init(csis);
>>> +	if (ret)
>>> +		return ret;
>>
>> I think you miss clean up of csis->pll completely. Just use
>> devm_clk_get_enabled and convert everything here to devm.
>>
>>
> 
> I'll fix in next patchset.
> 
>>> +
>>> +	ret = fsd_csis_async_register(csis);
>>> +	if (ret)
>>> +		goto err_media_cleanup;
>>> +
>>> +	return 0;
>>> +
>>> +err_media_cleanup:
>>> +	fsd_csis_media_cleanup(csis);
>>
>> Also this...
>>
> 
> if fsd_csis_media_init fails, the cleanup is handled internally.

What does it mean internally?

> Here, cleanup is used only for fsd_csis_async_register failure.
> 
> can you please help me understand what is wrong here?

Yeah, you leak clock resources.



Best regards,
Krzysztof

RE: [PATCH v2 12/12] media: fsd-csis: Add support for FSD CSIS DMA

[Inbaraj E]

Hi Krzysztof,

> >> Even more questions why?
> >
> > If CONFIG_PM is enabled, the clocks are enabled manually in the driver
> > through fsd_csis_runtime_resume API.
> >
> > If CONFIG_PM is enabled, the clocks are managed through the PM runtime
> > framework.
> >
> > Can you please help me understand what wrong here?
> 
> I think I see such code for the first time, so wrong is doing something
> common in completely unusual way.
> 

Driver should ensure a device can be also used normally when runtime
PM is disabled. So enabling clocks manually in probe, if CONFIG_PM is
disabled.

A Couple of other drivers also doing it in same way
drivers/media/platform/nxp/imx-mipi-csis.c and 
drivers/media/platform/samsung/exynos4-is/fimc-core.c

> >
> > I'll fix in next patchset.
> >
> >>> +
> >>> +	ret = fsd_csis_async_register(csis);
> >>> +	if (ret)
> >>> +		goto err_media_cleanup;
> >>> +
> >>> +	return 0;
> >>> +
> >>> +err_media_cleanup:
> >>> +	fsd_csis_media_cleanup(csis);
> >>
> >> Also this...
> >>
> >
> > if fsd_csis_media_init fails, the cleanup is handled internally.
> 
> What does it mean internally?

I mean that in case fsd_csis_media_init fails, the cleanup of resources is handled
Within the same function itself.

> 
> > Here, cleanup is used only for fsd_csis_async_register failure.
> >
> > can you please help me understand what is wrong here?
> 
> Yeah, you leak clock resources.

I'll fix in next patchset

Regards,
Inbaraj E

RE: [PATCH v2 12/12] media: fsd-csis: Add support for FSD CSIS DMA

[Inbaraj E]

> -----Original Message-----
> From: Inbaraj E <inbaraj.e@samsung.com>
> Sent: 23 August 2025 17:20
> To: 'Krzysztof Kozlowski' <krzk@kernel.org>; 'mturquette@baylibre.com'
> <mturquette@baylibre.com>; 'sboyd@kernel.org' <sboyd@kernel.org>;
> 'robh@kernel.org' <robh@kernel.org>; 'krzk+dt@kernel.org'
> <krzk+dt@kernel.org>; 'conor+dt@kernel.org' <conor+dt@kernel.org>;
> 's.nawrocki@samsung.com' <s.nawrocki@samsung.com>;
> 's.hauer@pengutronix.de' <s.hauer@pengutronix.de>;
> 'shawnguo@kernel.org' <shawnguo@kernel.org>;
> 'cw00.choi@samsung.com' <cw00.choi@samsung.com>; 'rmfrfs@gmail.com'
> <rmfrfs@gmail.com>; 'laurent.pinchart@ideasonboard.com'
> <laurent.pinchart@ideasonboard.com>; 'martink@posteo.de'
> <martink@posteo.de>; 'mchehab@kernel.org' <mchehab@kernel.org>;
> 'linux-fsd@tesla.com' <linux-fsd@tesla.com>; 'will@kernel.org'
> <will@kernel.org>; 'catalin.marinas@arm.com' <catalin.marinas@arm.com>;
> 'pankaj.dubey@samsung.com' <pankaj.dubey@samsung.com>;
> 'shradha.t@samsung.com' <shradha.t@samsung.com>;
> 'ravi.patel@samsung.com' <ravi.patel@samsung.com>
> Cc: 'linux-clk@vger.kernel.org' <linux-clk@vger.kernel.org>;
> 'devicetree@vger.kernel.org' <devicetree@vger.kernel.org>; 'linux-
> kernel@vger.kernel.org' <linux-kernel@vger.kernel.org>;
> 'alim.akhtar@samsung.com' <alim.akhtar@samsung.com>; 'linux-samsung-
> soc@vger.kernel.org' <linux-samsung-soc@vger.kernel.org>;
> 'kernel@puri.sm' <kernel@puri.sm>; 'kernel@pengutronix.de'
> <kernel@pengutronix.de>; 'festevam@gmail.com' <festevam@gmail.com>;
> 'linux-media@vger.kernel.org' <linux-media@vger.kernel.org>;
> 'imx@lists.linux.dev' <imx@lists.linux.dev>; 'linux-arm-
> kernel@lists.infradead.org' <linux-arm-kernel@lists.infradead.org>
> Subject: RE: [PATCH v2 12/12] media: fsd-csis: Add support for FSD CSIS DMA
> 
> Hi Krzysztof,
> 
> Thanks for the review.
> 
> >
> > On 14/08/2025 16:09, Inbaraj E wrote:
> > > FSD CSIS IP bundles DMA engine for receiving frames from MIPI-CSI2 bus.
> > > Add support internal DMA controller to capture the frames.
> > >
> > > Signed-off-by: Inbaraj E <inbaraj.e@samsung.com>
> >
> > I commented on order of patches and got more surprise - final driver
> > patch after DTS defconfig. It's really wrong order.
> 
> I'll fix in next patchset.
> 
> > > --- a/MAINTAINERS
> > > +++ b/MAINTAINERS
> > > @@ -3334,6 +3334,14 @@ S:	Maintained
> > >  F:	Documentation/devicetree/bindings/media/samsung,s5p-mfc.yaml
> > >  F:	drivers/media/platform/samsung/s5p-mfc/
> > >
> > > +ARM/SAMSUNG FSD BRIDGE DRIVER
> >
> > TESLA FSD BRIDGE DRIVER
> > (because ARM/foo are only SoC maintainer entries)
> >
> 
> I'll change in next patchset.
> 
> > > +M:	Inbaraj E <inbaraj.e@samsung.com>
> > > +L:	linux-arm-kernel@lists.infradead.org (moderated for non-
> > subscribers)
> >
> > Replace above list with samsung-soc list.
> >
> 
> I'll change in next patchset.
> 
> > > +L:	linux-media@vger.kernel.org
> > > +S:	Maintained
> > >  source "drivers/media/platform/samsung/exynos-gsc/Kconfig"
> > >  source "drivers/media/platform/samsung/exynos4-is/Kconfig"
> > > +
> > > +config VIDEO_FSD_CSIS
> >
> > VIDEO_TSLA_FSD_CSIS
> 
> I'll change in next patchset.
> 
> >
> > > +	tristate "FSD SoC MIPI-CSI2 media controller driver"
> > > +	depends on VIDEO_DEV && VIDEO_V4L2_SUBDEV_API
> > > +	depends on HAS_DMA
> > > +	depends on OF
> >
> > OF seems unneeded dependency
> >
> > But you miss ARCH_TESLA_FSD instead.
> >
> >
> 
> I'll remove OF and add ARCH_TESLA_FSD in next patchset.
> 
> > > +	select VIDEOBUF2_DMA_CONTIG
> > > +	select V4L2_FWNODE
> > > +	help
> > > +	  This is a video4linux2 driver for FSD SoC MIPI-CSI2 Rx.
> >
> > Tesla FSD
> 
> I'll add in next patchset.
> 
> > > new file mode 100644
> > > index 000000000000..74f46038d506
> > > --- /dev/null
> > > +++ b/drivers/media/platform/samsung/fsd-csis/fsd-csis.c
> > > @@ -0,0 +1,1709 @@
> > > +// SPDX-License-Identifier: GPL-2.0-only
> > > +/*
> > > + * Copyright (c) 2022-2025 Samsung Electronics Co., Ltd.
> > > + *             https://www.samsung.com
> > > + *
> > > + * FSD CSIS V4L2 Capture driver for FSD SoC.
> >
> > "Tesla FSD" in both places
> 
> I'll change in next patchset.
> 
> >
> > > + */
> > > +
> > > +#include <linux/clk.h>
> > > +#include <linux/pm_runtime.h>
> > > +#include <linux/regmap.h>
> > > +#include <media/v4l2-device.h>
> > > +#include <media/v4l2-ioctl.h>
> > > +#include <media/videobuf2-dma-contig.h> #include <media/v4l2-mc.h>
> >
> > How can you depend on OF if there is no single OF header?
> 
> > > +
> > > +	ret = devm_request_irq(dev, irq,
> > > +			csis_irq_handler, IRQF_SHARED, pdev->name, csis);
> >
> > Please align these (checkpatch --strict)
> 
> I'll fix in next patchset
> 
> >
> > > +
> > > +	ret = fsd_csis_clk_get(csis);
> > > +	if (ret < 0)
> > > +		return ret;
> > > +
> > > +	pm_runtime_enable(dev);
> > > +	if (!pm_runtime_enabled(dev)) {
> >
> > That's odd code. Why?
> >
> > > +		ret = fsd_csis_runtime_resume(dev);
> >
> > Even more questions why?
> 

Sorry I made typo here

 If CONFIG_PM is disabled, the clocks are enabled manually in the driver
 through fsd_csis_runtime_resume API.
 
 If CONFIG_PM is enabled, the clocks are managed through the PM runtime
 framework.
 
> Can you please help me understand what wrong here?
> 
> >
> > > +		if (ret < 0)
> > > +			return ret;
> > > +	}
> > > +
> > > +	platform_set_drvdata(pdev, csis);
> > > +
> > > +	ret = fsd_csis_enable_pll(csis);
> > > +	if (ret)
> > > +		return ret;
> > > +
> > > +	ret = fsd_csis_media_init(csis);
> > > +	if (ret)
> > > +		return ret;
> >
> > I think you miss clean up of csis->pll completely. Just use
> > devm_clk_get_enabled and convert everything here to devm.
> >
> >
> 
> I'll fix in next patchset.
> 
> > > +
> > > +	ret = fsd_csis_async_register(csis);
> > > +	if (ret)
> > > +		goto err_media_cleanup;
> > > +
> > > +	return 0;
> > > +
> > > +err_media_cleanup:
> > > +	fsd_csis_media_cleanup(csis);
> >
> > Also this...
> >
> 
> if fsd_csis_media_init fails, the cleanup is handled internally.
> Here, cleanup is used only for fsd_csis_async_register failure.
> 
> can you please help me understand what is wrong here?
> 
> > > +
> > > +	return ret;
> > > +}
> > > +
> > > +static void fsd_csis_remove(struct platform_device *pdev) {
> > > +	struct fsd_csis *csis = platform_get_drvdata(pdev);
> > > +
> > > +static struct platform_driver fsd_csis_driver = {
> > > +	.probe		= fsd_csis_probe,
> > > +	.remove		= fsd_csis_remove,
> > > +	.driver		= {
> > > +		.name		= FSD_CSIS_MODULE_NAME,
> > > +		.of_match_table = of_match_ptr(fsd_csis_of_match),
> >
> > Drop of_match_ptr, it is not really correct.
> 
> Will drop in next patchset.
> 
> Regards,
> Inbaraj E

Re: [PATCH v2 00/12] Add FSD CSI support

[Krzysztof Kozlowski]

On 14/08/2025 16:09, Inbaraj E wrote:
> FSD CSI(Camera Serial Interface) IP bundles Link controller and DMA
> controller for receiving frames. FSD SoC has 12 instances of CSI IP and
> 3 D-PHY. 4 instances of CSI IP use 1 D-PHY.
> 
> This patch series does the following:
> 1) Refactor the imx-mipi-csis driver to support platform specific
> clock names and interrupt handlers through device specific data
> (struct mipi_csis_info).
> 2) Add FSD CSI link controller support in imx-mipi-csis driver.
> 3) Introduce a new media driver for FSD CSI DMA providing support for
> video capture and streaming.
>  
> These patches were tested on the FSD platform using the
> capture_raw_frames application.
> 
> Changes since v1:
> 1. Addressed review comments from Laurent Pinchart to integrate the
> with imx-mipi-csis.c to handle the CSIS and expose it as a subdev.
> 
> Here is the link to v1 patch for reference:
> https://patchwork.kernel.org/project/linux-media/patch/7e7832c16925386b771ddb7e00e08661115aa0ea.1668963790.git.sathya@samsung.com/

Use lore links. b4 gives them for free..

> 
> Inbaraj E (12):
>   dt-bindings: clock: Add CAM_CSI clock macro for FSD
>   clk: samsung: fsd: Add clk id for PCLK and PLL in CAM_CSI block
>   dt-bindings: media: nxp: Add support for FSD SoC
>   arm64: dts: fsd: Add CSI nodes

Please split patches targeting different subsystems, since they are
completely independent. There is little benefit in combining independent
work into one huge patchset.
Best regards,
Krzysztof

RE: [PATCH v2 00/12] Add FSD CSI support

[Inbaraj E]

Hi Krzysztof

> >
> > Changes since v1:
> > 1. Addressed review comments from Laurent Pinchart to integrate the
> > with imx-mipi-csis.c to handle the CSIS and expose it as a subdev.
> >
> > Here is the link to v1 patch for reference:
> > https://patchwork.kernel.org/project/linux-media/patch/7e7832c16925386
> > b771ddb7e00e08661115aa0ea.1668963790.git.sathya@samsung.com/
> 
> Use lore links. b4 gives them for free..

I'll use lore links from next patchset.

> 
> >
> > Inbaraj E (12):
> >   dt-bindings: clock: Add CAM_CSI clock macro for FSD
> >   clk: samsung: fsd: Add clk id for PCLK and PLL in CAM_CSI block
> >   dt-bindings: media: nxp: Add support for FSD SoC
> >   arm64: dts: fsd: Add CSI nodes
> 
> Please split patches targeting different subsystems, since they are
> completely independent. There is little benefit in combining independent
> work into one huge patchset.

I'll spilt into different patchset according to the subsystem

> Best regards,
> Krzysztof

Regards,
Inbaraj E