* [PATCH v2 1/5] riscv: import read/write_relaxed functions
2023-10-31 23:55 ` [PATCH v2 0/5] Add support for StarFive JH7110 TRNG driver Chanho Park
@ 2023-10-31 23:55 ` Chanho Park
2023-10-31 23:55 ` [PATCH v2 2/5] clk: starfive: jh7110: Add security clocks Chanho Park
` (3 subsequent siblings)
4 siblings, 0 replies; 8+ messages in thread
From: Chanho Park @ 2023-10-31 23:55 UTC (permalink / raw)
To: Sughosh Ganu, Heinrich Schuchardt, Rick Chen, Leo, u-boot; +Cc: Chanho Park
This imports mmio functions from Linux's arch/riscv/include/asm/mmio.h
to use read/write[b|w|l|q]_relaxed functions.
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
---
arch/riscv/include/asm/io.h | 45 +++++++++++++++++++++++++++++++++++++
1 file changed, 45 insertions(+)
diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h
index b16e6dfa3760..4170877a1ae0 100644
--- a/arch/riscv/include/asm/io.h
+++ b/arch/riscv/include/asm/io.h
@@ -323,6 +323,51 @@ static inline void writesl(unsigned int *addr, const void *data, int longlen)
#define insw_p(port, to, len) insw(port, to, len)
#define insl_p(port, to, len) insl(port, to, len)
+/*
+ * Unordered I/O memory access primitives. These are even more relaxed than
+ * the relaxed versions, as they don't even order accesses between successive
+ * operations to the I/O regions.
+ */
+#define readb_cpu(c) ({ u8 __r = __raw_readb(c); __r; })
+#define readw_cpu(c) ({ u16 __r = le16_to_cpu((__force __le16)__raw_readw(c)); __r; })
+#define readl_cpu(c) ({ u32 __r = le32_to_cpu((__force __le32)__raw_readl(c)); __r; })
+
+#define writeb_cpu(v, c) ((void)__raw_writeb((v), (c)))
+#define writew_cpu(v, c) ((void)__raw_writew((__force u16)cpu_to_le16(v), (c)))
+#define writel_cpu(v, c) ((void)__raw_writel((__force u32)cpu_to_le32(v), (c)))
+
+#ifdef CONFIG_64BIT
+#define readq_cpu(c) ({ u64 __r = le64_to_cpu((__force __le64)__raw_readq(c)); __r; })
+#define writeq_cpu(v, c) ((void)__raw_writeq((__force u64)cpu_to_le64(v), (c)))
+#endif
+
+/*
+ * Relaxed I/O memory access primitives. These follow the Device memory
+ * ordering rules but do not guarantee any ordering relative to Normal memory
+ * accesses. These are defined to order the indicated access (either a read or
+ * write) with all other I/O memory accesses to the same peripheral. Since the
+ * platform specification defines that all I/O regions are strongly ordered on
+ * channel 0, no explicit fences are required to enforce this ordering.
+ */
+/* FIXME: These are now the same as asm-generic */
+#define __io_rbr() do {} while (0)
+#define __io_rar() do {} while (0)
+#define __io_rbw() do {} while (0)
+#define __io_raw() do {} while (0)
+
+#define readb_relaxed(c) ({ u8 __v; __io_rbr(); __v = readb_cpu(c); __io_rar(); __v; })
+#define readw_relaxed(c) ({ u16 __v; __io_rbr(); __v = readw_cpu(c); __io_rar(); __v; })
+#define readl_relaxed(c) ({ u32 __v; __io_rbr(); __v = readl_cpu(c); __io_rar(); __v; })
+
+#define writeb_relaxed(v, c) ({ __io_rbw(); writeb_cpu((v), (c)); __io_raw(); })
+#define writew_relaxed(v, c) ({ __io_rbw(); writew_cpu((v), (c)); __io_raw(); })
+#define writel_relaxed(v, c) ({ __io_rbw(); writel_cpu((v), (c)); __io_raw(); })
+
+#ifdef CONFIG_64BIT
+#define readq_relaxed(c) ({ u64 __v; __io_rbr(); __v = readq_cpu(c); __io_rar(); __v; })
+#define writeq_relaxed(v, c) ({ __io_rbw(); writeq_cpu((v), (c)); __io_raw(); })
+#endif
+
#include <asm-generic/io.h>
#endif /* __ASM_RISCV_IO_H */
--
2.39.2
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v2 2/5] clk: starfive: jh7110: Add security clocks
2023-10-31 23:55 ` [PATCH v2 0/5] Add support for StarFive JH7110 TRNG driver Chanho Park
2023-10-31 23:55 ` [PATCH v2 1/5] riscv: import read/write_relaxed functions Chanho Park
@ 2023-10-31 23:55 ` Chanho Park
2023-10-31 23:55 ` [PATCH v2 3/5] rng: Add StarFive JH7110 RNG driver Chanho Park
` (2 subsequent siblings)
4 siblings, 0 replies; 8+ messages in thread
From: Chanho Park @ 2023-10-31 23:55 UTC (permalink / raw)
To: Sughosh Ganu, Heinrich Schuchardt, Rick Chen, Leo, u-boot; +Cc: Chanho Park
Add STGCLK_SEC_HCLK and STGCLK_SEC_MISCAHB clocks for JH7110 TRNG
device.
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
---
drivers/clk/starfive/clk-jh7110.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/clk/starfive/clk-jh7110.c b/drivers/clk/starfive/clk-jh7110.c
index 31aaf3340f94..a835541e48e9 100644
--- a/drivers/clk/starfive/clk-jh7110.c
+++ b/drivers/clk/starfive/clk-jh7110.c
@@ -539,6 +539,16 @@ static int jh7110_stgcrg_init(struct udevice *dev)
"pcie1_tl", "stg_axiahb",
OFFSET(JH7110_STGCLK_PCIE1_TL)));
+ /* Security clocks */
+ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_SEC_HCLK),
+ starfive_clk_gate(priv->reg,
+ "sec_ahb", "stg_axiahb",
+ OFFSET(JH7110_STGCLK_SEC_HCLK)));
+ clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_SEC_MISCAHB),
+ starfive_clk_gate(priv->reg,
+ "sec_misc_ahb", "stg_axiahb",
+ OFFSET(JH7110_STGCLK_SEC_MISCAHB)));
+
return 0;
}
--
2.39.2
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v2 3/5] rng: Add StarFive JH7110 RNG driver
2023-10-31 23:55 ` [PATCH v2 0/5] Add support for StarFive JH7110 TRNG driver Chanho Park
2023-10-31 23:55 ` [PATCH v2 1/5] riscv: import read/write_relaxed functions Chanho Park
2023-10-31 23:55 ` [PATCH v2 2/5] clk: starfive: jh7110: Add security clocks Chanho Park
@ 2023-10-31 23:55 ` Chanho Park
2023-11-01 0:52 ` Jaehoon Chung
2023-10-31 23:55 ` [PATCH v2 4/5] riscv: dts: jh7110: Add rng device tree node Chanho Park
2023-10-31 23:55 ` [PATCH v2 5/5] configs: visionfive2: Enable JH7110 RNG driver Chanho Park
4 siblings, 1 reply; 8+ messages in thread
From: Chanho Park @ 2023-10-31 23:55 UTC (permalink / raw)
To: Sughosh Ganu, Heinrich Schuchardt, Rick Chen, Leo, u-boot; +Cc: Chanho Park
Adds to support JH7110 TRNG driver which is based on linux kernel's
jh7110-trng.c. This can support to generate 256-bit random numbers and
128-bit but this makes 256-bit default for convenience.
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
---
drivers/rng/Kconfig | 6 +
drivers/rng/Makefile | 1 +
drivers/rng/jh7110_rng.c | 258 +++++++++++++++++++++++++++++++++++++++
3 files changed, 265 insertions(+)
create mode 100644 drivers/rng/jh7110_rng.c
diff --git a/drivers/rng/Kconfig b/drivers/rng/Kconfig
index 994cc35b2744..0dba1e06b429 100644
--- a/drivers/rng/Kconfig
+++ b/drivers/rng/Kconfig
@@ -91,4 +91,10 @@ config TPM_RNG
functionality. Enable random number generator on TPM
devices.
+config RNG_JH7110
+ bool "StarFive JH7110 Random Number Generator support"
+ depends on DM_RNG && STARFIVE_JH7110
+ help
+ Enable True Random Number Generator in StarFive JH7110 SoCs.
+
endif
diff --git a/drivers/rng/Makefile b/drivers/rng/Makefile
index 47b323e61ee3..9de762c8a1c3 100644
--- a/drivers/rng/Makefile
+++ b/drivers/rng/Makefile
@@ -15,3 +15,4 @@ obj-$(CONFIG_RNG_IPROC200) += iproc_rng200.o
obj-$(CONFIG_RNG_SMCCC_TRNG) += smccc_trng.o
obj-$(CONFIG_RNG_ARM_RNDR) += arm_rndr.o
obj-$(CONFIG_TPM_RNG) += tpm_rng.o
+obj-$(CONFIG_RNG_JH7110) += jh7110_rng.o
diff --git a/drivers/rng/jh7110_rng.c b/drivers/rng/jh7110_rng.c
new file mode 100644
index 000000000000..37ea8cc39945
--- /dev/null
+++ b/drivers/rng/jh7110_rng.c
@@ -0,0 +1,258 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * TRNG driver for the StarFive JH7110 SoC
+ *
+ */
+
+#include <clk.h>
+#include <dm.h>
+#include <reset.h>
+#include <rng.h>
+#include <asm/io.h>
+#include <linux/iopoll.h>
+
+/* trng register offset */
+#define STARFIVE_CTRL 0x00
+#define STARFIVE_STAT 0x04
+#define STARFIVE_MODE 0x08
+#define STARFIVE_SMODE 0x0C
+#define STARFIVE_IE 0x10
+#define STARFIVE_ISTAT 0x14
+#define STARFIVE_RAND0 0x20
+#define STARFIVE_RAND1 0x24
+#define STARFIVE_RAND2 0x28
+#define STARFIVE_RAND3 0x2C
+#define STARFIVE_RAND4 0x30
+#define STARFIVE_RAND5 0x34
+#define STARFIVE_RAND6 0x38
+#define STARFIVE_RAND7 0x3C
+#define STARFIVE_AUTO_RQSTS 0x60
+#define STARFIVE_AUTO_AGE 0x64
+
+/* CTRL CMD */
+#define STARFIVE_CTRL_EXEC_NOP 0x0
+#define STARFIVE_CTRL_GENE_RANDNUM 0x1
+#define STARFIVE_CTRL_EXEC_RANDRESEED 0x2
+
+/* STAT */
+#define STARFIVE_STAT_NONCE_MODE BIT(2)
+#define STARFIVE_STAT_R256 BIT(3)
+#define STARFIVE_STAT_MISSION_MODE BIT(8)
+#define STARFIVE_STAT_SEEDED BIT(9)
+#define STARFIVE_STAT_LAST_RESEED(x) ((x) << 16)
+#define STARFIVE_STAT_SRVC_RQST BIT(27)
+#define STARFIVE_STAT_RAND_GENERATING BIT(30)
+#define STARFIVE_STAT_RAND_SEEDING BIT(31)
+#define STARFIVE_STAT_RUNNING (STARFIVE_STAT_RAND_GENERATING | \
+ STARFIVE_STAT_RAND_SEEDING)
+
+/* MODE */
+#define STARFIVE_MODE_R256 BIT(3)
+
+/* SMODE */
+#define STARFIVE_SMODE_NONCE_MODE BIT(2)
+#define STARFIVE_SMODE_MISSION_MODE BIT(8)
+#define STARFIVE_SMODE_MAX_REJECTS(x) ((x) << 16)
+
+/* IE */
+#define STARFIVE_IE_RAND_RDY_EN BIT(0)
+#define STARFIVE_IE_SEED_DONE_EN BIT(1)
+#define STARFIVE_IE_LFSR_LOCKUP_EN BIT(4)
+#define STARFIVE_IE_GLBL_EN BIT(31)
+
+#define STARFIVE_IE_ALL (STARFIVE_IE_GLBL_EN | \
+ STARFIVE_IE_RAND_RDY_EN | \
+ STARFIVE_IE_SEED_DONE_EN | \
+ STARFIVE_IE_LFSR_LOCKUP_EN)
+
+/* ISTAT */
+#define STARFIVE_ISTAT_RAND_RDY BIT(0)
+#define STARFIVE_ISTAT_SEED_DONE BIT(1)
+#define STARFIVE_ISTAT_LFSR_LOCKUP BIT(4)
+
+#define STARFIVE_RAND_LEN sizeof(u32)
+
+enum mode {
+ PRNG_128BIT,
+ PRNG_256BIT,
+};
+
+struct starfive_trng_plat {
+ void *base;
+ struct clk *hclk;
+ struct clk *ahb;
+ struct reset_ctl *rst;
+ u32 mode;
+};
+
+static inline int starfive_trng_wait_idle(struct starfive_trng_plat *trng)
+{
+ u32 stat;
+
+ return readl_relaxed_poll_timeout(trng->base + STARFIVE_STAT, stat,
+ !(stat & STARFIVE_STAT_RUNNING),
+ 100000);
+}
+
+static inline void starfive_trng_irq_mask_clear(struct starfive_trng_plat *trng)
+{
+ /* clear register: ISTAT */
+ u32 data = readl(trng->base + STARFIVE_ISTAT);
+
+ writel(data, trng->base + STARFIVE_ISTAT);
+}
+
+static int starfive_trng_cmd(struct starfive_trng_plat *trng, u32 cmd)
+{
+ u32 stat, flg;
+ int ret;
+
+ switch (cmd) {
+ case STARFIVE_CTRL_GENE_RANDNUM:
+ writel(cmd, trng->base + STARFIVE_CTRL);
+ flg = STARFIVE_ISTAT_RAND_RDY;
+ break;
+ case STARFIVE_CTRL_EXEC_RANDRESEED:
+ writel(cmd, trng->base + STARFIVE_CTRL);
+ flg = STARFIVE_ISTAT_SEED_DONE;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ ret = readl_relaxed_poll_timeout(trng->base + STARFIVE_ISTAT, stat,
+ (stat & flg), 1000);
+ writel(flg, trng->base + STARFIVE_ISTAT);
+
+ return ret;
+}
+
+static int starfive_trng_read(struct udevice *dev, void *data, size_t len)
+{
+ struct starfive_trng_plat *trng = dev_get_plat(dev);
+ u8 *buffer = data;
+ int iter_mask;
+
+ if (trng->mode == PRNG_256BIT)
+ iter_mask = 7;
+ else
+ iter_mask = 3;
+
+ for (int i = 0; len; ++i, i &= iter_mask) {
+ u32 val;
+ size_t step;
+ int ret;
+
+ ret = starfive_trng_cmd(trng, STARFIVE_CTRL_GENE_RANDNUM);
+ if (ret)
+ return ret;
+
+ val = readl(trng->base + STARFIVE_RAND0 +
+ (i * STARFIVE_RAND_LEN));
+ step = min_t(size_t, len, STARFIVE_RAND_LEN);
+ memcpy(buffer, &val, step);
+ buffer += step;
+ len -= step;
+ }
+
+ return 0;
+}
+
+static int starfive_trng_init(struct starfive_trng_plat *trng)
+{
+ u32 mode, intr = 0;
+
+ /* setup Auto Request/Age register */
+ writel(0, trng->base + STARFIVE_AUTO_AGE);
+ writel(0, trng->base + STARFIVE_AUTO_RQSTS);
+
+ /* clear register: ISTAT */
+ starfive_trng_irq_mask_clear(trng);
+
+ intr |= STARFIVE_IE_ALL;
+ writel(intr, trng->base + STARFIVE_IE);
+
+ mode = readl(trng->base + STARFIVE_MODE);
+
+ switch (trng->mode) {
+ case PRNG_128BIT:
+ mode &= ~STARFIVE_MODE_R256;
+ break;
+ case PRNG_256BIT:
+ mode |= STARFIVE_MODE_R256;
+ break;
+ default:
+ mode |= STARFIVE_MODE_R256;
+ break;
+ }
+
+ writel(mode, trng->base + STARFIVE_MODE);
+
+ return starfive_trng_cmd(trng, STARFIVE_CTRL_EXEC_RANDRESEED);
+}
+
+static int starfive_trng_probe(struct udevice *dev)
+{
+ struct starfive_trng_plat *pdata = dev_get_plat(dev);
+ int err;
+
+ err = clk_enable(pdata->hclk);
+ if (err)
+ return err;
+
+ err = clk_enable(pdata->ahb);
+ if (err)
+ return err;
+
+ err = reset_deassert(pdata->rst);
+ if (err)
+ return err;
+
+ pdata->mode = PRNG_256BIT;
+
+ return starfive_trng_init(pdata);
+}
+
+static int starfive_trng_of_to_plat(struct udevice *dev)
+{
+ struct starfive_trng_plat *pdata = dev_get_plat(dev);
+
+ pdata->base = (void *)dev_read_addr(dev);
+ if (!pdata->base)
+ return -ENODEV;
+
+ pdata->hclk = devm_clk_get(dev, "hclk");
+ if (IS_ERR(pdata->hclk))
+ return -ENODEV;
+
+ pdata->ahb = devm_clk_get(dev, "ahb");
+ if (IS_ERR(pdata->ahb))
+ return -ENODEV;
+
+ pdata->rst = devm_reset_control_get(dev, NULL);
+ if (IS_ERR(pdata->rst))
+ return -ENODEV;
+
+ return 0;
+}
+
+static const struct dm_rng_ops starfive_trng_ops = {
+ .read = starfive_trng_read,
+};
+
+static const struct udevice_id starfive_trng_match[] = {
+ {
+ .compatible = "starfive,jh7110-trng",
+ },
+ {},
+};
+
+U_BOOT_DRIVER(starfive_trng) = {
+ .name = "jh7110-trng",
+ .id = UCLASS_RNG,
+ .of_match = starfive_trng_match,
+ .probe = starfive_trng_probe,
+ .ops = &starfive_trng_ops,
+ .plat_auto = sizeof(struct starfive_trng_plat),
+ .of_to_plat = starfive_trng_of_to_plat,
+};
--
2.39.2
^ permalink raw reply related [flat|nested] 8+ messages in thread* RE: [PATCH v2 3/5] rng: Add StarFive JH7110 RNG driver
2023-10-31 23:55 ` [PATCH v2 3/5] rng: Add StarFive JH7110 RNG driver Chanho Park
@ 2023-11-01 0:52 ` Jaehoon Chung
2023-11-01 1:18 ` Chanho Park
0 siblings, 1 reply; 8+ messages in thread
From: Jaehoon Chung @ 2023-11-01 0:52 UTC (permalink / raw)
To: 'Chanho Park', 'Sughosh Ganu',
'Heinrich Schuchardt', 'Rick Chen', 'Leo',
u-boot
> -----Original Message-----
> From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Chanho Park
> Sent: Wednesday, November 1, 2023 8:55 AM
> To: Sughosh Ganu <sughosh.ganu@linaro.org>; Heinrich Schuchardt <xypron.glpk@gmx.de>; Rick Chen
> <rick@andestech.com>; Leo <ycliang@andestech.com>; u-boot@lists.denx.de
> Cc: Chanho Park <chanho61.park@samsung.com>
> Subject: [PATCH v2 3/5] rng: Add StarFive JH7110 RNG driver
>
> Adds to support JH7110 TRNG driver which is based on linux kernel's
> jh7110-trng.c. This can support to generate 256-bit random numbers and
> 128-bit but this makes 256-bit default for convenience.
>
> Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> ---
> drivers/rng/Kconfig | 6 +
> drivers/rng/Makefile | 1 +
> drivers/rng/jh7110_rng.c | 258 +++++++++++++++++++++++++++++++++++++++
> 3 files changed, 265 insertions(+)
> create mode 100644 drivers/rng/jh7110_rng.c
>
> diff --git a/drivers/rng/Kconfig b/drivers/rng/Kconfig
> index 994cc35b2744..0dba1e06b429 100644
> --- a/drivers/rng/Kconfig
> +++ b/drivers/rng/Kconfig
> @@ -91,4 +91,10 @@ config TPM_RNG
> functionality. Enable random number generator on TPM
> devices.
>
> +config RNG_JH7110
> + bool "StarFive JH7110 Random Number Generator support"
> + depends on DM_RNG && STARFIVE_JH7110
> + help
> + Enable True Random Number Generator in StarFive JH7110 SoCs.
> +
> endif
> diff --git a/drivers/rng/Makefile b/drivers/rng/Makefile
> index 47b323e61ee3..9de762c8a1c3 100644
> --- a/drivers/rng/Makefile
> +++ b/drivers/rng/Makefile
> @@ -15,3 +15,4 @@ obj-$(CONFIG_RNG_IPROC200) += iproc_rng200.o
> obj-$(CONFIG_RNG_SMCCC_TRNG) += smccc_trng.o
> obj-$(CONFIG_RNG_ARM_RNDR) += arm_rndr.o
> obj-$(CONFIG_TPM_RNG) += tpm_rng.o
> +obj-$(CONFIG_RNG_JH7110) += jh7110_rng.o
> diff --git a/drivers/rng/jh7110_rng.c b/drivers/rng/jh7110_rng.c
> new file mode 100644
> index 000000000000..37ea8cc39945
> --- /dev/null
> +++ b/drivers/rng/jh7110_rng.c
> @@ -0,0 +1,258 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +/*
> + * TRNG driver for the StarFive JH7110 SoC
> + *
> + */
> +
> +#include <clk.h>
> +#include <dm.h>
> +#include <reset.h>
> +#include <rng.h>
> +#include <asm/io.h>
> +#include <linux/iopoll.h>
> +
> +/* trng register offset */
> +#define STARFIVE_CTRL 0x00
> +#define STARFIVE_STAT 0x04
> +#define STARFIVE_MODE 0x08
> +#define STARFIVE_SMODE 0x0C
> +#define STARFIVE_IE 0x10
> +#define STARFIVE_ISTAT 0x14
> +#define STARFIVE_RAND0 0x20
> +#define STARFIVE_RAND1 0x24
> +#define STARFIVE_RAND2 0x28
> +#define STARFIVE_RAND3 0x2C
> +#define STARFIVE_RAND4 0x30
> +#define STARFIVE_RAND5 0x34
> +#define STARFIVE_RAND6 0x38
> +#define STARFIVE_RAND7 0x3C
> +#define STARFIVE_AUTO_RQSTS 0x60
> +#define STARFIVE_AUTO_AGE 0x64
> +
> +/* CTRL CMD */
> +#define STARFIVE_CTRL_EXEC_NOP 0x0
> +#define STARFIVE_CTRL_GENE_RANDNUM 0x1
> +#define STARFIVE_CTRL_EXEC_RANDRESEED 0x2
> +
> +/* STAT */
> +#define STARFIVE_STAT_NONCE_MODE BIT(2)
> +#define STARFIVE_STAT_R256 BIT(3)
> +#define STARFIVE_STAT_MISSION_MODE BIT(8)
> +#define STARFIVE_STAT_SEEDED BIT(9)
> +#define STARFIVE_STAT_LAST_RESEED(x) ((x) << 16)
> +#define STARFIVE_STAT_SRVC_RQST BIT(27)
> +#define STARFIVE_STAT_RAND_GENERATING BIT(30)
> +#define STARFIVE_STAT_RAND_SEEDING BIT(31)
> +#define STARFIVE_STAT_RUNNING (STARFIVE_STAT_RAND_GENERATING | \
> + STARFIVE_STAT_RAND_SEEDING)
> +
> +/* MODE */
> +#define STARFIVE_MODE_R256 BIT(3)
> +
> +/* SMODE */
> +#define STARFIVE_SMODE_NONCE_MODE BIT(2)
> +#define STARFIVE_SMODE_MISSION_MODE BIT(8)
> +#define STARFIVE_SMODE_MAX_REJECTS(x) ((x) << 16)
> +
> +/* IE */
> +#define STARFIVE_IE_RAND_RDY_EN BIT(0)
> +#define STARFIVE_IE_SEED_DONE_EN BIT(1)
> +#define STARFIVE_IE_LFSR_LOCKUP_EN BIT(4)
> +#define STARFIVE_IE_GLBL_EN BIT(31)
> +
> +#define STARFIVE_IE_ALL (STARFIVE_IE_GLBL_EN | \
> + STARFIVE_IE_RAND_RDY_EN | \
> + STARFIVE_IE_SEED_DONE_EN | \
> + STARFIVE_IE_LFSR_LOCKUP_EN)
> +
> +/* ISTAT */
> +#define STARFIVE_ISTAT_RAND_RDY BIT(0)
> +#define STARFIVE_ISTAT_SEED_DONE BIT(1)
> +#define STARFIVE_ISTAT_LFSR_LOCKUP BIT(4)
> +
> +#define STARFIVE_RAND_LEN sizeof(u32)
> +
> +enum mode {
> + PRNG_128BIT,
> + PRNG_256BIT,
> +};
> +
> +struct starfive_trng_plat {
> + void *base;
> + struct clk *hclk;
> + struct clk *ahb;
> + struct reset_ctl *rst;
> + u32 mode;
> +};
> +
> +static inline int starfive_trng_wait_idle(struct starfive_trng_plat *trng)
> +{
> + u32 stat;
> +
> + return readl_relaxed_poll_timeout(trng->base + STARFIVE_STAT, stat,
> + !(stat & STARFIVE_STAT_RUNNING),
> + 100000);
> +}
> +
> +static inline void starfive_trng_irq_mask_clear(struct starfive_trng_plat *trng)
> +{
> + /* clear register: ISTAT */
> + u32 data = readl(trng->base + STARFIVE_ISTAT);
> +
> + writel(data, trng->base + STARFIVE_ISTAT);
> +}
> +
> +static int starfive_trng_cmd(struct starfive_trng_plat *trng, u32 cmd)
> +{
> + u32 stat, flg;
> + int ret;
> +
> + switch (cmd) {
> + case STARFIVE_CTRL_GENE_RANDNUM:
> + writel(cmd, trng->base + STARFIVE_CTRL);
> + flg = STARFIVE_ISTAT_RAND_RDY;
> + break;
> + case STARFIVE_CTRL_EXEC_RANDRESEED:
> + writel(cmd, trng->base + STARFIVE_CTRL);
> + flg = STARFIVE_ISTAT_SEED_DONE;
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + ret = readl_relaxed_poll_timeout(trng->base + STARFIVE_ISTAT, stat,
> + (stat & flg), 1000);
> + writel(flg, trng->base + STARFIVE_ISTAT);
> +
> + return ret;
> +}
> +
> +static int starfive_trng_read(struct udevice *dev, void *data, size_t len)
> +{
> + struct starfive_trng_plat *trng = dev_get_plat(dev);
> + u8 *buffer = data;
> + int iter_mask;
> +
> + if (trng->mode == PRNG_256BIT)
> + iter_mask = 7;
> + else
> + iter_mask = 3;
> +
> + for (int i = 0; len; ++i, i &= iter_mask) {
> + u32 val;
> + size_t step;
> + int ret;
> +
> + ret = starfive_trng_cmd(trng, STARFIVE_CTRL_GENE_RANDNUM);
> + if (ret)
> + return ret;
> +
> + val = readl(trng->base + STARFIVE_RAND0 +
> + (i * STARFIVE_RAND_LEN));
> + step = min_t(size_t, len, STARFIVE_RAND_LEN);
> + memcpy(buffer, &val, step);
> + buffer += step;
> + len -= step;
> + }
> +
> + return 0;
> +}
> +
> +static int starfive_trng_init(struct starfive_trng_plat *trng)
> +{
> + u32 mode, intr = 0;
> +
> + /* setup Auto Request/Age register */
> + writel(0, trng->base + STARFIVE_AUTO_AGE);
> + writel(0, trng->base + STARFIVE_AUTO_RQSTS);
> +
> + /* clear register: ISTAT */
> + starfive_trng_irq_mask_clear(trng);
> +
> + intr |= STARFIVE_IE_ALL;
> + writel(intr, trng->base + STARFIVE_IE);
> +
> + mode = readl(trng->base + STARFIVE_MODE);
> +
> + switch (trng->mode) {
> + case PRNG_128BIT:
> + mode &= ~STARFIVE_MODE_R256;
> + break;
> + case PRNG_256BIT:
> + mode |= STARFIVE_MODE_R256;
> + break;
> + default:
> + mode |= STARFIVE_MODE_R256;
> + break;
> + }
> +
> + writel(mode, trng->base + STARFIVE_MODE);
> +
> + return starfive_trng_cmd(trng, STARFIVE_CTRL_EXEC_RANDRESEED);
> +}
> +
> +static int starfive_trng_probe(struct udevice *dev)
> +{
> + struct starfive_trng_plat *pdata = dev_get_plat(dev);
> + int err;
> +
> + err = clk_enable(pdata->hclk);
> + if (err)
> + return err;
> +
> + err = clk_enable(pdata->ahb);
> + if (err)
Doesn't need to disable the previous clk about pdata->hclk?
> + return err;
> +
> + err = reset_deassert(pdata->rst);
> + if (err)
Ditto about clocks of hclk and ahb?
How about handle error?
err = clk_enable(pdata->hclk);
if (err)
...
err = clk_enable(pdata->ahb);
if (err)
goto err_ahb;
...
Return starfive_tring_init(pdata);
goto_err_reset:
clk_disable(pdata->ahb);
goto err_ahb:
clk_disable(pdata->hclk);
return err;
> + return err;
> +
> + pdata->mode = PRNG_256BIT;
> +
> + return starfive_trng_init(pdata);
> +}
> +
> +static int starfive_trng_of_to_plat(struct udevice *dev)
> +{
> + struct starfive_trng_plat *pdata = dev_get_plat(dev);
> +
> + pdata->base = (void *)dev_read_addr(dev);
> + if (!pdata->base)
> + return -ENODEV;
> +
> + pdata->hclk = devm_clk_get(dev, "hclk");
> + if (IS_ERR(pdata->hclk))
> + return -ENODEV;
> +
> + pdata->ahb = devm_clk_get(dev, "ahb");
> + if (IS_ERR(pdata->ahb))
> + return -ENODEV;
> +
> + pdata->rst = devm_reset_control_get(dev, NULL);
> + if (IS_ERR(pdata->rst))
> + return -ENODEV;
> +
> + return 0;
> +}
> +
> +static const struct dm_rng_ops starfive_trng_ops = {
> + .read = starfive_trng_read,
> +};
> +
> +static const struct udevice_id starfive_trng_match[] = {
> + {
> + .compatible = "starfive,jh7110-trng",
> + },
> + {},
> +};
> +
> +U_BOOT_DRIVER(starfive_trng) = {
> + .name = "jh7110-trng",
> + .id = UCLASS_RNG,
> + .of_match = starfive_trng_match,
> + .probe = starfive_trng_probe,
> + .ops = &starfive_trng_ops,
> + .plat_auto = sizeof(struct starfive_trng_plat),
> + .of_to_plat = starfive_trng_of_to_plat,
> +};
> --
> 2.39.2
^ permalink raw reply [flat|nested] 8+ messages in thread* RE: [PATCH v2 3/5] rng: Add StarFive JH7110 RNG driver
2023-11-01 0:52 ` Jaehoon Chung
@ 2023-11-01 1:18 ` Chanho Park
0 siblings, 0 replies; 8+ messages in thread
From: Chanho Park @ 2023-11-01 1:18 UTC (permalink / raw)
To: 'Jaehoon Chung', 'Sughosh Ganu',
'Heinrich Schuchardt', 'Rick Chen', 'Leo',
u-boot
> -----Original Message-----
> From: Jaehoon Chung <jh80.chung@samsung.com>
> Sent: Wednesday, November 1, 2023 9:52 AM
> To: 'Chanho Park' <chanho61.park@samsung.com>; 'Sughosh Ganu'
> <sughosh.ganu@linaro.org>; 'Heinrich Schuchardt' <xypron.glpk@gmx.de>;
> 'Rick Chen' <rick@andestech.com>; 'Leo' <ycliang@andestech.com>; u-
> boot@lists.denx.de
> Subject: RE: [PATCH v2 3/5] rng: Add StarFive JH7110 RNG driver
>
>
>
> > -----Original Message-----
> > From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Chanho Park
> > Sent: Wednesday, November 1, 2023 8:55 AM
> > To: Sughosh Ganu <sughosh.ganu@linaro.org>; Heinrich Schuchardt
> <xypron.glpk@gmx.de>; Rick Chen
> > <rick@andestech.com>; Leo <ycliang@andestech.com>; u-boot@lists.denx.de
> > Cc: Chanho Park <chanho61.park@samsung.com>
> > Subject: [PATCH v2 3/5] rng: Add StarFive JH7110 RNG driver
> >
> > Adds to support JH7110 TRNG driver which is based on linux kernel's
> > jh7110-trng.c. This can support to generate 256-bit random numbers and
> > 128-bit but this makes 256-bit default for convenience.
> >
> > Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> > ---
> > drivers/rng/Kconfig | 6 +
> > drivers/rng/Makefile | 1 +
> > drivers/rng/jh7110_rng.c | 258 +++++++++++++++++++++++++++++++++++++++
> > 3 files changed, 265 insertions(+)
> > create mode 100644 drivers/rng/jh7110_rng.c
> >
> > diff --git a/drivers/rng/Kconfig b/drivers/rng/Kconfig
> > index 994cc35b2744..0dba1e06b429 100644
> > --- a/drivers/rng/Kconfig
> > +++ b/drivers/rng/Kconfig
> > @@ -91,4 +91,10 @@ config TPM_RNG
> > functionality. Enable random number generator on TPM
> > devices.
> >
> > +config RNG_JH7110
> > + bool "StarFive JH7110 Random Number Generator support"
> > + depends on DM_RNG && STARFIVE_JH7110
> > + help
> > + Enable True Random Number Generator in StarFive JH7110 SoCs.
> > +
> > endif
> > diff --git a/drivers/rng/Makefile b/drivers/rng/Makefile
> > index 47b323e61ee3..9de762c8a1c3 100644
> > --- a/drivers/rng/Makefile
> > +++ b/drivers/rng/Makefile
> > @@ -15,3 +15,4 @@ obj-$(CONFIG_RNG_IPROC200) += iproc_rng200.o
> > obj-$(CONFIG_RNG_SMCCC_TRNG) += smccc_trng.o
> > obj-$(CONFIG_RNG_ARM_RNDR) += arm_rndr.o
> > obj-$(CONFIG_TPM_RNG) += tpm_rng.o
> > +obj-$(CONFIG_RNG_JH7110) += jh7110_rng.o
> > diff --git a/drivers/rng/jh7110_rng.c b/drivers/rng/jh7110_rng.c
> > new file mode 100644
> > index 000000000000..37ea8cc39945
> > --- /dev/null
> > +++ b/drivers/rng/jh7110_rng.c
> > @@ -0,0 +1,258 @@
> > +// SPDX-License-Identifier: GPL-2.0-or-later
> > +/*
> > + * TRNG driver for the StarFive JH7110 SoC
> > + *
> > + */
> > +
> > +#include <clk.h>
> > +#include <dm.h>
> > +#include <reset.h>
> > +#include <rng.h>
> > +#include <asm/io.h>
> > +#include <linux/iopoll.h>
> > +
> > +/* trng register offset */
> > +#define STARFIVE_CTRL 0x00
> > +#define STARFIVE_STAT 0x04
> > +#define STARFIVE_MODE 0x08
> > +#define STARFIVE_SMODE 0x0C
> > +#define STARFIVE_IE 0x10
> > +#define STARFIVE_ISTAT 0x14
> > +#define STARFIVE_RAND0 0x20
> > +#define STARFIVE_RAND1 0x24
> > +#define STARFIVE_RAND2 0x28
> > +#define STARFIVE_RAND3 0x2C
> > +#define STARFIVE_RAND4 0x30
> > +#define STARFIVE_RAND5 0x34
> > +#define STARFIVE_RAND6 0x38
> > +#define STARFIVE_RAND7 0x3C
> > +#define STARFIVE_AUTO_RQSTS 0x60
> > +#define STARFIVE_AUTO_AGE 0x64
> > +
> > +/* CTRL CMD */
> > +#define STARFIVE_CTRL_EXEC_NOP 0x0
> > +#define STARFIVE_CTRL_GENE_RANDNUM 0x1
> > +#define STARFIVE_CTRL_EXEC_RANDRESEED 0x2
> > +
> > +/* STAT */
> > +#define STARFIVE_STAT_NONCE_MODE BIT(2)
> > +#define STARFIVE_STAT_R256 BIT(3)
> > +#define STARFIVE_STAT_MISSION_MODE BIT(8)
> > +#define STARFIVE_STAT_SEEDED BIT(9)
> > +#define STARFIVE_STAT_LAST_RESEED(x) ((x) << 16)
> > +#define STARFIVE_STAT_SRVC_RQST BIT(27)
> > +#define STARFIVE_STAT_RAND_GENERATING BIT(30)
> > +#define STARFIVE_STAT_RAND_SEEDING BIT(31)
> > +#define STARFIVE_STAT_RUNNING (STARFIVE_STAT_RAND_GENERATING | \
> > + STARFIVE_STAT_RAND_SEEDING)
> > +
> > +/* MODE */
> > +#define STARFIVE_MODE_R256 BIT(3)
> > +
> > +/* SMODE */
> > +#define STARFIVE_SMODE_NONCE_MODE BIT(2)
> > +#define STARFIVE_SMODE_MISSION_MODE BIT(8)
> > +#define STARFIVE_SMODE_MAX_REJECTS(x) ((x) << 16)
> > +
> > +/* IE */
> > +#define STARFIVE_IE_RAND_RDY_EN BIT(0)
> > +#define STARFIVE_IE_SEED_DONE_EN BIT(1)
> > +#define STARFIVE_IE_LFSR_LOCKUP_EN BIT(4)
> > +#define STARFIVE_IE_GLBL_EN BIT(31)
> > +
> > +#define STARFIVE_IE_ALL (STARFIVE_IE_GLBL_EN | \
> > + STARFIVE_IE_RAND_RDY_EN | \
> > + STARFIVE_IE_SEED_DONE_EN | \
> > + STARFIVE_IE_LFSR_LOCKUP_EN)
> > +
> > +/* ISTAT */
> > +#define STARFIVE_ISTAT_RAND_RDY BIT(0)
> > +#define STARFIVE_ISTAT_SEED_DONE BIT(1)
> > +#define STARFIVE_ISTAT_LFSR_LOCKUP BIT(4)
> > +
> > +#define STARFIVE_RAND_LEN sizeof(u32)
> > +
> > +enum mode {
> > + PRNG_128BIT,
> > + PRNG_256BIT,
> > +};
> > +
> > +struct starfive_trng_plat {
> > + void *base;
> > + struct clk *hclk;
> > + struct clk *ahb;
> > + struct reset_ctl *rst;
> > + u32 mode;
> > +};
> > +
> > +static inline int starfive_trng_wait_idle(struct starfive_trng_plat
> *trng)
> > +{
> > + u32 stat;
> > +
> > + return readl_relaxed_poll_timeout(trng->base + STARFIVE_STAT, stat,
> > + !(stat & STARFIVE_STAT_RUNNING),
> > + 100000);
> > +}
> > +
> > +static inline void starfive_trng_irq_mask_clear(struct
> starfive_trng_plat *trng)
> > +{
> > + /* clear register: ISTAT */
> > + u32 data = readl(trng->base + STARFIVE_ISTAT);
> > +
> > + writel(data, trng->base + STARFIVE_ISTAT);
> > +}
> > +
> > +static int starfive_trng_cmd(struct starfive_trng_plat *trng, u32 cmd)
> > +{
> > + u32 stat, flg;
> > + int ret;
> > +
> > + switch (cmd) {
> > + case STARFIVE_CTRL_GENE_RANDNUM:
> > + writel(cmd, trng->base + STARFIVE_CTRL);
> > + flg = STARFIVE_ISTAT_RAND_RDY;
> > + break;
> > + case STARFIVE_CTRL_EXEC_RANDRESEED:
> > + writel(cmd, trng->base + STARFIVE_CTRL);
> > + flg = STARFIVE_ISTAT_SEED_DONE;
> > + break;
> > + default:
> > + return -EINVAL;
> > + }
> > +
> > + ret = readl_relaxed_poll_timeout(trng->base + STARFIVE_ISTAT, stat,
> > + (stat & flg), 1000);
> > + writel(flg, trng->base + STARFIVE_ISTAT);
> > +
> > + return ret;
> > +}
> > +
> > +static int starfive_trng_read(struct udevice *dev, void *data, size_t
> len)
> > +{
> > + struct starfive_trng_plat *trng = dev_get_plat(dev);
> > + u8 *buffer = data;
> > + int iter_mask;
> > +
> > + if (trng->mode == PRNG_256BIT)
> > + iter_mask = 7;
> > + else
> > + iter_mask = 3;
> > +
> > + for (int i = 0; len; ++i, i &= iter_mask) {
> > + u32 val;
> > + size_t step;
> > + int ret;
> > +
> > + ret = starfive_trng_cmd(trng, STARFIVE_CTRL_GENE_RANDNUM);
> > + if (ret)
> > + return ret;
> > +
> > + val = readl(trng->base + STARFIVE_RAND0 +
> > + (i * STARFIVE_RAND_LEN));
> > + step = min_t(size_t, len, STARFIVE_RAND_LEN);
> > + memcpy(buffer, &val, step);
> > + buffer += step;
> > + len -= step;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static int starfive_trng_init(struct starfive_trng_plat *trng)
> > +{
> > + u32 mode, intr = 0;
> > +
> > + /* setup Auto Request/Age register */
> > + writel(0, trng->base + STARFIVE_AUTO_AGE);
> > + writel(0, trng->base + STARFIVE_AUTO_RQSTS);
> > +
> > + /* clear register: ISTAT */
> > + starfive_trng_irq_mask_clear(trng);
> > +
> > + intr |= STARFIVE_IE_ALL;
> > + writel(intr, trng->base + STARFIVE_IE);
> > +
> > + mode = readl(trng->base + STARFIVE_MODE);
> > +
> > + switch (trng->mode) {
> > + case PRNG_128BIT:
> > + mode &= ~STARFIVE_MODE_R256;
> > + break;
> > + case PRNG_256BIT:
> > + mode |= STARFIVE_MODE_R256;
> > + break;
> > + default:
> > + mode |= STARFIVE_MODE_R256;
> > + break;
> > + }
> > +
> > + writel(mode, trng->base + STARFIVE_MODE);
> > +
> > + return starfive_trng_cmd(trng, STARFIVE_CTRL_EXEC_RANDRESEED);
> > +}
> > +
> > +static int starfive_trng_probe(struct udevice *dev)
> > +{
> > + struct starfive_trng_plat *pdata = dev_get_plat(dev);
> > + int err;
> > +
> > + err = clk_enable(pdata->hclk);
> > + if (err)
> > + return err;
> > +
> > + err = clk_enable(pdata->ahb);
> > + if (err)
>
> Doesn't need to disable the previous clk about pdata->hclk?
>
>
> > + return err;
> > +
> > + err = reset_deassert(pdata->rst);
> > + if (err)
>
> Ditto about clocks of hclk and ahb?
>
> How about handle error?
>
> err = clk_enable(pdata->hclk);
> if (err)
> ...
>
> err = clk_enable(pdata->ahb);
> if (err)
> goto err_ahb;
>
> ...
>
> Return starfive_tring_init(pdata);
>
> goto_err_reset:
> clk_disable(pdata->ahb);
> goto err_ahb:
> clk_disable(pdata->hclk);
>
> return err;
Thank you for your suggestion.
I'll update the codes in the next patchset.
Best Regards,
Chanho Park
>
> > + return err;
> > +
> > + pdata->mode = PRNG_256BIT;
> > +
> > + return starfive_trng_init(pdata);
> > +}
> > +
> > +static int starfive_trng_of_to_plat(struct udevice *dev)
> > +{
> > + struct starfive_trng_plat *pdata = dev_get_plat(dev);
> > +
> > + pdata->base = (void *)dev_read_addr(dev);
> > + if (!pdata->base)
> > + return -ENODEV;
> > +
> > + pdata->hclk = devm_clk_get(dev, "hclk");
> > + if (IS_ERR(pdata->hclk))
> > + return -ENODEV;
> > +
> > + pdata->ahb = devm_clk_get(dev, "ahb");
> > + if (IS_ERR(pdata->ahb))
> > + return -ENODEV;
> > +
> > + pdata->rst = devm_reset_control_get(dev, NULL);
> > + if (IS_ERR(pdata->rst))
> > + return -ENODEV;
> > +
> > + return 0;
> > +}
> > +
> > +static const struct dm_rng_ops starfive_trng_ops = {
> > + .read = starfive_trng_read,
> > +};
> > +
> > +static const struct udevice_id starfive_trng_match[] = {
> > + {
> > + .compatible = "starfive,jh7110-trng",
> > + },
> > + {},
> > +};
> > +
> > +U_BOOT_DRIVER(starfive_trng) = {
> > + .name = "jh7110-trng",
> > + .id = UCLASS_RNG,
> > + .of_match = starfive_trng_match,
> > + .probe = starfive_trng_probe,
> > + .ops = &starfive_trng_ops,
> > + .plat_auto = sizeof(struct starfive_trng_plat),
> > + .of_to_plat = starfive_trng_of_to_plat,
> > +};
> > --
> > 2.39.2
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 4/5] riscv: dts: jh7110: Add rng device tree node
2023-10-31 23:55 ` [PATCH v2 0/5] Add support for StarFive JH7110 TRNG driver Chanho Park
` (2 preceding siblings ...)
2023-10-31 23:55 ` [PATCH v2 3/5] rng: Add StarFive JH7110 RNG driver Chanho Park
@ 2023-10-31 23:55 ` Chanho Park
2023-10-31 23:55 ` [PATCH v2 5/5] configs: visionfive2: Enable JH7110 RNG driver Chanho Park
4 siblings, 0 replies; 8+ messages in thread
From: Chanho Park @ 2023-10-31 23:55 UTC (permalink / raw)
To: Sughosh Ganu, Heinrich Schuchardt, Rick Chen, Leo, u-boot; +Cc: Chanho Park
Adds jh7110 trng device tree node.
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
---
arch/riscv/dts/jh7110.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
index ec237a46ffba..13c47f7caa36 100644
--- a/arch/riscv/dts/jh7110.dtsi
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -627,6 +627,16 @@
status = "disabled";
};
+ rng: rng@1600c000 {
+ compatible = "starfive,jh7110-trng";
+ reg = <0x0 0x1600C000 0x0 0x4000>;
+ clocks = <&stgcrg JH7110_STGCLK_SEC_HCLK>,
+ <&stgcrg JH7110_STGCLK_SEC_MISCAHB>;
+ clock-names = "hclk", "ahb";
+ resets = <&stgcrg JH7110_STGRST_SEC_TOP_HRESETN>;
+ interrupts = <30>;
+ };
+
aoncrg: clock-controller@17000000 {
compatible = "starfive,jh7110-aoncrg";
reg = <0x0 0x17000000 0x0 0x10000>;
--
2.39.2
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v2 5/5] configs: visionfive2: Enable JH7110 RNG driver
2023-10-31 23:55 ` [PATCH v2 0/5] Add support for StarFive JH7110 TRNG driver Chanho Park
` (3 preceding siblings ...)
2023-10-31 23:55 ` [PATCH v2 4/5] riscv: dts: jh7110: Add rng device tree node Chanho Park
@ 2023-10-31 23:55 ` Chanho Park
4 siblings, 0 replies; 8+ messages in thread
From: Chanho Park @ 2023-10-31 23:55 UTC (permalink / raw)
To: Sughosh Ganu, Heinrich Schuchardt, Rick Chen, Leo, u-boot; +Cc: Chanho Park
Enables JH7110 RNG driver to visionfive2 board.
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
---
configs/starfive_visionfive2_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig
index b21754feafce..b15e7d24db19 100644
--- a/configs/starfive_visionfive2_defconfig
+++ b/configs/starfive_visionfive2_defconfig
@@ -120,6 +120,8 @@ CONFIG_SPL_PINCTRL_STARFIVE=y
CONFIG_SPL_PINCTRL_STARFIVE_JH7110=y
CONFIG_PINCTRL_STARFIVE=y
# CONFIG_RAM_SIFIVE is not set
+CONFIG_DM_RNG=y
+CONFIG_RNG_JH7110=y
CONFIG_SYS_NS16550=y
CONFIG_CADENCE_QSPI=y
CONFIG_TIMER_EARLY=y
--
2.39.2
^ permalink raw reply related [flat|nested] 8+ messages in thread