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From: Nicola Vetrini <nicola.vetrini@bugseng.com>
To: Julien Grall <julien@xen.org>
Cc: xen-devel@lists.xenproject.org, sstabellini@kernel.org,
	michal.orzel@amd.com, xenia.ragiadakou@amd.com,
	ayan.kumar.halder@amd.com, consulting@bugseng.com,
	jbeulich@suse.com, andrew.cooper3@citrix.com,
	roger.pau@citrix.com,
	Simone Ballarin <simone.ballarin@bugseng.com>,
	Doug Goldstein <cardoe@cardoe.com>,
	George Dunlap <george.dunlap@citrix.com>, Wei Liu <wl@xen.org>
Subject: Re: [XEN PATCH][for-4.19 1/9] xen/include: add macro LOWEST_POW2
Date: Fri, 06 Oct 2023 12:02:31 +0200	[thread overview]
Message-ID: <0197ecdcc5869dddecc98907f67ba0f1@bugseng.com> (raw)
In-Reply-To: <6102db25-2fd6-49fa-be66-ec2b627b019b@xen.org>

On 06/10/2023 11:29, Julien Grall wrote:
> Hi,
> 
> On 06/10/2023 09:26, Nicola Vetrini wrote:
>> The purpose of this macro is to encapsulate the well-known expression
>> 'x & -x', that in 2's complement architectures on unsigned integers 
>> will
>> give 2^ffs(x), where ffs(x) is the position of the lowest set bit in 
>> x.
>> 
>> A deviation for ECLAIR is also introduced.
> 
> Can you explain why this is a deviation in ECLAIR rather than one with
> /* SAF-* */ (or whichever name we decide to rename to)? Is this
> because the code is correct from MISRA perspective but the tool is
> confused?
> 

The code does violate Rule 10.1 (a unary minus applied to an unsigned 
value is
deemed inappropriate by MISRA), but rather than changing a whole lot of 
places where this
construct is used (mainly in x86 code), the reasoning is that it makes 
more sense to isolate
it and justify its presence by the fact that on 2's complement 
architectures the result is
indeed correct.

>> 
>> Signed-off-by: Nicola Vetrini <nicola.vetrini@bugseng.com>
>> ---
>>   automation/eclair_analysis/ECLAIR/deviations.ecl | 6 ++++++
>>   xen/include/xen/macros.h                         | 6 ++++--
>>   2 files changed, 10 insertions(+), 2 deletions(-)
>> 
>> diff --git a/automation/eclair_analysis/ECLAIR/deviations.ecl 
>> b/automation/eclair_analysis/ECLAIR/deviations.ecl
>> index d8170106b449..016164643105 100644
>> --- a/automation/eclair_analysis/ECLAIR/deviations.ecl
>> +++ b/automation/eclair_analysis/ECLAIR/deviations.ecl
>> @@ -274,6 +274,12 @@ still non-negative."
>>   -config=MC3R1.R10.1,etypes+={safe, 
>> "stmt(operator(logical)||node(conditional_operator||binary_conditional_operator))", 
>> "dst_type(ebool||boolean)"}
>>   -doc_end
>>   +-doc_begin="The macro LOWEST_POW2 encapsulates a well-known pattern 
>> to obtain the value
>> +2^ffs(x) for unsigned integers on two's complement architectures
>> +(all the architectures supported by Xen satisfy this requirement)."
>> +-config=MC3R1.R10.1,reports+={safe, 
>> "any_area(any_loc(any_exp(macro(^LOWEST_POW2$))))"}
>> +-doc_end
>> +
>>   ### Set 3 ###
>>     #
>> diff --git a/xen/include/xen/macros.h b/xen/include/xen/macros.h
>> index d0caae7db298..bb9a1c9a53d0 100644
>> --- a/xen/include/xen/macros.h
>> +++ b/xen/include/xen/macros.h
>> @@ -8,8 +8,10 @@
>>   #define DIV_ROUND(n, d) (((n) + (d) / 2) / (d))
>>   #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
>>   -#define MASK_EXTR(v, m) (((v) & (m)) / ((m) & -(m)))
>> -#define MASK_INSR(v, m) (((v) * ((m) & -(m))) & (m))
>> +#define LOWEST_POW2(x) ((x) & -(x))
>> +
>> +#define MASK_EXTR(v, m) (((v) & (m)) / LOWEST_POW2(m))
>> +#define MASK_INSR(v, m) (((v) * LOWEST_POW2(m)) & (m))
>>     #define count_args_(dot, a1, a2, a3, a4, a5, a6, a7, a8, x, ...) x
>>   #define count_args(args...) \

-- 
Nicola Vetrini, BSc
Software Engineer, BUGSENG srl (https://bugseng.com)


  reply	other threads:[~2023-10-06 10:02 UTC|newest]

Thread overview: 45+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-06  8:26 [XEN PATCH 0/9] address violations of MISRA C:2012 Rule 10.1 Nicola Vetrini
2023-10-06  8:26 ` [XEN PATCH][for-4.19 1/9] xen/include: add macro LOWEST_POW2 Nicola Vetrini
2023-10-06  9:29   ` Julien Grall
2023-10-06 10:02     ` Nicola Vetrini [this message]
2023-10-06 10:22       ` Julien Grall
2023-10-06 10:34         ` Nicola Vetrini
2023-10-06 14:35           ` Julien Grall
2023-10-06 15:36             ` Nicola Vetrini
2023-10-07  0:05             ` Stefano Stabellini
2023-10-07  0:29               ` Stefano Stabellini
2023-10-09  8:23                 ` Nicola Vetrini
2023-10-06 16:35   ` andrew.cooper3
2023-10-09  7:08     ` Nicola Vetrini
2023-10-06  8:26 ` [XEN PATCH][for-4.19 2/9] arm/bitops: encapsulate violation of MISRA C:2012 Rule 10.1 Nicola Vetrini
2023-10-10  0:45   ` Stefano Stabellini
2023-10-06  8:26 ` [XEN PATCH][for-4.19 3/9] xen/pdx: amend definition of PDX_GROUP_COUNT Nicola Vetrini
2023-10-06  8:26 ` [XEN PATCH 4/9] x86_64/mm: express macro CNT using LOWEST_POW2 Nicola Vetrini
2023-10-06  8:26 ` [XEN PATCH 5/9] x86/cpu-policy: address violations of MISRA C Rule 10.1 Nicola Vetrini
2023-10-06 17:57   ` Andrew Cooper
2023-10-09  7:13     ` Nicola Vetrini
2023-10-06  8:26 ` [XEN PATCH 6/9] x86/io_apic: address violation of MISRA C:2012 " Nicola Vetrini
2023-10-10  0:48   ` Stefano Stabellini
2023-10-06  8:26 ` [XEN PATCH 7/9] x86/mce: Move MC_NCLASSES into the enum mctelem_class Nicola Vetrini
2023-10-06 19:11   ` andrew.cooper3
2023-10-09  7:15     ` Nicola Vetrini
2023-10-06  8:26 ` [XEN PATCH][for-4.19 8/9] xen/types: address Rule 10.1 for DECLARE_BITMAP use Nicola Vetrini
2023-10-06  9:34   ` Julien Grall
2023-10-06 10:10     ` Nicola Vetrini
2023-10-06 14:47       ` Julien Grall
2023-10-07  1:04         ` Stefano Stabellini
2023-10-09  7:48           ` Nicola Vetrini
2023-10-09  9:09           ` Julien Grall
2023-10-10  1:09             ` Stefano Stabellini
2023-10-10 10:53               ` Julien Grall
2023-10-10 12:07                 ` Nicola Vetrini
2023-10-10 12:13                   ` Julien Grall
2023-10-10 12:15                     ` Julien Grall
2023-10-10 12:55                       ` Nicola Vetrini
2023-10-10 14:20                 ` Nicola Vetrini
2023-10-09  7:44         ` Nicola Vetrini
2023-10-06  8:26 ` [XEN PATCH 9/9] xen/compat: address Rule 10.1 for macros CHECK_SIZE Nicola Vetrini
2023-10-10  1:02   ` Stefano Stabellini
2023-10-10 16:00     ` Andrew Cooper
2023-10-10 16:06       ` Nicola Vetrini
2023-10-10 16:19         ` Andrew Cooper

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