From: "Kevin D. Kissell" <kevink@mips.com>
To: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>, "Jun Sun" <jsun@mvista.com>
Cc: <linux-mips@oss.sgi.com>
Subject: Re: config option vs. run-time detection (the debate continues ...)
Date: Fri, 9 Feb 2001 23:12:00 +0100 [thread overview]
Message-ID: <01b001c092e5$58f6a8a0$0deca8c0@Ulysses> (raw)
In-Reply-To: Pine.GSO.3.96.1010209212607.13007B-100000@delta.ds2.pg.gda.pl
> > Another question. I know with mips32 and mips64 we can do run-time
detection
> > reliably. What about other existing processors?
>
> I've sent a quote from an IDT manual recently. It recommended to use the
> FPU implementation ID to check if an FP hw is present. I believe it
> should work for any sane implementation of a MIPS CPU. See the mail for
> details.
The best method I know for post-R3000 CPUs is to
write and read back the CU1 bit of the Status register.
CPUs without an integrated FPU will not have a flip-flop
for the bit, and will read back a 0 even after writing a 1.
There was never any architectural requirement that
this be so, however, and this cannot be absolutely
guaranteed to work. If anyone has a counter-example,
however, I'd be interested in hearing about it.
Kevin K.
WARNING: multiple messages have this Message-ID (diff)
From: "Kevin D. Kissell" <kevink@mips.com>
To: "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>, Jun Sun <jsun@mvista.com>
Cc: linux-mips@oss.sgi.com
Subject: Re: config option vs. run-time detection (the debate continues ...)
Date: Fri, 9 Feb 2001 23:12:00 +0100 [thread overview]
Message-ID: <01b001c092e5$58f6a8a0$0deca8c0@Ulysses> (raw)
Message-ID: <20010209221200.KYRbCdol5vsgX6G2WH41H2BtUlO1JF_ztxo4OD_l2h4@z> (raw)
In-Reply-To: Pine.GSO.3.96.1010209212607.13007B-100000@delta.ds2.pg.gda.pl
> > Another question. I know with mips32 and mips64 we can do run-time
detection
> > reliably. What about other existing processors?
>
> I've sent a quote from an IDT manual recently. It recommended to use the
> FPU implementation ID to check if an FP hw is present. I believe it
> should work for any sane implementation of a MIPS CPU. See the mail for
> details.
The best method I know for post-R3000 CPUs is to
write and read back the CU1 bit of the Status register.
CPUs without an integrated FPU will not have a flip-flop
for the bit, and will read back a 0 even after writing a 1.
There was never any architectural requirement that
this be so, however, and this cannot be absolutely
guaranteed to work. If anyone has a counter-example,
however, I'd be interested in hearing about it.
Kevin K.
next prev parent reply other threads:[~2001-02-09 22:08 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2001-02-08 20:27 config option vs. run-time detection (the debate continues ...) Jun Sun
2001-02-08 22:06 ` Kevin D. Kissell
2001-02-08 22:06 ` Kevin D. Kissell
2001-02-08 22:58 ` Jun Sun
2001-02-09 0:25 ` Kevin D. Kissell
2001-02-09 0:25 ` Kevin D. Kissell
2001-02-09 11:48 ` Maciej W. Rozycki
2001-02-09 12:56 ` Kevin D. Kissell
2001-02-09 12:56 ` Kevin D. Kissell
2001-02-09 13:06 ` Maciej W. Rozycki
2001-02-09 19:59 ` Jun Sun
2001-02-09 20:39 ` Maciej W. Rozycki
2001-02-09 21:31 ` Jun Sun
2001-02-10 9:01 ` Maciej W. Rozycki
2001-02-12 18:21 ` Jun Sun
2001-02-13 18:31 ` Maciej W. Rozycki
2001-02-09 22:12 ` Kevin D. Kissell [this message]
2001-02-09 22:12 ` Kevin D. Kissell
2001-02-10 9:05 ` Maciej W. Rozycki
2001-02-09 19:58 ` Florian Lohoff
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