RE: [PATCH 2/3] clk: samsung: clk-pll: Add support for pll_309

["Alim Akhtar" <alim.akhtar@samsung.com>]

> -----Original Message-----
> From: Aiden Isik via B4 Relay
> <devnull+aidenisik.member.fsf.org@kernel.org>
> Sent: Monday, August 17, 2026 3:47 PM
> To: Krzysztof Kozlowski <krzk@kernel.org>; Sylwester Nawrocki
> <s.nawrocki@samsung.com>; Chanwoo Choi <cw00.choi@samsung.com>;
> Peter Griffin <peter.griffin@linaro.org>; Alim Akhtar
> <alim.akhtar@samsung.com>; Michael Turquette
> <mturquette@baylibre.com>; Stephen Boyd <sboyd@kernel.org>; Brian
> Masney <bmasney@redhat.com>; Rob Herring <robh@kernel.org>; Conor
> Dooley <conor+dt@kernel.org>; Kees Cook <kees@kernel.org>; Gustavo A.
> R. Silva <gustavoars@kernel.org>
> Cc: linux-samsung-soc@vger.kernel.org; linux-clk@vger.kernel.org;
> devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> kernel@vger.kernel.org; linux-hardening@vger.kernel.org; Aiden Isik
> <aidenisik+git@member.fsf.org>
> Subject: [PATCH 2/3] clk: samsung: clk-pll: Add support for pll_309
> 
> From: Aiden Isik <aidenisik@member.fsf.org>
> 
> pll_309 (referred to in the downstream kernel sources as frd_309_rpll) is one
> of two PLLs used in the Exynos5515 SoC. It is an integer/fractional PLL with an
> FVCO of 600-2400MHz.
> 
> It has the same locktime (500), and kdiv/mdiv/pdiv/sdiv masks and shifts as
> pll_531x, so it can be handled in exactly the same way.
> 
> When defining a PLL, the "con" parameter should be set to the CON3 register,
> like this:
> 
> PLL(pll_309, CLK_FOUT_AUD_PLL, "fout_aud_pll", "oscclk",
>     PLL_LOCKTIME_PLL_AUD, PLL_CON3_PLL_AUD, NULL),
> 
This patch does more then what is described above; please explain all changes in the commit. 
If needed, split this into common and pll_309 specific changes. Thanks!

Regards,
Alim