[PATCH 0/8] 34XX: PM: Workarounds to get omap3 to retention 2nd.

[PATCH 0/8] 34XX: PM: Workarounds to get omap3 to retention 2nd.

[Högander Jouni]

This patch set contains all workarounds that are needed to get omap3
to retention. Also patch from Tero Kristo to get PM to work if using
serial console is included in this set. Basically all patches in this
set should be reverted one by one as correct fixes are implemented and
applied.

This patch set superseeds earlier version sent 2008-06-09 9:32:40.

-- 
Jouni Högander

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[PATCH 1/8] 34XX: PM: Workaround for taking care of gpio clocks

[Jouni Hogander]

In omap3 gpios 2-6 are in per domain. Clocks for these should be
disabled. This patch is needed until gpio driver disables gpio clocks
when they are not needed.

Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com>
---
 arch/arm/mach-omap2/pm34xx.c |   48 +++++++++++++++++++++++++++++++++++++++++-
 1 files changed, 47 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 40a5828..be3c74f 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -52,6 +52,34 @@ static void (*saved_idle)(void);
 
 static struct powerdomain *mpu_pwrdm;
 
+/* XXX This is for gpio fclk hack. Will be removed as gpio driver
+ * handles fcks correctly */
+#define NUM_OF_PERGPIOS 5
+static struct clk *gpio_fcks[NUM_OF_PERGPIOS];
+static struct clk *gpio_icks[NUM_OF_PERGPIOS];
+
+/* XXX This is for gpio fclk hack. Will be removed as gpio driver
+ * handles fcks correctly */
+static void per_gpio_clk_enable(void)
+{
+	int i;
+	for (i = 1; i < NUM_OF_PERGPIOS + 1; i++) {
+		clk_enable(gpio_icks[i-1]);
+		clk_enable(gpio_fcks[i-1]);
+	}
+}
+
+/* XXX This is for gpio fclk hack. Will be removed as gpio driver
+ * handles fcks correctly */
+static void per_gpio_clk_disable(void)
+{
+	int i;
+	for (i = 1; i < NUM_OF_PERGPIOS + 1; i++) {
+		clk_disable(gpio_fcks[i-1]);
+		clk_disable(gpio_icks[i-1]);
+	}
+}
+
 /* PRCM Interrupt Handler for wakeups */
 static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
 {
@@ -168,8 +196,16 @@ static void omap_sram_idle(void)
 
 	omap2_gpio_prepare_for_retention();
 
+	/* XXX This is for gpio fclk hack. Will be removed as gpio driver
+	 * handles fcks correctly */
+	per_gpio_clk_disable();
+
 	_omap_sram_idle(NULL, save_state);
 
+	/* XXX This is for gpio fclk hack. Will be removed as gpio driver
+	 * handles fcks correctly */
+	per_gpio_clk_enable();
+
 	omap2_gpio_resume_after_retention();
 }
 
@@ -354,7 +390,8 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm)
 int __init omap3_pm_init(void)
 {
 	struct power_state *pwrst;
-	int ret;
+	char clk_name[11];
+	int ret, i;
 
 	printk(KERN_ERR "Power Management for TI OMAP3.\n");
 
@@ -388,6 +425,15 @@ int __init omap3_pm_init(void)
 
 	pm_idle = omap3_pm_idle;
 
+	/* XXX This is for gpio fclk hack. Will be removed as gpio driver
+	 * handles fcks correctly */
+	for (i = 1; i < NUM_OF_PERGPIOS + 1; i++) {
+		sprintf(clk_name, "gpio%d_fck", i + 1);
+		gpio_fcks[i-1] = clk_get(NULL, clk_name);
+		sprintf(clk_name, "gpio%d_ick", i + 1);
+		gpio_icks[i-1] = clk_get(NULL, clk_name);
+	}
+
 err1:
 	return ret;
 err2:
-- 
1.5.5

[PATCH 2/8] PRCM: Workaround for pwrdn_x control

[Jouni Hogander]

Clock path should be powered down only after all it's clients are
properly disabled. Generally we don't have working implementation for
checking wether some clock is enabled or disabled.

Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com>
---
 arch/arm/mach-omap2/clock.c |   11 ++++++++++-
 1 files changed, 10 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index ed15868..9099ba6 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -329,6 +329,9 @@ void omap2_clk_disable(struct clk *clk)
 {
 	if (clk->usecount > 0 && !(--clk->usecount)) {
 		_omap2_clk_disable(clk);
+		/* XXX Currently we don't have working code for
+		 * checking wether clock is really disabled */
+		udelay(10);
 		if (clk->parent)
 			omap2_clk_disable(clk->parent);
 		if (clk->clkdm)
@@ -974,6 +977,12 @@ void omap2_clk_disable_unused(struct clk *clk)
 		return;
 
 	printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name);
-	_omap2_clk_disable(clk);
+	/* XXX In case of omap3 we need to make sure that sequence is
+	 * correct when disabling clocks */
+	if (cpu_is_omap34xx()) {
+		omap2_clk_enable(clk);
+		omap2_clk_disable(clk);
+	} else
+		_omap2_clk_disable(clk);
 }
 #endif
-- 
1.5.5

[PATCH 3/8] 34XX: PM: Workaround for missing smartreflex driver

[Jouni Hogander]

This workaround is needed because we don't have smartreflex
driver. These configurations are taken from TI's reference code.

Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com>
---
 arch/arm/mach-omap2/pm34xx.c     |   74 ++++++++++++++++++++++++++++++++++++++
 drivers/i2c/chips/twl4030-core.c |    9 +++++
 2 files changed, 83 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index be3c74f..1476597 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -357,6 +357,25 @@ static struct platform_suspend_ops omap_pm_ops = {
 	.valid		= suspend_valid_only_mem,
 };
 
+/* PRM_VC_CMD_VAL_0 specific bits */
+#define PRM_VC_CMD_VAL0_ON		0x30
+#define PRM_VC_CMD_VAL0_ONLP		0x18
+#define PRM_VC_CMD_VAL0_RET		0x18
+#define PRM_VC_CMD_VAL0_OFF		0x18
+
+/* PRM_VC_CMD_VAL_1 specific bits */
+#define PRM_VC_CMD_VAL1_ON		0x2C
+#define PRM_VC_CMD_VAL1_ONLP		0x18
+#define PRM_VC_CMD_VAL1_RET		0x18
+#define PRM_VC_CMD_VAL1_OFF		0x18
+
+/* PRM_VOLTCTRL */
+#define PRM_VOLTCTRL_AUTO_RET		0x2
+
+/* T2 SMART REFLEX */
+#define R_SRI2C_SLAVE_ADDR		0x12
+#define R_VDD1_SR_CONTROL		0x00
+#define R_VDD2_SR_CONTROL		0x01
 static void __init prcm_setup_regs(void)
 {
 	/* setup wakup source */
@@ -369,6 +388,61 @@ static void __init prcm_setup_regs(void)
 	 * it is selected to mpu wakeup goup */
 	prm_write_mod_reg(OMAP3430_IO_EN | OMAP3430_WKUP_EN,
 			OCP_MOD, OMAP2_PRM_IRQENABLE_MPU_OFFSET);
+
+	if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0)) {
+		/* XXX These are smartreflex related and are here as long as we
+		 * have working	smartreflex driver in linux-omap tree */
+		prm_write_mod_reg((R_SRI2C_SLAVE_ADDR <<
+				    OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT) |
+				   (R_SRI2C_SLAVE_ADDR <<
+				    OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT),
+				   OMAP3430_GR_MOD,
+				   OMAP3_PRM_VC_SMPS_SA_OFFSET);
+
+		prm_write_mod_reg((R_VDD2_SR_CONTROL <<
+				    OMAP3430_VOLRA1_SHIFT) |
+				   (R_VDD1_SR_CONTROL <<
+				    OMAP3430_VOLRA0_SHIFT),
+				   OMAP3430_GR_MOD,
+				   OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET);
+
+		prm_write_mod_reg((PRM_VC_CMD_VAL0_ON <<
+				    OMAP3430_VC_CMD_ON_SHIFT) |
+				   (PRM_VC_CMD_VAL0_ONLP <<
+				    OMAP3430_VC_CMD_ONLP_SHIFT) |
+				   (PRM_VC_CMD_VAL0_RET <<
+				    OMAP3430_VC_CMD_RET_SHIFT) |
+				   (PRM_VC_CMD_VAL0_OFF <<
+				    OMAP3430_VC_CMD_OFF_SHIFT),
+				   OMAP3430_GR_MOD,
+				   OMAP3_PRM_VC_CMD_VAL_0_OFFSET);
+
+		prm_write_mod_reg((PRM_VC_CMD_VAL1_ON <<
+				    OMAP3430_VC_CMD_ON_SHIFT) |
+				   (PRM_VC_CMD_VAL1_ONLP <<
+				    OMAP3430_VC_CMD_ONLP_SHIFT) |
+				   (PRM_VC_CMD_VAL1_RET <<
+				    OMAP3430_VC_CMD_RET_SHIFT) |
+				   (PRM_VC_CMD_VAL1_OFF <<
+				    OMAP3430_VC_CMD_OFF_SHIFT),
+				   OMAP3430_GR_MOD,
+				   OMAP3_PRM_VC_CMD_VAL_1_OFFSET);
+
+		prm_write_mod_reg(OMAP3430_CMD1 |
+				   OMAP3430_RAV1,
+				   OMAP3430_GR_MOD,
+				   OMAP3_PRM_VC_CH_CONF_OFFSET);
+
+		prm_write_mod_reg(OMAP3430_MCODE_SHIFT |
+				   OMAP3430_HSEN |
+				   OMAP3430_SREN,
+				   OMAP3430_GR_MOD,
+				   OMAP3_PRM_VC_I2C_CFG_OFFSET);
+
+		prm_write_mod_reg(PRM_VOLTCTRL_AUTO_RET,
+				   OMAP3430_GR_MOD,
+				   OMAP3_PRM_VOLTCTRL_OFFSET);
+	}
 }
 
 static int __init pwrdms_setup(struct powerdomain *pwrdm)
diff --git a/drivers/i2c/chips/twl4030-core.c b/drivers/i2c/chips/twl4030-core.c
index 8822653..96e6216 100644
--- a/drivers/i2c/chips/twl4030-core.c
+++ b/drivers/i2c/chips/twl4030-core.c
@@ -119,6 +119,7 @@
 /* Few power values */
 #define R_CFG_BOOT			0x05
 #define R_PROTECT_KEY			0x0E
+#define R_DCDC_GLOBAL_CFG              0x06
 
 /* access control */
 #define KEY_UNLOCK1			0xce
@@ -709,6 +710,14 @@ static int power_companion_init(void)
 	e |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_MASTER, ctrl, R_CFG_BOOT);
 	e |= protect_pm_master();
 
+	/* XXX Enable smart reflex. Voltage scaling method should be
+	 * passed in platform data */
+	e |= twl4030_i2c_read_u8(TWL4030_MODULE_PM_RECEIVER,
+				 &ctrl, R_DCDC_GLOBAL_CFG);
+	ctrl |= 0x8;
+	e |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER,
+				  ctrl, R_DCDC_GLOBAL_CFG);
+
 	return e;
 }
 
-- 
1.5.5

[PATCH 4/8] 34XX: PM: Workaround to enable autoidle for clocks and plls

[Jouni Hogander]

This workaround enables autoidle for interface clocks and plls. Also
automatic control of external oscillator through sys_clkreq is
enabled. I think these should be done by clockfw.

Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com>
---
 arch/arm/mach-omap2/pm34xx.c |  120 ++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 120 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 1476597..ee00609 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -378,6 +378,126 @@ static struct platform_suspend_ops omap_pm_ops = {
 #define R_VDD2_SR_CONTROL		0x01
 static void __init prcm_setup_regs(void)
 {
+	/* XXX Enable interface clock autoidle for all modules. This
+	 * should be done by clockfw */
+	cm_write_mod_reg(
+		OMAP3430ES2_AUTO_MMC3 |
+		OMAP3430ES2_AUTO_ICR |
+		OMAP3430_AUTO_AES2 |
+		OMAP3430_AUTO_SHA12 |
+		OMAP3430_AUTO_DES2 |
+		OMAP3430_AUTO_MMC2 |
+		OMAP3430_AUTO_MMC1 |
+		OMAP3430_AUTO_MSPRO |
+		OMAP3430_AUTO_HDQ |
+		OMAP3430_AUTO_MCSPI4 |
+		OMAP3430_AUTO_MCSPI3 |
+		OMAP3430_AUTO_MCSPI2 |
+		OMAP3430_AUTO_MCSPI1 |
+		OMAP3430_AUTO_I2C3 |
+		OMAP3430_AUTO_I2C2 |
+		OMAP3430_AUTO_I2C1 |
+		OMAP3430_AUTO_UART2 |
+		OMAP3430_AUTO_UART1 |
+		OMAP3430_AUTO_GPT11 |
+		OMAP3430_AUTO_GPT10 |
+		OMAP3430_AUTO_MCBSP5 |
+		OMAP3430_AUTO_MCBSP1 |
+		OMAP3430ES1_AUTO_FAC | /* This is es1 only */
+		OMAP3430_AUTO_MAILBOXES |
+		OMAP3430_AUTO_OMAPCTRL |
+		OMAP3430ES1_AUTO_FSHOSTUSB |
+		OMAP3430_AUTO_HSOTGUSB |
+		OMAP3430ES1_AUTO_D2D | /* This is es1 only */
+		OMAP3430_AUTO_SSI,
+		CORE_MOD, CM_AUTOIDLE1);
+
+	cm_write_mod_reg(
+		OMAP3430_AUTO_PKA |
+		OMAP3430_AUTO_AES1 |
+		OMAP3430_AUTO_RNG |
+		OMAP3430_AUTO_SHA11 |
+		OMAP3430_AUTO_DES1,
+		CORE_MOD, CM_AUTOIDLE2);
+
+	if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0)) {
+		cm_write_mod_reg(
+			OMAP3430ES2_AUTO_USBTLL,
+			CORE_MOD, CM_AUTOIDLE3);
+	}
+
+	cm_write_mod_reg(
+		OMAP3430_AUTO_WDT2 |
+		OMAP3430_AUTO_WDT1 |
+		OMAP3430_AUTO_GPIO1 |
+		OMAP3430_AUTO_32KSYNC |
+		OMAP3430_AUTO_GPT12 |
+		OMAP3430_AUTO_GPT1 ,
+		WKUP_MOD, CM_AUTOIDLE);
+
+	cm_write_mod_reg(
+		OMAP3430_AUTO_DSS,
+		OMAP3430_DSS_MOD,
+		CM_AUTOIDLE);
+
+	cm_write_mod_reg(
+		OMAP3430_AUTO_CAM,
+		OMAP3430_CAM_MOD,
+		CM_AUTOIDLE);
+
+	cm_write_mod_reg(
+		OMAP3430_AUTO_GPIO6 |
+		OMAP3430_AUTO_GPIO5 |
+		OMAP3430_AUTO_GPIO4 |
+		OMAP3430_AUTO_GPIO3 |
+		OMAP3430_AUTO_GPIO2 |
+		OMAP3430_AUTO_WDT3 |
+		OMAP3430_AUTO_UART3 |
+		OMAP3430_AUTO_GPT9 |
+		OMAP3430_AUTO_GPT8 |
+		OMAP3430_AUTO_GPT7 |
+		OMAP3430_AUTO_GPT6 |
+		OMAP3430_AUTO_GPT5 |
+		OMAP3430_AUTO_GPT4 |
+		OMAP3430_AUTO_GPT3 |
+		OMAP3430_AUTO_GPT2 |
+		OMAP3430_AUTO_MCBSP4 |
+		OMAP3430_AUTO_MCBSP3 |
+		OMAP3430_AUTO_MCBSP2,
+		OMAP3430_PER_MOD,
+		CM_AUTOIDLE);
+
+	if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0)) {
+		cm_write_mod_reg(
+			OMAP3430ES2_AUTO_USBHOST,
+			OMAP3430ES2_USBHOST_MOD,
+			CM_AUTOIDLE);
+	}
+
+	/* XXX Set all plls to autoidle. This is needed until autoidle is
+	 * enabled by clockfw */
+	cm_write_mod_reg(1 << OMAP3430_CLKTRCTRL_IVA2_SHIFT,
+			 OMAP3430_IVA2_MOD,
+			 CM_AUTOIDLE2);
+	cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT,
+			 MPU_MOD,
+			 CM_AUTOIDLE2);
+	cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
+			 (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT),
+			 PLL_MOD,
+			 CM_AUTOIDLE);
+	cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
+			 PLL_MOD,
+			 CM_AUTOIDLE2);
+
+	/* XXX Enable control of expternal oscillator through
+	 * sys_clkreq. I think clockfw should provide means to do this
+	 */
+	prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
+			     1 << OMAP_AUTOEXTCLKMODE_SHIFT,
+			     OMAP3430_GR_MOD,
+			     OMAP3_PRM_CLKSRC_CTRL_OFFSET);
+
 	/* setup wakup source */
 	prm_write_mod_reg(OMAP3430_EN_IO | OMAP3430_EN_GPIO1 | OMAP3430_EN_GPT1,
 			  WKUP_MOD, PM_WKEN);
-- 
1.5.5

[PATCH 5/8] 34XX: PM: Workaround to reset all wkdeps

[Jouni Hogander]

This workaround is needed until powerdomain code resets wkdeps.

Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com>
---
 arch/arm/mach-omap2/pm34xx.c |   20 ++++++++++++++++++--
 1 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index ee00609..29ef5a8 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -378,6 +378,20 @@ static struct platform_suspend_ops omap_pm_ops = {
 #define R_VDD2_SR_CONTROL		0x01
 static void __init prcm_setup_regs(void)
 {
+	/* XXX Reset all wkdeps. This should be done when initializing
+	 * powerdomains */
+	prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
+	prm_write_mod_reg(0, MPU_MOD, PM_WKDEP);
+	prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP);
+	prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP);
+	prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP);
+	prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP);
+	if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0)) {
+		prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP);
+		prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
+	} else
+		prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
+
 	/* XXX Enable interface clock autoidle for all modules. This
 	 * should be done by clockfw */
 	cm_write_mod_reg(
@@ -589,6 +603,10 @@ int __init omap3_pm_init(void)
 
 	printk(KERN_ERR "Power Management for TI OMAP3.\n");
 
+	/* XXX prcm_setup_regs needs to be before enabling hw
+	 * supervised mode for powerdomains */
+	prcm_setup_regs();
+
 	ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
 			  (irq_handler_t)prcm_interrupt_handler,
 			  IRQF_DISABLED, "prcm", NULL);
@@ -615,8 +633,6 @@ int __init omap3_pm_init(void)
 
 	suspend_set_ops(&omap_pm_ops);
 
-	prcm_setup_regs();
-
 	pm_idle = omap3_pm_idle;
 
 	/* XXX This is for gpio fclk hack. Will be removed as gpio driver
-- 
1.5.5

[PATCH 6/8] 34XX: PM: Workaround to check wether any fck is active before entering sleep

[Jouni Hogander]

This workaround shouldn't be needed when all drivers are configuring
their sysconfig registers properly and setting their requirements
through omap-pm-srf.

Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com>
---
 arch/arm/mach-omap2/pm34xx.c |   39 +++++++++++++++++++++++++++++++++++++++
 1 files changed, 39 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 29ef5a8..0f42de7 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -80,6 +80,13 @@ static void per_gpio_clk_disable(void)
 	}
 }
 
+/* XXX This is for gpio fclk hack. Will be removed as gpio driver
+ * handles fcks correctly */
+static void gpio_fclk_mask(u32 *fclk)
+{
+	*fclk &= ~(0x1f << 13);
+}
+
 /* PRCM Interrupt Handler for wakeups */
 static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
 {
@@ -209,10 +216,42 @@ static void omap_sram_idle(void)
 	omap2_gpio_resume_after_retention();
 }
 
+static int omap3_fclks_active(void)
+{
+	u32 fck_core1 = 0, fck_core3 = 0, fck_sgx = 0, fck_dss = 0,
+		fck_cam = 0, fck_per = 0, fck_usbhost = 0;
+
+	fck_core1 = cm_read_mod_reg(CORE_MOD,
+				    CM_FCLKEN1);
+	if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0)) {
+		fck_core3 = cm_read_mod_reg(CORE_MOD,
+					    OMAP3430ES2_CM_FCLKEN3);
+		fck_sgx = cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
+					  CM_FCLKEN);
+		fck_usbhost = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
+					      CM_FCLKEN);
+	} else
+		fck_sgx = cm_read_mod_reg(GFX_MOD,
+					  OMAP3430ES2_CM_FCLKEN3);
+	fck_dss = cm_read_mod_reg(OMAP3430_DSS_MOD,
+				  CM_FCLKEN);
+	fck_cam = cm_read_mod_reg(OMAP3430_CAM_MOD,
+				  CM_FCLKEN);
+	fck_per = cm_read_mod_reg(OMAP3430_PER_MOD,
+				  CM_FCLKEN);
+	gpio_fclk_mask(&fck_per);
+	if (fck_core1 | fck_core3 | fck_sgx | fck_dss |
+	    fck_cam | fck_per | fck_usbhost)
+		return 1;
+	return 0;
+}
+
 static int omap3_can_sleep(void)
 {
 	if (!enable_dyn_sleep)
 		return 0;
+	if (omap3_fclks_active())
+		return 0;
 	if (atomic_read(&sleep_block) > 0)
 		return 0;
 	return 1;
-- 
1.5.5

[PATCH 7/8] 34XX: PM: Workaround to disable mmc

[Jouni Hogander]

Current hsmmc is not pm friendly. Disable it because it prevents omap3
retention

Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com>
---
 arch/arm/configs/omap_3430sdp_defconfig |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/configs/omap_3430sdp_defconfig b/arch/arm/configs/omap_3430sdp_defconfig
index 947c25f..ee902ae 100644
--- a/arch/arm/configs/omap_3430sdp_defconfig
+++ b/arch/arm/configs/omap_3430sdp_defconfig
@@ -1043,7 +1043,7 @@ CONFIG_USB_ZERO=y
 # CONFIG_USB_G_SERIAL is not set
 # CONFIG_USB_MIDI_GADGET is not set
 # CONFIG_USB_G_PRINTER is not set
-CONFIG_MMC=y
+# CONFIG_MMC is not set
 # CONFIG_MMC_DEBUG is not set
 # CONFIG_MMC_UNSAFE_RESUME is not set
 
-- 
1.5.5

[PATCH 8/8] Added sleep support to UART

[Jouni Hogander]

From: Tero Kristo <tero.kristo@nokia.com>

UART usage (e.g. serial console) now denies sleep for 5 seconds. This
makes it possible to use serial console when dynamic idle is
enabled. Write 1 to /sys/power/uart_clocks_off_while_sleep to enable
uart clock disable on idle. Without this omap won't enter retention.

Also moved code from pm-debug.c to serial.c, and made pm24xx.c use
this new implementation.

Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com>
---
 arch/arm/mach-omap2/pm-debug.c     |  132 --------------------------------
 arch/arm/mach-omap2/pm.c           |   37 ++++++++--
 arch/arm/mach-omap2/pm.h           |    9 +--
 arch/arm/mach-omap2/pm24xx.c       |   57 ++++++++------
 arch/arm/mach-omap2/pm34xx.c       |   16 ++++
 arch/arm/mach-omap2/serial.c       |  148 ++++++++++++++++++++++++++++++++++++
 include/asm-arm/arch-omap/common.h |    3 +
 7 files changed, 233 insertions(+), 169 deletions(-)

diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index a32f11f..61d4501 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -37,138 +37,6 @@
 #ifdef CONFIG_PM_DEBUG
 int omap2_pm_debug = 0;
 
-static int serial_console_clock_disabled;
-static int serial_console_uart;
-static unsigned int serial_console_next_disable;
-
-static struct clk *console_iclk, *console_fclk;
-
-static void serial_console_kick(void)
-{
-	serial_console_next_disable = omap2_read_32k_sync_counter();
-	/* Keep the clocks on for 4 secs */
-	serial_console_next_disable += 4 * 32768;
-}
-
-static void serial_wait_tx(void)
-{
-	static const unsigned long uart_bases[3] = {
-		0x4806a000, 0x4806c000, 0x4806e000
-	};
-	unsigned long lsr_reg;
-	int looped = 0;
-
-	/* Wait for TX FIFO and THR to get empty */
-	lsr_reg = IO_ADDRESS(uart_bases[serial_console_uart - 1] + (5 << 2));
-	while ((__raw_readb(lsr_reg) & 0x60) != 0x60)
-		looped = 1;
-	if (looped)
-		serial_console_kick();
-}
-
-u32 omap2_read_32k_sync_counter(void)
-{
-        return omap_readl(OMAP2_32KSYNCT_BASE + 0x0010);
-}
-
-void serial_console_fclk_mask(u32 *f1, u32 *f2)
-{
-	switch (serial_console_uart)  {
-	case 1:
-		*f1 &= ~(1 << 21);
-		break;
-	case 2:
-		*f1 &= ~(1 << 22);
-		break;
-	case 3:
-		*f2 &= ~(1 << 2);
-		break;
-	}
-}
-
-void serial_console_sleep(int enable)
-{
-	if (console_iclk == NULL || console_fclk == NULL)
-		return;
-
-	if (enable) {
-		BUG_ON(serial_console_clock_disabled);
-		if (clk_get_usecount(console_fclk) == 0)
-			return;
-		if ((int) serial_console_next_disable - (int) omap2_read_32k_sync_counter() >= 0)
-			return;
-		serial_wait_tx();
-		clk_disable(console_iclk);
-		clk_disable(console_fclk);
-		serial_console_clock_disabled = 1;
-	} else {
-		int serial_wakeup = 0;
-		u32 l;
-
-		switch (serial_console_uart)  {
-		case 1:
-			l = prm_read_mod_reg(CORE_MOD, PM_WKST1);
-			if (l & OMAP24XX_ST_UART1)
-				serial_wakeup = 1;
-			break;
-		case 2:
-			l = prm_read_mod_reg(CORE_MOD, PM_WKST1);
-			if (l & OMAP24XX_ST_UART2)
-				serial_wakeup = 1;
-			break;
-		case 3:
-			l = prm_read_mod_reg(CORE_MOD, OMAP24XX_PM_WKST2);
-			if (l & OMAP24XX_ST_UART3)
-				serial_wakeup = 1;
-			break;
-		}
-		if (serial_wakeup)
-			serial_console_kick();
-		if (!serial_console_clock_disabled)
-			return;
-		clk_enable(console_iclk);
-		clk_enable(console_fclk);
-		serial_console_clock_disabled = 0;
-	}
-}
-
-void pm_init_serial_console(void)
-{
-	const struct omap_serial_console_config *conf;
-	char name[16];
-
-	conf = omap_get_config(OMAP_TAG_SERIAL_CONSOLE,
-			       struct omap_serial_console_config);
-	if (conf == NULL)
-		return;
-	if (conf->console_uart > 3 || conf->console_uart < 1)
-		return;
-	serial_console_uart = conf->console_uart;
-	sprintf(name, "uart%d_fck", conf->console_uart);
-	console_fclk = clk_get(NULL, name);
-	if (IS_ERR(console_fclk))
-		console_fclk = NULL;
-	name[6] = 'i';
-	console_iclk = clk_get(NULL, name);
-	if (IS_ERR(console_fclk))
-		console_iclk = NULL;
-	if (console_fclk == NULL || console_iclk == NULL) {
-		serial_console_uart = 0;
-		return;
-	}
-	switch (serial_console_uart) {
-	case 1:
-		prm_set_mod_reg_bits(OMAP24XX_ST_UART1, CORE_MOD, PM_WKEN1);
-		break;
-	case 2:
-		prm_set_mod_reg_bits(OMAP24XX_ST_UART2, CORE_MOD, PM_WKEN1);
-		break;
-	case 3:
-		prm_set_mod_reg_bits(OMAP24XX_ST_UART3, CORE_MOD, OMAP24XX_PM_WKEN2);
-		break;
-	}
-}
-
 #define DUMP_PRM_MOD_REG(mod, reg)    \
 	regs[reg_count].name = #mod "." #reg; \
 	regs[reg_count++].val = prm_read_mod_reg(mod, reg)
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index bef58d7..1b6c81a 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -31,30 +31,51 @@
 #include "pm.h"
 
 unsigned short enable_dyn_sleep;
+unsigned short uart_clocks_off_while_sleep;
 atomic_t sleep_block = ATOMIC_INIT(0);
 
+static ssize_t idle_show(struct kobject *, struct kobj_attribute *, char *);
+static ssize_t idle_store(struct kobject *k, struct kobj_attribute *,
+			  const char *buf, size_t n);
+
+static struct kobj_attribute sleep_while_idle_attr =
+	__ATTR(sleep_while_idle, 0644, idle_show, idle_store);
+
+static struct kobj_attribute uart_clocks_off_while_sleep_attr =
+	__ATTR(uart_clocks_off_while_sleep, 0644, idle_show, idle_store);
+
 static ssize_t idle_show(struct kobject *kobj, struct kobj_attribute *attr,
 			 char *buf)
 {
-	return sprintf(buf, "%hu\n", enable_dyn_sleep);
+	if (attr == &sleep_while_idle_attr)
+		return sprintf(buf, "%hu\n", enable_dyn_sleep);
+	else if (attr == &uart_clocks_off_while_sleep_attr)
+		return sprintf(buf, "%hu\n", uart_clocks_off_while_sleep);
+	else
+		return -EINVAL;
 }
 
 static ssize_t idle_store(struct kobject *kobj, struct kobj_attribute *attr,
 			  const char *buf, size_t n)
 {
 	unsigned short value;
+
 	if (sscanf(buf, "%hu", &value) != 1 ||
 	    (value != 0 && value != 1)) {
-		printk(KERN_ERR "idle_sleep_store: Invalid value\n");
+		printk(KERN_ERR "idle_store: Invalid value\n");
 		return -EINVAL;
 	}
-	enable_dyn_sleep = value;
+
+	if (attr == &sleep_while_idle_attr)
+		enable_dyn_sleep = value;
+	else if (attr == &uart_clocks_off_while_sleep_attr)
+		uart_clocks_off_while_sleep = value;
+	else
+		return -EINVAL;
+
 	return n;
 }
 
-static struct kobj_attribute sleep_while_idle_attr =
-	__ATTR(sleep_while_idle, 0644, idle_show, idle_store);
-
 void omap2_block_sleep(void)
 {
 	atomic_inc(&sleep_block);
@@ -86,6 +107,10 @@ int __init omap_pm_init(void)
 	error = sysfs_create_file(power_kobj, &sleep_while_idle_attr.attr);
 	if (error)
 		printk(KERN_ERR "sysfs_create_file failed: %d\n", error);
+	error = sysfs_create_file(power_kobj,
+				  &uart_clocks_off_while_sleep_attr.attr);
+	if (error)
+		printk(KERN_ERR "sysfs_create_file failed: %d\n", error);
 
 	return error;
 }
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 351456e..be8488a 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -17,21 +17,14 @@ extern int omap2_pm_init(void);
 extern int omap3_pm_init(void);
 
 extern unsigned short enable_dyn_sleep;
+extern unsigned short uart_clocks_off_while_sleep;
 extern atomic_t sleep_block;
 
 #ifdef CONFIG_PM_DEBUG
-extern u32 omap2_read_32k_sync_counter(void);
 extern void omap2_pm_dump(int mode, int resume, unsigned int us);
-extern void serial_console_fclk_mask(u32 *f1, u32 *f2);
-extern void pm_init_serial_console(void);
-extern void serial_console_sleep(int enable);
 extern int omap2_pm_debug;
 #else
-#define omap2_read_32k_sync_counter() 0;
-#define serial_console_sleep(enable) do; while(0)
-#define pm_init_serial_console() do; while(0)
 #define omap2_pm_dump(mode,resume,us) do; while(0)
-#define serial_console_fclk_mask(f1,f2)  do; while(0)
 #define omap2_pm_debug 0
 #endif /* CONFIG_PM_DEBUG */
 #endif
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index 69972a2..ad5078e 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -44,6 +44,7 @@
 #include <asm/arch/mux.h>
 #include <asm/arch/dma.h>
 #include <asm/arch/board.h>
+#include <asm/arch/common.h>
 
 #include "prm.h"
 #include "prm-regbits-24xx.h"
@@ -73,7 +74,10 @@ static int omap2_fclks_active(void)
 
 	f1 = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
 	f2 = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
-	serial_console_fclk_mask(&f1, &f2);
+
+	if (uart_clocks_off_while_sleep)
+		omap_serial_fclk_mask(&f1, &f2);
+
 	if (f1 | f2)
 		return 1;
 	return 0;
@@ -81,7 +85,8 @@ static int omap2_fclks_active(void)
 
 static void omap2_enter_full_retention(void)
 {
-	u32 l, sleep_time = 0;
+	u32 l = 0;
+	struct timespec sleep_time;
 
 	/* There is 1 reference hold for all children of the oscillator
 	 * clock, the following will remove it. If no one else uses the
@@ -111,28 +116,33 @@ static void omap2_enter_full_retention(void)
 
 	if (omap2_pm_debug) {
 		omap2_pm_dump(0, 0, 0);
-		sleep_time = omap2_read_32k_sync_counter();
+		getnstimeofday(&sleep_time);
 	}
 
+	if (uart_clocks_off_while_sleep)
+		omap_serial_enable_clocks(0);
+
 	/* One last check for pending IRQs to avoid extra latency due
 	 * to sleeping unnecessarily. */
 	if (omap_irq_pending())
 		goto no_sleep;
 
-	serial_console_sleep(1);
 	/* Jump to SRAM suspend code */
 	omap2_sram_suspend(OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL));
 no_sleep:
-	serial_console_sleep(0);
+	omap_serial_check_wakeup();
+	if (uart_clocks_off_while_sleep)
+		omap_serial_enable_clocks(1);
 
 	if (omap2_pm_debug) {
-		unsigned long long tmp;
-		u32 resume_time;
-
-		resume_time = omap2_read_32k_sync_counter();
-		tmp = resume_time - sleep_time;
-		tmp *= 1000000;
-		omap2_pm_dump(0, 1, tmp / 32768);
+		struct timespec t;
+		struct timespec ts_delta;
+
+		getnstimeofday(&t);
+		ts_delta = timespec_sub(t, sleep_time);
+		omap2_pm_dump(0, 1,
+			      div_s64(timespec_to_ns(&ts_delta),
+				      NSEC_PER_USEC));
 	}
 	omap2_gpio_resume_after_retention();
 
@@ -193,7 +203,7 @@ static int omap2_allow_mpu_retention(void)
 
 static void omap2_enter_mpu_retention(void)
 {
-	u32 sleep_time = 0;
+	struct timespec sleep_time;
 	int only_idle = 0;
 
 	/* Putting MPU into the WFI state while a transfer is active
@@ -222,19 +232,20 @@ static void omap2_enter_mpu_retention(void)
 
 	if (omap2_pm_debug) {
 		omap2_pm_dump(only_idle ? 2 : 1, 0, 0);
-		sleep_time = omap2_read_32k_sync_counter();
+		getnstimeofday(&sleep_time);
 	}
 
 	omap2_sram_idle();
 
 	if (omap2_pm_debug) {
-		unsigned long long tmp;
-		u32 resume_time;
-
-		resume_time = omap2_read_32k_sync_counter();
-		tmp = resume_time - sleep_time;
-		tmp *= 1000000;
-		omap2_pm_dump(only_idle ? 2 : 1, 1, tmp / 32768);
+		struct timespec t;
+		struct timespec ts_delta;
+
+		getnstimeofday(&t);
+		ts_delta = timespec_sub(t, sleep_time);
+		omap2_pm_dump(only_idle ? 2 : 1, 1,
+			      div_s64(timespec_to_ns(&ts_delta),
+				      NSEC_PER_USEC));
 	}
 }
 
@@ -250,6 +261,8 @@ static int omap2_can_sleep(void)
 		return 0;
 	if (omap_dma_running())
 		return 0;
+	if (!omap_serial_can_sleep())
+		return 0;
 
 	return 1;
 }
@@ -517,8 +530,6 @@ int __init omap2_pm_init(void)
 
 	prcm_setup_regs();
 
-	pm_init_serial_console();
-
 	/* Hack to prevent MPU retention when STI console is enabled. */
 	{
 		const struct omap_sti_console_config *sti;
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 0f42de7..743de03 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -29,6 +29,7 @@
 #include <asm/arch/pm.h>
 #include <asm/arch/clockdomain.h>
 #include <asm/arch/powerdomain.h>
+#include <asm/arch/common.h>
 
 #include "cm.h"
 #include "cm-regbits-34xx.h"
@@ -93,6 +94,9 @@ static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
 	u32 wkst, irqstatus_mpu;
 	u32 fclk, iclk;
 
+	/* Check if we woke up to serial console activity */
+	omap_serial_check_wakeup();
+
 	/* WKUP */
 	wkst = prm_read_mod_reg(WKUP_MOD, PM_WKST);
 	if (wkst) {
@@ -207,8 +211,14 @@ static void omap_sram_idle(void)
 	 * handles fcks correctly */
 	per_gpio_clk_disable();
 
+	if (uart_clocks_off_while_sleep)
+		omap_serial_enable_clocks(0);
+
 	_omap_sram_idle(NULL, save_state);
 
+	if (uart_clocks_off_while_sleep)
+		omap_serial_enable_clocks(1);
+
 	/* XXX This is for gpio fclk hack. Will be removed as gpio driver
 	 * handles fcks correctly */
 	per_gpio_clk_enable();
@@ -240,6 +250,10 @@ static int omap3_fclks_active(void)
 	fck_per = cm_read_mod_reg(OMAP3430_PER_MOD,
 				  CM_FCLKEN);
 	gpio_fclk_mask(&fck_per);
+
+	if (uart_clocks_off_while_sleep)
+		omap_serial_fclk_mask(&fck_core1, &fck_per);
+
 	if (fck_core1 | fck_core3 | fck_sgx | fck_dss |
 	    fck_cam | fck_per | fck_usbhost)
 		return 1;
@@ -254,6 +268,8 @@ static int omap3_can_sleep(void)
 		return 0;
 	if (atomic_read(&sleep_block) > 0)
 		return 0;
+	if (!omap_serial_can_sleep())
+		return 0;
 	return 1;
 }
 
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index b0fa582..905594a 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -22,9 +22,66 @@
 
 #include <asm/arch/common.h>
 #include <asm/arch/board.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/control.h>
+
+#include "prm.h"
+#include "pm.h"
+
+#define SERIAL_AWAKE_TIME 5
 
 static struct clk *uart_ick[OMAP_MAX_NR_PORTS];
 static struct clk *uart_fck[OMAP_MAX_NR_PORTS];
+static struct timespec omap_serial_next_sleep;
+
+#ifdef CONFIG_ARCH_OMAP24XX
+static const u32 omap2_uart_wk_st[OMAP_MAX_NR_PORTS] = {
+	OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKST1),
+	OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKST1),
+	OMAP2420_PRM_REGADDR(CORE_MOD, OMAP24XX_PM_WKST2)
+};
+static const u32 omap2_uart_wk_en[OMAP_MAX_NR_PORTS] = {
+	OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKEN1),
+	OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKEN1),
+	OMAP2420_PRM_REGADDR(CORE_MOD, OMAP24XX_PM_WKEN2),
+};
+static const u32 omap2_uart_wk_bit[OMAP_MAX_NR_PORTS] = {
+	OMAP24XX_ST_UART1, OMAP24XX_ST_UART2, OMAP24XX_ST_UART3
+};
+#endif
+
+#ifdef CONFIG_ARCH_OMAP34XX
+static const u32 omap3_uart_wk_st[OMAP_MAX_NR_PORTS] = {
+	OMAP34XX_PRM_REGADDR(CORE_MOD, PM_WKST1),
+	OMAP34XX_PRM_REGADDR(CORE_MOD, PM_WKST1),
+	OMAP34XX_PRM_REGADDR(OMAP3430_PER_MOD, PM_WKST1)
+};
+static const u32 omap3_uart_wk_en[OMAP_MAX_NR_PORTS] = {
+	OMAP34XX_PRM_REGADDR(CORE_MOD, PM_WKEN1),
+	OMAP34XX_PRM_REGADDR(CORE_MOD, PM_WKEN1),
+	OMAP34XX_PRM_REGADDR(OMAP3430_PER_MOD, PM_WKEN1)
+};
+static const u32 omap3_uart_wk_bit[OMAP_MAX_NR_PORTS] = {
+	OMAP3430_ST_UART1, OMAP3430_ST_UART2, OMAP3430_ST_UART3
+};
+#endif
+
+static const u32 *omap_uart_wk_st;
+static const u32 *omap_uart_wk_en;
+static const u32 *omap_uart_wk_bit;
+
+/* UART padconfig registers, these may differ if non-default padconfig
+   is used */
+#define CONTROL_PADCONF_UART1_RX 0x182
+#define CONTROL_PADCONF_UART2_RX 0x17A
+#define CONTROL_PADCONF_UART3_RX 0x19E
+#define PADCONF_WAKEUP_ST 0x8000
+
+static const u32 omap34xx_uart_padconf[OMAP_MAX_NR_PORTS] = {
+	CONTROL_PADCONF_UART1_RX,
+	CONTROL_PADCONF_UART2_RX,
+	CONTROL_PADCONF_UART3_RX
+};
 
 static struct plat_serial8250_port serial_platform_data[] = {
 	{
@@ -83,6 +140,13 @@ static inline void __init omap_serial_reset(struct plat_serial8250_port *p)
 	serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 << 2) | (1 << 0));
 }
 
+static void omap_serial_kick(void)
+{
+	getnstimeofday(&omap_serial_next_sleep);
+	timespec_add_ns(&omap_serial_next_sleep, (s64)SERIAL_AWAKE_TIME *
+		NSEC_PER_SEC);
+}
+
 void omap_serial_enable_clocks(int enable)
 {
 	int i;
@@ -99,6 +163,67 @@ void omap_serial_enable_clocks(int enable)
 	}
 }
 
+void omap_serial_fclk_mask(u32 *f1, u32 *f2)
+{
+	if (uart_ick[0])
+		*f1 &= ~(1 << uart_fck[0]->enable_bit);
+	if (uart_ick[1])
+		*f1 &= ~(1 << uart_fck[1]->enable_bit);
+	if (uart_ick[2])
+		*f2 &= ~(1 << uart_fck[2]->enable_bit);
+}
+
+void omap_serial_check_wakeup(void)
+{
+	int i;
+
+
+	for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
+		if (!uart_ick[i])
+			continue;
+
+		if (cpu_is_omap34xx())
+			if (omap_ctrl_readw(omap34xx_uart_padconf[i]) &
+			    PADCONF_WAKEUP_ST) {
+				omap_serial_kick();
+				return;
+			}
+
+		if (__raw_readl(omap_uart_wk_st[i]) &
+		    omap_uart_wk_bit[i]) {
+			omap_serial_kick();
+			return;
+		}
+	}
+}
+
+int omap_serial_can_sleep(void)
+{
+	int i;
+	struct timespec t;
+
+	struct plat_serial8250_port *p = serial_platform_data;
+
+	getnstimeofday(&t);
+
+	for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
+		if (!uart_ick[i])
+			continue;
+		/* Check if we have data in the transmit buffer */
+		if ((serial_read_reg(p + i, UART_LSR) &
+			(UART_LSR_TEMT|UART_LSR_THRE))
+			!= (UART_LSR_TEMT|UART_LSR_THRE)) {
+				omap_serial_kick();
+				return 0;
+		}
+	}
+
+	if (timespec_compare(&t, &omap_serial_next_sleep) < 0)
+		return 0;
+
+	return 1;
+}
+
 void __init omap_serial_init(void)
 {
 	int i;
@@ -116,8 +241,25 @@ void __init omap_serial_init(void)
 	if (info == NULL)
 		return;
 
+#ifdef CONFIG_ARCH_OMAP24XX
+	if (cpu_is_omap242x()) {
+		omap_uart_wk_st = omap2_uart_wk_st;
+		omap_uart_wk_en = omap2_uart_wk_en;
+		omap_uart_wk_bit = omap2_uart_wk_bit;
+	}
+#endif
+
+#ifdef CONFIG_ARCH_OMAP34XX
+	if (cpu_is_omap34xx()) {
+		omap_uart_wk_st = omap3_uart_wk_st;
+		omap_uart_wk_en = omap3_uart_wk_en;
+		omap_uart_wk_bit = omap3_uart_wk_bit;
+	}
+#endif
+
 	for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
 		struct plat_serial8250_port *p = serial_platform_data + i;
+		u32 v;
 
 		if (!(info->enabled_uarts & (1 << i))) {
 			p->membase = NULL;
@@ -142,7 +284,13 @@ void __init omap_serial_init(void)
 			clk_enable(uart_fck[i]);
 
 		omap_serial_reset(p);
+
+		v = __raw_readl(omap_uart_wk_en[i]);
+		v |= omap_uart_wk_bit[i];
+		__raw_writel(v, omap_uart_wk_en[i]);
 	}
+
+	omap_serial_kick();
 }
 
 static struct platform_device serial_device = {
diff --git a/include/asm-arm/arch-omap/common.h b/include/asm-arm/arch-omap/common.h
index 7a48fc9..5d2033b 100644
--- a/include/asm-arm/arch-omap/common.h
+++ b/include/asm-arm/arch-omap/common.h
@@ -35,6 +35,9 @@ extern void omap_map_common_io(void);
 extern struct sys_timer omap_timer;
 extern void omap_serial_init(void);
 extern void omap_serial_enable_clocks(int enable);
+extern int omap_serial_can_sleep(void);
+extern void omap_serial_fclk_mask(u32 *f1, u32 *f2);
+void omap_serial_check_wakeup(void);
 #ifdef CONFIG_I2C_OMAP
 extern int omap_register_i2c_bus(int bus_id, u32 clkrate,
 				 struct i2c_board_info const *info,
-- 
1.5.5

Re: [PATCH 7/8] 34XX: PM: Workaround to disable mmc

[Felipe Balbi]

On Tue, 17 Jun 2008 10:31:11 +0300, Jouni Hogander
<jouni.hogander@nokia.com> wrote:
> Current hsmmc is not pm friendly. Disable it because it prevents omap3
> retention

Disabling will just hide the bug. Better making it modular
and let mmc guys dig on it.

What do you need to make it more pm friendly?

-- 
Best Regards,

Felipe Balbi
http://felipebalbi.com
me@felipebalbi.com

Re: [PATCH 7/8] 34XX: PM: Workaround to disable mmc

[Högander Jouni]

"ext Felipe Balbi" <me@felipebalbi.com> writes:

> On Tue, 17 Jun 2008 10:31:11 +0300, Jouni Hogander
> <jouni.hogander@nokia.com> wrote:
>> Current hsmmc is not pm friendly. Disable it because it prevents omap3
>> retention
>
> Disabling will just hide the bug. Better making it modular
> and let mmc guys dig on it.

Ok, I can change it, if this set needs to be sent again. I think
disabling mmc increases visibility of its PM problems. I mean missing
mmc driver is more visible than missing PM in this case.

>
> What do you need to make it more pm friendly?

Not to prevent omap retention.

>
> -- 
> Best Regards,
>
> Felipe Balbi
> http://felipebalbi.com
> me@felipebalbi.com
>
>
>

-- 
Jouni Högander

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RE: [PATCH 7/8] 34XX: PM: Workaround to disable mmc

[Woodruff, Richard]

> On Tue, 17 Jun 2008 10:31:11 +0300, Jouni Hogander
> <jouni.hogander@nokia.com> wrote:
> > Current hsmmc is not pm friendly. Disable it because it prevents omap3
> > retention
>
> Disabling will just hide the bug. Better making it modular
> and let mmc guys dig on it.
>
> What do you need to make it more pm friendly?

Madhu recently traded work arounds in one of our MMC trees.  A rest of command line was used instead of toggle of idle handshakes.  Hardware designers did confirm it being needed.  I'll forward a version.

Regards,
Richard W.

Re: [PATCH 7/8] 34XX: PM: Workaround to disable mmc

[Koen Kooi]

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1


Op 17 jun 2008, om 14:09 heeft Högander Jouni het volgende geschreven:

> "ext Felipe Balbi" <me@felipebalbi.com> writes:
>
>> On Tue, 17 Jun 2008 10:31:11 +0300, Jouni Hogander
>> <jouni.hogander@nokia.com> wrote:
>>> Current hsmmc is not pm friendly. Disable it because it prevents  
>>> omap3
>>> retention
>>
>> Disabling will just hide the bug. Better making it modular
>> and let mmc guys dig on it.
>
> Ok, I can change it, if this set needs to be sent again. I think
> disabling mmc increases visibility of its PM problems. I mean missing
> mmc driver is more visible than missing PM in this case.

My rootfs and kernel are on SD, so disabling SD results in the biggest  
powersaving possible: not turning on the board ;)
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.5 (Darwin)

iD8DBQFIV7BlMkyGM64RGpERAlcJAJ412DshyLeAvZhrCa0beMXsZPy2UgCeL/KQ
UKjp5Lb11vjTd9P/lSovNCU=
=36Pq
-----END PGP SIGNATURE-----
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Re: [PATCH 7/8] 34XX: PM: Workaround to disable mmc

[Madhusudhan Chikkature]

----- Original Message ----- 
From: ""Högander" Jouni" <jouni.hogander@nokia.com>
To: "ext Felipe Balbi" <me@felipebalbi.com>
Cc: <linux-omap@vger.kernel.org>
Sent: Tuesday, June 17, 2008 5:39 PM
Subject: Re: [PATCH 7/8] 34XX: PM: Workaround to disable mmc


> "ext Felipe Balbi" <me@felipebalbi.com> writes:
>
>> On Tue, 17 Jun 2008 10:31:11 +0300, Jouni Hogander
>> <jouni.hogander@nokia.com> wrote:
>>> Current hsmmc is not pm friendly. Disable it because it prevents omap3
>>> retention
>>
>> Disabling will just hide the bug. Better making it modular
>> and let mmc guys dig on it.
>
> Ok, I can change it, if this set needs to be sent again. I think
> disabling mmc increases visibility of its PM problems. I mean missing
> mmc driver is more visible than missing PM in this case.
>
>>
>> What do you need to make it more pm friendly?
>
> Not to prevent omap retention.
When are you expecting the omap to go into retention? Is it in the suspend 
path?

Regards,
Madhu
>
>>
>> -- 
>> Best Regards,
>>
>> Felipe Balbi
>> http://felipebalbi.com
>> me@felipebalbi.com
>>
>>
>>
>
> -- 
> Jouni Högander
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 

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Re: [PATCH 7/8] 34XX: PM: Workaround to disable mmc

[Högander Jouni]

"ext Madhusudhan Chikkature" <madhu.cr@ti.com> writes:

> ----- Original Message ----- 
> From: ""Högander" Jouni" <jouni.hogander@nokia.com>
> To: "ext Felipe Balbi" <me@felipebalbi.com>
> Cc: <linux-omap@vger.kernel.org>
> Sent: Tuesday, June 17, 2008 5:39 PM
> Subject: Re: [PATCH 7/8] 34XX: PM: Workaround to disable mmc
>
>
>> "ext Felipe Balbi" <me@felipebalbi.com> writes:
>>
>>> On Tue, 17 Jun 2008 10:31:11 +0300, Jouni Hogander
>>> <jouni.hogander@nokia.com> wrote:
>>>> Current hsmmc is not pm friendly. Disable it because it prevents omap3
>>>> retention
>>>
>>> Disabling will just hide the bug. Better making it modular
>>> and let mmc guys dig on it.
>>
>> Ok, I can change it, if this set needs to be sent again. I think
>> disabling mmc increases visibility of its PM problems. I mean missing
>> mmc driver is more visible than missing PM in this case.
>>
>>>
>>> What do you need to make it more pm friendly?
>>
>> Not to prevent omap retention.
> When are you expecting the omap to go into retention? Is it in the
> suspend path?

I expect it to enter retention when suspending yes. It should also
enter retention dynamically. I mean when mpu enters wfi in pm_idle loop.

-- 
Jouni Högander

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Re: [PATCH 2/8] PRCM: Workaround for pwrdn_x control

[Paul Walmsley]

Hello Jouni,

On Tue, 17 Jun 2008, Jouni Hogander wrote:

> Clock path should be powered down only after all it's clients are
> properly disabled. Generally we don't have working implementation for
> checking wether some clock is enabled or disabled.

Just wanted to revisit this again briefly.  Is this patch intended to fix 
DPLL output powerdown paths?  Or do all clocks need this for some reason?

If the former, what do you think instead about adding a custom disable 
function for the DPLL outputs which would include the udelay()?
That way we might be able to avoid adding the udelay() to all clock 
disable calls.

- Paul

>  arch/arm/mach-omap2/clock.c |   11 ++++++++++-
>  1 files changed, 10 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
> index ed15868..9099ba6 100644
> --- a/arch/arm/mach-omap2/clock.c
> +++ b/arch/arm/mach-omap2/clock.c
> @@ -329,6 +329,9 @@ void omap2_clk_disable(struct clk *clk)
>  {
>  	if (clk->usecount > 0 && !(--clk->usecount)) {
>  		_omap2_clk_disable(clk);
> +		/* XXX Currently we don't have working code for
> +		 * checking wether clock is really disabled */
> +		udelay(10);
>  		if (clk->parent)
>  			omap2_clk_disable(clk->parent);
>  		if (clk->clkdm)
> @@ -974,6 +977,12 @@ void omap2_clk_disable_unused(struct clk *clk)
>  		return;
>  
>  	printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name);
> -	_omap2_clk_disable(clk);
> +	/* XXX In case of omap3 we need to make sure that sequence is
> +	 * correct when disabling clocks */
> +	if (cpu_is_omap34xx()) {
> +		omap2_clk_enable(clk);
> +		omap2_clk_disable(clk);
> +	} else
> +		_omap2_clk_disable(clk);
>  }
>  #endif
> -- 
> 1.5.5
> 
> --
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> 


- Paul

Re: [PATCH 2/8] PRCM: Workaround for pwrdn_x control

[Högander Jouni]

"ext Paul Walmsley" <paul@pwsan.com> writes:

> Hello Jouni,
>
> On Tue, 17 Jun 2008, Jouni Hogander wrote:
>
>> Clock path should be powered down only after all it's clients are
>> properly disabled. Generally we don't have working implementation for
>> checking wether some clock is enabled or disabled.
>
> Just wanted to revisit this again briefly.  Is this patch intended to fix 
> DPLL output powerdown paths?  Or do all clocks need this for some
> reason?

Delay is needed only between client disable and output path power
down.

>
> If the former, what do you think instead about adding a custom disable 
> function for the DPLL outputs which would include the udelay()?
> That way we might be able to avoid adding the udelay() to all clock 
> disable calls.

Yes, this sounds more reasonable. I'm preparing one more version of
of workaround set. I can do this also. What do you think, is this
still workaround or are we planning to implement wait_rdy which checks
also wether clock is disabled?

>
> - Paul
>
>>  arch/arm/mach-omap2/clock.c |   11 ++++++++++-
>>  1 files changed, 10 insertions(+), 1 deletions(-)
>> 
>> diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
>> index ed15868..9099ba6 100644
>> --- a/arch/arm/mach-omap2/clock.c
>> +++ b/arch/arm/mach-omap2/clock.c
>> @@ -329,6 +329,9 @@ void omap2_clk_disable(struct clk *clk)
>>  {
>>  	if (clk->usecount > 0 && !(--clk->usecount)) {
>>  		_omap2_clk_disable(clk);
>> +		/* XXX Currently we don't have working code for
>> +		 * checking wether clock is really disabled */
>> +		udelay(10);
>>  		if (clk->parent)
>>  			omap2_clk_disable(clk->parent);
>>  		if (clk->clkdm)
>> @@ -974,6 +977,12 @@ void omap2_clk_disable_unused(struct clk *clk)
>>  		return;
>>  
>>  	printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name);
>> -	_omap2_clk_disable(clk);
>> +	/* XXX In case of omap3 we need to make sure that sequence is
>> +	 * correct when disabling clocks */
>> +	if (cpu_is_omap34xx()) {
>> +		omap2_clk_enable(clk);
>> +		omap2_clk_disable(clk);
>> +	} else
>> +		_omap2_clk_disable(clk);
>>  }
>>  #endif
>> -- 
>> 1.5.5
>> 
>> --
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>> 
>
>
> - Paul
>
>

-- 
Jouni Högander

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