* [PATCHv3 0/2] ARM: EXYNOS: Support new Exynos4415 SoC based on Cortex-A9 quad cores @ 2014-10-28 4:46 ` Chanwoo Choi 0 siblings, 0 replies; 10+ messages in thread From: Chanwoo Choi @ 2014-10-28 4:46 UTC (permalink / raw) To: kgene.kim Cc: mark.rutland, arnd, olof, tomasz.figa, inki.dae, sw0312.kim, kyungmin.park, cw00.choi, m.szyprowski, yj44.cho, jaewon02.kim, ideal.song, linux-samsung-soc, linux-kernel, linux-arm-kernel This patchset support new Exynos4415 Samsung SoC based on Cortex-A9 quad cores. Exynos4415 is a System-On-Chip (SoC) that is based on 32-bit RISC processor for Smartphone. It is desigend with the 28nm low-power high-K metal gate process and provides the best performance features. This patchset include some patches such as: - Support booting of Exynos4415 - Supoort uart/mct/adc/gic/i2c/spi/power-domain/pmu/mshc/ehci/ohci/pwm/amba Changes from v2: - Modify the name of first patch Changes from v1: - Remove legacy helper function to identify SoC - Separate out the clock patches[2] from Exynos4415 patchset[1] and sent it [2] - Separate out the pinctrl patch[3] from Exynos4415 patchset[1] and sent it [3] [1] [PATCH 0/5] Support new Exynos4415 SoC based on Cortex-A9 quad cores : https://lkml.org/lkml/2014/10/19/253 [2] [PATCHv3 1/2] clk: samsung: exynos4415: Add clocks using common clock framework : https://lkml.org/lkml/2014/10/26/159 [3] [PATCHv2] pinctrl: exynos: Add support for Exynos4415 : https://lkml.org/lkml/2014/10/26/160 Chanwoo Choi (2): ARM: EXYNOS: Add EXYNOS4415 SoC ARM: dts: Add dts files for Exynos4415 SoC arch/arm/boot/dts/exynos4415-pinctrl.dtsi | 613 +++++++++++++++++++++++++++++ arch/arm/boot/dts/exynos4415.dtsi | 627 ++++++++++++++++++++++++++++++ arch/arm/mach-exynos/Kconfig | 5 + arch/arm/mach-exynos/exynos.c | 2 + 4 files changed, 1247 insertions(+) create mode 100644 arch/arm/boot/dts/exynos4415-pinctrl.dtsi create mode 100644 arch/arm/boot/dts/exynos4415.dtsi -- 1.8.5.5 ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCHv3 0/2] ARM: EXYNOS: Support new Exynos4415 SoC based on Cortex-A9 quad cores @ 2014-10-28 4:46 ` Chanwoo Choi 0 siblings, 0 replies; 10+ messages in thread From: Chanwoo Choi @ 2014-10-28 4:46 UTC (permalink / raw) To: linux-arm-kernel This patchset support new Exynos4415 Samsung SoC based on Cortex-A9 quad cores. Exynos4415 is a System-On-Chip (SoC) that is based on 32-bit RISC processor for Smartphone. It is desigend with the 28nm low-power high-K metal gate process and provides the best performance features. This patchset include some patches such as: - Support booting of Exynos4415 - Supoort uart/mct/adc/gic/i2c/spi/power-domain/pmu/mshc/ehci/ohci/pwm/amba Changes from v2: - Modify the name of first patch Changes from v1: - Remove legacy helper function to identify SoC - Separate out the clock patches[2] from Exynos4415 patchset[1] and sent it [2] - Separate out the pinctrl patch[3] from Exynos4415 patchset[1] and sent it [3] [1] [PATCH 0/5] Support new Exynos4415 SoC based on Cortex-A9 quad cores : https://lkml.org/lkml/2014/10/19/253 [2] [PATCHv3 1/2] clk: samsung: exynos4415: Add clocks using common clock framework : https://lkml.org/lkml/2014/10/26/159 [3] [PATCHv2] pinctrl: exynos: Add support for Exynos4415 : https://lkml.org/lkml/2014/10/26/160 Chanwoo Choi (2): ARM: EXYNOS: Add EXYNOS4415 SoC ARM: dts: Add dts files for Exynos4415 SoC arch/arm/boot/dts/exynos4415-pinctrl.dtsi | 613 +++++++++++++++++++++++++++++ arch/arm/boot/dts/exynos4415.dtsi | 627 ++++++++++++++++++++++++++++++ arch/arm/mach-exynos/Kconfig | 5 + arch/arm/mach-exynos/exynos.c | 2 + 4 files changed, 1247 insertions(+) create mode 100644 arch/arm/boot/dts/exynos4415-pinctrl.dtsi create mode 100644 arch/arm/boot/dts/exynos4415.dtsi -- 1.8.5.5 ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCHv3 1/2] ARM: EXYNOS: Add EXYNOS4415 SoC 2014-10-28 4:46 ` Chanwoo Choi @ 2014-10-28 4:46 ` Chanwoo Choi -1 siblings, 0 replies; 10+ messages in thread From: Chanwoo Choi @ 2014-10-28 4:46 UTC (permalink / raw) To: kgene.kim Cc: mark.rutland, arnd, olof, tomasz.figa, inki.dae, sw0312.kim, kyungmin.park, cw00.choi, m.szyprowski, yj44.cho, jaewon02.kim, ideal.song, linux-samsung-soc, linux-kernel, linux-arm-kernel This patch add Exynos4415's SoC. Exynos4415 is based on the 32-bit RISC processor for Smartphone. Exynos4415 uses Cortex A9 quad-cores and has a target speed of 1.6GHz and provides 8.5GB/s memory bandwidth. Cc: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> --- arch/arm/mach-exynos/Kconfig | 5 +++++ arch/arm/mach-exynos/exynos.c | 2 ++ 2 files changed, 7 insertions(+) diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 46f3c0d..349c867 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -75,6 +75,11 @@ config SOC_EXYNOS4412 default y depends on ARCH_EXYNOS4 +config SOC_EXYNOS4415 + bool "SAMSUNG EXYNOS4415" + default y + depends on ARCH_EXYNOS4 + config SOC_EXYNOS5250 bool "SAMSUNG EXYNOS5250" default y diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c index 1b46460..1da531f 100644 --- a/arch/arm/mach-exynos/exynos.c +++ b/arch/arm/mach-exynos/exynos.c @@ -252,6 +252,7 @@ static const struct of_device_id exynos_dt_pmu_match[] = { { .compatible = "samsung,exynos4210-pmu" }, { .compatible = "samsung,exynos4212-pmu" }, { .compatible = "samsung,exynos4412-pmu" }, + { .compatible = "samsung,exynos4415-pmu" }, { .compatible = "samsung,exynos5250-pmu" }, { .compatible = "samsung,exynos5260-pmu" }, { .compatible = "samsung,exynos5410-pmu" }, @@ -359,6 +360,7 @@ static char const *exynos_dt_compat[] __initconst = { "samsung,exynos4210", "samsung,exynos4212", "samsung,exynos4412", + "samsung,exynos4415", "samsung,exynos5", "samsung,exynos5250", "samsung,exynos5260", -- 1.8.5.5 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCHv3 1/2] ARM: EXYNOS: Add EXYNOS4415 SoC @ 2014-10-28 4:46 ` Chanwoo Choi 0 siblings, 0 replies; 10+ messages in thread From: Chanwoo Choi @ 2014-10-28 4:46 UTC (permalink / raw) To: linux-arm-kernel This patch add Exynos4415's SoC. Exynos4415 is based on the 32-bit RISC processor for Smartphone. Exynos4415 uses Cortex A9 quad-cores and has a target speed of 1.6GHz and provides 8.5GB/s memory bandwidth. Cc: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> --- arch/arm/mach-exynos/Kconfig | 5 +++++ arch/arm/mach-exynos/exynos.c | 2 ++ 2 files changed, 7 insertions(+) diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 46f3c0d..349c867 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -75,6 +75,11 @@ config SOC_EXYNOS4412 default y depends on ARCH_EXYNOS4 +config SOC_EXYNOS4415 + bool "SAMSUNG EXYNOS4415" + default y + depends on ARCH_EXYNOS4 + config SOC_EXYNOS5250 bool "SAMSUNG EXYNOS5250" default y diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c index 1b46460..1da531f 100644 --- a/arch/arm/mach-exynos/exynos.c +++ b/arch/arm/mach-exynos/exynos.c @@ -252,6 +252,7 @@ static const struct of_device_id exynos_dt_pmu_match[] = { { .compatible = "samsung,exynos4210-pmu" }, { .compatible = "samsung,exynos4212-pmu" }, { .compatible = "samsung,exynos4412-pmu" }, + { .compatible = "samsung,exynos4415-pmu" }, { .compatible = "samsung,exynos5250-pmu" }, { .compatible = "samsung,exynos5260-pmu" }, { .compatible = "samsung,exynos5410-pmu" }, @@ -359,6 +360,7 @@ static char const *exynos_dt_compat[] __initconst = { "samsung,exynos4210", "samsung,exynos4212", "samsung,exynos4412", + "samsung,exynos4415", "samsung,exynos5", "samsung,exynos5250", "samsung,exynos5260", -- 1.8.5.5 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCHv3 2/2] ARM: dts: Add dts files for Exynos4415 SoC 2014-10-28 4:46 ` Chanwoo Choi @ 2014-10-28 4:46 ` Chanwoo Choi -1 siblings, 0 replies; 10+ messages in thread From: Chanwoo Choi @ 2014-10-28 4:46 UTC (permalink / raw) To: kgene.kim Cc: mark.rutland, arnd, olof, tomasz.figa, inki.dae, sw0312.kim, kyungmin.park, cw00.choi, m.szyprowski, yj44.cho, jaewon02.kim, ideal.song, linux-samsung-soc, linux-kernel, linux-arm-kernel, Ben Dooks, Russell King This patch adds new exynos4415.dtsi to support Exynos4415 SoC based on Cortex-A9 quad cores and includes following dt nodes: - GIC interrupt controller (GIC-400) - Pinctrl to control three GPIO parts - CMU (Clock Management Unit) for CMU/CMU_DMC/AUDSS - CPU information (Cortex-A9 quad cores) - UART to support serial port - MCT (Multi Core Timer) - ADC (Analog Digital Converter) - RTC (Real Time Clock) - I2C/SPI busses - Power domains (CAM, TV, MFC, G3D, LCD0, ISP0/1) - PMU (Performance Monitoring Unit) - MSHC (Mobile Storage Host Controller) - EHCI (Enhanced Host Controller Interface) - OHIC (Open Host Controller Interface) - USB 2.0 device with hsotg - PWM (Pluse Width Modulation) Timer - AMBA bus for PDMA0/1 - SYSRAM node for memory mapping - SYSREG node for memory mapping - PMU (Power Management Unit) node for memory mapping Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: Ben Dooks <ben-linux@fluff.org> Cc: Russell King <linux@arm.linux.org.uk> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Olof Johansson <olof@lixom.net> Cc: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com> [m.szyprowski: Add OHCI node and correct EHCI node] Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> [yj44.cho: Add mipi-phy node] Signed-off-by: YoungJun Cho <yj44.cho@samsung.com> [jaewon02: Add EHCI and SPI_2 node] Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com> [ideal.song: Add I2S0 node for audio interface] Signed-off-by: Inha Song <ideal.song@samsung.com> [tomasz.figa: Add L2 cache node] Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> Acked-by: Kyungmin Park <Kyungmin Park@samsung.com> --- arch/arm/boot/dts/exynos4415-pinctrl.dtsi | 613 +++++++++++++++++++++++++++++ arch/arm/boot/dts/exynos4415.dtsi | 627 ++++++++++++++++++++++++++++++ 2 files changed, 1240 insertions(+) create mode 100644 arch/arm/boot/dts/exynos4415-pinctrl.dtsi create mode 100644 arch/arm/boot/dts/exynos4415.dtsi diff --git a/arch/arm/boot/dts/exynos4415-pinctrl.dtsi b/arch/arm/boot/dts/exynos4415-pinctrl.dtsi new file mode 100644 index 0000000..5ce4314 --- /dev/null +++ b/arch/arm/boot/dts/exynos4415-pinctrl.dtsi @@ -0,0 +1,613 @@ +/* + * Samsung's Exynos4415 SoCs pin-mux and pin-config device tree source + * + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * + * Samsung's Exynos4415 SoCs pin-mux and pin-config optiosn are listed as device + * tree nodes are listed in this file. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +&pinctrl_0 { + gpa0: gpa0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa1: gpa1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb: gpb { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc0: gpc0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc1: gpc1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd0: gpd0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd1: gpd1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf0: gpf0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf1: gpf1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf2: gpf2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + uart0_data: uart0-data { + samsung,pins = "gpa0-0", "gpa0-1"; + samsung,pin-function = <0x2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart0_fctl: uart0-fctl { + samsung,pins = "gpa0-2", "gpa0-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart1_data: uart1-data { + samsung,pins = "gpa0-4", "gpa0-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart1_fctl: uart1-fctl { + samsung,pins = "gpa0-6", "gpa0-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart2_data: uart2-data { + samsung,pins = "gpa1-0", "gpa1-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart2_fctl: uart2-fctl { + samsung,pins = "gpa1-2", "gpa1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart3_data: uart3-data { + samsung,pins = "gpa1-4", "gpa1-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + i2c2_bus: i2c2-bus { + samsung,pins = "gpa0-6", "gpa0-7"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c3_bus: i2c3-bus { + samsung,pins = "gpa1-2", "gpa1-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + spi0_bus: spi0-bus { + samsung,pins = "gpb-0", "gpb-2", "gpb-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c4_bus: i2c4-bus { + samsung,pins = "gpb-0", "gpb-1"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + spi1_bus: spi1-bus { + samsung,pins = "gpb-4", "gpb-6", "gpb-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c5_bus: i2c5-bus { + samsung,pins = "gpb-2", "gpb-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2s1_bus: i2s1-bus { + samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", + "gpc0-4"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + i2s2_bus: i2s2-bus { + samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", + "gpc1-4"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + pcm2_bus: pcm2-bus { + samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", + "gpc1-4"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + i2c6_bus: i2c6-bus { + samsung,pins = "gpc1-3", "gpc1-4"; + samsung,pin-function = <4>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + spi2_bus: spi2-bus { + samsung,pins = "gpc1-1", "gpc1-3", "gpc1-4"; + samsung,pin-function = <5>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + pwm0_out: pwm0-out { + samsung,pins = "gpd0-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + pwm1_out: pwm1-out { + samsung,pins = "gpd0-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + pwm2_out: pwm2-out { + samsung,pins = "gpd0-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + pwm3_out: pwm3-out { + samsung,pins = "gpd0-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + i2c7_bus: i2c7-bus { + samsung,pins = "gpd0-2", "gpd0-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c0_bus: i2c0-bus { + samsung,pins = "gpd1-0", "gpd1-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c1_bus: i2c1-bus { + samsung,pins = "gpd1-2", "gpd1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; +}; + +&pinctrl_1 { + gpk0: gpk0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpk1: gpk1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpk2: gpk2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpk3: gpk3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpl0: gpl0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + mp00: mp00 { + gpio-controller; + #gpio-cells = <2>; + }; + + mp01: mp01 { + gpio-controller; + #gpio-cells = <2>; + }; + + mp02: mp02 { + gpio-controller; + #gpio-cells = <2>; + }; + + mp03: mp03 { + gpio-controller; + #gpio-cells = <2>; + }; + + mp04: mp04 { + gpio-controller; + #gpio-cells = <2>; + }; + + mp05: mp05 { + gpio-controller; + #gpio-cells = <2>; + }; + + mp06: mp06 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpm0: gpm0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpm1: gpm1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpm2: gpm2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpm3: gpm3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpm4: gpm4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx0: gpx0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&gic>; + interrupts = <0 32 0>, <0 33 0>, <0 34 0>, <0 35 0>, + <0 36 0>, <0 37 0>, <0 38 0>, <0 39 0>; + #interrupt-cells = <2>; + }; + + gpx1: gpx1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&gic>; + interrupts = <0 40 0>, <0 41 0>, <0 42 0>, <0 43 0>, + <0 44 0>, <0 45 0>, <0 46 0>, <0 47 0>; + #interrupt-cells = <2>; + }; + + gpx2: gpx2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx3: gpx3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + sd0_clk: sd0-clk { + samsung,pins = "gpk0-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd0_cmd: sd0-cmd { + samsung,pins = "gpk0-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd0_cd: sd0-cd { + samsung,pins = "gpk0-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd0_rdqs: sd0-rdqs { + samsung,pins = "gpk0-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd0_bus1: sd0-bus-width1 { + samsung,pins = "gpk0-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd0_bus4: sd0-bus-width4 { + samsung,pins = "gpk0-4", "gpk0-5", "gpk0-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd0_bus8: sd0-bus-width8 { + samsung,pins = "gpl0-0", "gpl0-1", "gpl0-2", "gpl0-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd1_clk: sd1-clk { + samsung,pins = "gpk1-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd1_cmd: sd1-cmd { + samsung,pins = "gpk1-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd1_cd: sd1-cd { + samsung,pins = "gpk1-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd1_bus1: sd1-bus-width1 { + samsung,pins = "gpk1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd1_bus4: sd1-bus-width4 { + samsung,pins = "gpk1-4", "gpk1-5", "gpk1-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd2_clk: sd2-clk { + samsung,pins = "gpk2-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <4>; + }; + + sd2_cmd: sd2-cmd { + samsung,pins = "gpk2-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <4>; + }; + + sd2_cd: sd2-cd { + samsung,pins = "gpk2-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd2_bus1: sd2-bus-width1 { + samsung,pins = "gpk2-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <4>; + }; + + sd2_bus4: sd2-bus-width4 { + samsung,pins = "gpk2-4", "gpk2-5", "gpk2-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <4>; + }; + + cam_port_b_io: cam-port-b-io { + samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3", + "gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7", + "gpm1-0", "gpm1-1", "gpm2-0", "gpm2-1"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + cam_port_b_clk_active: cam-port-b-clk-active { + samsung,pins = "gpm2-2"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + cam_port_b_clk_idle: cam-port-b-clk-idle { + samsung,pins = "gpm2-2"; + samsung,pin-function = <0>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + fimc_is_i2c0: fimc-is-i2c0 { + samsung,pins = "gpm4-0", "gpm4-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + fimc_is_i2c1: fimc-is-i2c1 { + samsung,pins = "gpm4-2", "gpm4-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + fimc_is_uart: fimc-is-uart { + samsung,pins = "gpm3-5", "gpm3-7"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; +}; + +&pinctrl_2 { + gpz: gpz { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + i2s0_bus: i2s0-bus { + samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", + "gpz-4", "gpz-5", "gpz-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + etc: etc { + gpio-controller; + #gpio-cells = <2>; + }; +}; diff --git a/arch/arm/boot/dts/exynos4415.dtsi b/arch/arm/boot/dts/exynos4415.dtsi new file mode 100644 index 0000000..078b1b8 --- /dev/null +++ b/arch/arm/boot/dts/exynos4415.dtsi @@ -0,0 +1,627 @@ +/* + * Samsung's Exynos4415 SoC device tree source + * + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * + * Samsung's Exynos4415 SoC device nodes are listed in this file. Exynos4415 + * based board files can include this file and provide values for board specfic + * bindings. + * + * Note: This file does not include device nodes for all the controllers in + * Exynos4415 SoC. As device tree coverage for Exynos4415 increases, additional + * nodes can be added to this file. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "skeleton.dtsi" +#include <dt-bindings/clock/exynos4415.h> +#include <dt-bindings/clock/exynos-audss-clk.h> + +/ { + compatible = "samsung,exynos4415"; + interrupt-parent = <&gic>; + + aliases { + pinctrl0 = &pinctrl_0; + pinctrl1 = &pinctrl_1; + pinctrl2 = &pinctrl_2; + mshc0 = &mshc_0; + mshc1 = &mshc_1; + mshc2 = &mshc_2; + spi0 = &spi_0; + spi1 = &spi_1; + spi2 = &spi_2; + i2c0 = &i2c_0; + i2c1 = &i2c_1; + i2c2 = &i2c_2; + i2c3 = &i2c_3; + i2c4 = &i2c_4; + i2c5 = &i2c_5; + i2c6 = &i2c_6; + i2c7 = &i2c_7; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0xa00>; + clock-frequency = <1600000000>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0xa01>; + clock-frequency = <1600000000>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0xa02>; + clock-frequency = <1600000000>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0xa03>; + clock-frequency = <1600000000>; + }; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + fixed-rate-clocks { + #address-cells = <1>; + #size-cells = <0>; + + xusbxti: clock@0 { + compatible = "fixed-clock"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + clock-frequency = <0>; + #clock-cells = <0>; + clock-output-names = "xusbxti"; + }; + + xxti: clock@1 { + compatible = "fixed-clock"; + reg = <1>; + clock-frequency = <0>; + #clock-cells = <0>; + clock-output-names = "xxti"; + }; + }; + + sysram@02020000 { + compatible = "mmio-sram"; + reg = <0x02020000 0x50000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x02020000 0x50000>; + + smp-sysram@0 { + compatible = "samsung,exynos4210-sysram"; + reg = <0x0 0x1000>; + }; + + smp-sysram@4f000 { + compatible = "samsung,exynos4210-sysram-ns"; + reg = <0x4f000 0x1000>; + }; + }; + + pinctrl_2: pinctrl@03860000 { + compatible = "samsung,exynos4415-pinctrl"; + reg = <0x03860000 0x1000>; + interrupts = <0 242 0>; + }; + + chipid@10000000 { + compatible = "samsung,exynos4210-chipid"; + reg = <0x10000000 0x100>; + }; + + sysreg_system_controller: syscon@10010000 { + compatible = "samsung,exynos4-sysreg", "syscon"; + reg = <0x10010000 0x400>; + }; + + pmu_system_controller: system-controller@10020000 { + compatible = "samsung,exynos4415-pmu", "syscon"; + reg = <0x10020000 0x4000>; + }; + + mipi_phy: video-phy@10020710 { + compatible = "samsung,s5pv210-mipi-video-phy"; + reg = <0x10020710 8>; + #phy-cells = <1>; + }; + + pd_cam: cam-power-domain@10024000 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10024000 0x20>; + }; + + pd_tv: tv-power-domain@10024020 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10024020 0x20>; + }; + + pd_mfc: mfc-power-domain@10024040 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10024040 0x20>; + }; + + pd_g3d: g3d-power-domain@10024060 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10024060 0x20>; + }; + + pd_lcd0: lcd0-power-domain@10024080 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10024080 0x20>; + }; + + pd_isp0: isp0-power-domain@100240A0 { + compatible = "samsung,exynos4210-pd"; + reg = <0x100240A0 0x20>; + }; + + pd_isp1: isp1-power-domain@100240E0 { + compatible = "samsung,exynos4210-pd"; + reg = <0x100240E0 0x20>; + }; + + cmu: clock-controller@10030000 { + compatible = "samsung,exynos4415-cmu"; + reg = <0x10030000 0x18000>; + #clock-cells = <1>; + }; + + rtc: rtc@10070000 { + compatible = "samsung,exynos3250-rtc"; + reg = <0x10070000 0x100>; + interrupts = <0 73 0>, <0 74 0>; + status = "disabled"; + }; + + mct@10050000 { + compatible = "samsung,exynos4210-mct"; + reg = <0x10050000 0x800>; + interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>, + <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>; + clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>; + clock-names = "fin_pll", "mct"; + }; + + gic: interrupt-controller@10481000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x10481000 0x1000>, + <0x10482000 0x1000>, + <0x10484000 0x2000>, + <0x10486000 0x2000>; + interrupts = <1 9 0xf04>; + }; + + l2c: l2-cache-controller@10502000 { + compatible = "arm,pl310-cache"; + reg = <0x10502000 0x1000>; + cache-unified; + cache-level = <2>; + arm,tag-latency = <2 2 1>; + arm,data-latency = <3 2 1>; + arm,double-linefill = <1>; + arm,double-linefill-incr = <0>; + arm,double-linefill-wrap = <1>; + arm,prefetch-drop = <1>; + arm,prefetch-offset = <7>; + }; + + cmu_dmc: clock-controller@105C0000 { + compatible = "samsung,exynos4415-cmu-dmc"; + reg = <0x105C0000 0x3000>; + #clock-cells = <1>; + }; + + pinctrl_1: pinctrl@11000000 { + compatible = "samsung,exynos4415-pinctrl"; + reg = <0x11000000 0x1000>; + interrupts = <0 225 0>; + + wakeup-interrupt-controller { + compatible = "samsung,exynos4210-wakeup-eint"; + interrupt-parent = <&gic>; + interrupts = <0 48 0>; + }; + }; + + pinctrl_0: pinctrl@11400000 { + compatible = "samsung,exynos4415-pinctrl"; + reg = <0x11400000 0x1000>; + interrupts = <0 240 0>; + }; + + hsotg: hsotg@12480000 { + compatible = "samsung,s3c6400-hsotg"; + reg = <0x12480000 0x20000>; + interrupts = <0 141 0>; + clocks = <&cmu CLK_USBDEVICE>; + clock-names = "otg"; + phys = <&exynos_usbphy 0>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + mshc_0: mshc@12510000 { + compatible = "samsung,exynos5250-dw-mshc"; + reg = <0x12510000 0x1000>; + interrupts = <0 142 0>; + clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>; + clock-names = "biu", "ciu"; + fifo-depth = <0x80>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + mshc_1: mshc@12520000 { + compatible = "samsung,exynos5250-dw-mshc"; + reg = <0x12520000 0x1000>; + interrupts = <0 143 0>; + clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>; + clock-names = "biu", "ciu"; + fifo-depth = <0x80>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + mshc_2: mshc@12530000 { + compatible = "samsung,exynos5250-dw-mshc"; + reg = <0x12530000 0x1000>; + interrupts = <0 144 0>; + clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>; + clock-names = "biu", "ciu"; + fifo-depth = <0x80>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + ehci: ehci@12580000 { + compatible = "samsung,exynos4210-ehci"; + reg = <0x12580000 0x100>; + interrupts = <0 140 0>; + clocks = <&cmu CLK_USBHOST>; + clock-names = "usbhost"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + phys = <&exynos_usbphy 1>; + status = "disabled"; + }; + port@1 { + reg = <1>; + phys = <&exynos_usbphy 2>; + status = "disabled"; + }; + port@2 { + reg = <2>; + phys = <&exynos_usbphy 3>; + status = "disabled"; + }; + }; + + ohci: ohci@12590000 { + compatible = "samsung,exynos4210-ohci"; + reg = <0x12590000 0x100>; + interrupts = <0 140 0>; + clocks = <&cmu CLK_USBHOST>; + clock-names = "usbhost"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + phys = <&exynos_usbphy 1>; + status = "disabled"; + }; + }; + + exynos_usbphy: exynos-usbphy@125B0000 { + compatible = "samsung,exynos4x12-usb2-phy"; + reg = <0x125B0000 0x100>; + samsung,pmureg-phandle = <&pmu_system_controller>; + samsung,sysreg-phandle = <&sysreg_system_controller>; + clocks = <&cmu CLK_USBDEVICE>, <&xusbxti>; + clock-names = "phy", "ref"; + #phy-cells = <1>; + status = "disabled"; + }; + + amba { + compatible = "arm,amba-bus"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + ranges; + + pdma0: pdma@12680000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x12680000 0x1000>; + interrupts = <0 138 0>; + clocks = <&cmu CLK_PDMA0>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + }; + + pdma1: pdma@12690000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x12690000 0x1000>; + interrupts = <0 139 0>; + clocks = <&cmu CLK_PDMA1>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + }; + }; + + adc: adc@126C0000 { + compatible = "samsung,exynos3250-adc", + "samsung,exynos-adc-v2"; + reg = <0x126C0000 0x100>, <0x10020718 0x4>; + interrupts = <0 137 0>; + clock-names = "adc", "sclk"; + clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>; + #io-channel-cells = <1>; + io-channel-ranges; + status = "disabled"; + }; + + serial_0: serial@13800000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13800000 0x100>; + interrupts = <0 109 0>; + clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>; + clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; + }; + + serial_1: serial@13810000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13810000 0x100>; + interrupts = <0 110 0>; + clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>; + clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; + }; + + serial_2: serial@13820000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13820000 0x100>; + interrupts = <0 111 0>; + clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>; + clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; + }; + + serial_3: serial@13830000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13830000 0x100>; + interrupts = <0 112 0>; + clocks = <&cmu CLK_UART3>, <&cmu CLK_SCLK_UART3>; + clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; + }; + + i2c_0: i2c@13860000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x13860000 0x100>; + interrupts = <0 113 0>; + clocks = <&cmu CLK_I2C0>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_bus>; + status = "disabled"; + }; + + i2c_1: i2c@13870000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x13870000 0x100>; + interrupts = <0 114 0>; + clocks = <&cmu CLK_I2C1>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_bus>; + status = "disabled"; + }; + + i2c_2: i2c@13880000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x13880000 0x100>; + interrupts = <0 115 0>; + clocks = <&cmu CLK_I2C2>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_bus>; + status = "disabled"; + }; + + i2c_3: i2c@13890000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x13890000 0x100>; + interrupts = <0 116 0>; + clocks = <&cmu CLK_I2C3>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_bus>; + status = "disabled"; + }; + + i2c_4: i2c@138A0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x138A0000 0x100>; + interrupts = <0 117 0>; + clocks = <&cmu CLK_I2C4>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_bus>; + status = "disabled"; + }; + + i2c_5: i2c@138B0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x138B0000 0x100>; + interrupts = <0 118 0>; + clocks = <&cmu CLK_I2C5>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_bus>; + status = "disabled"; + }; + + i2c_6: i2c@138C0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x138C0000 0x100>; + interrupts = <0 119 0>; + clocks = <&cmu CLK_I2C6>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_bus>; + status = "disabled"; + }; + + i2c_7: i2c@138D0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x138D0000 0x100>; + interrupts = <0 120 0>; + clocks = <&cmu CLK_I2C7>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7_bus>; + status = "disabled"; + }; + + spi_0: spi@13920000 { + compatible = "samsung,exynos4210-spi"; + reg = <0x13920000 0x100>; + interrupts = <0 121 0>; + dmas = <&pdma0 7>, <&pdma0 6>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>; + clock-names = "spi", "spi_busclk0"; + samsung,spi-src-clk = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_bus>; + status = "disabled"; + }; + + spi_1: spi@13930000 { + compatible = "samsung,exynos4210-spi"; + reg = <0x13930000 0x100>; + interrupts = <0 122 0>; + dmas = <&pdma1 7>, <&pdma1 6>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>; + clock-names = "spi", "spi_busclk0"; + samsung,spi-src-clk = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_bus>; + status = "disabled"; + }; + + spi_2: spi@13940000 { + compatible = "samsung,exynos4210-spi"; + reg = <0x13940000 0x100>; + interrupts = <0 123 0>; + dmas = <&pdma0 9>, <&pdma0 8>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu CLK_SPI2>, <&cmu CLK_SCLK_SPI2>; + clock-names = "spi", "spi_busclk0"; + samsung,spi-src-clk = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_bus>; + status = "disabled"; + }; + + clock_audss: clock-controller@03810000 { + compatible = "samsung,exynos4210-audss-clock"; + reg = <0x03810000 0x0C>; + #clock-cells = <1>; + }; + + i2s0: i2s@3830000 { + compatible = "samsung,s5pv210-i2s"; + reg = <0x03830000 0x100>; + interrupts = <0 124 0>; + clocks = <&clock_audss EXYNOS_I2S_BUS>, + <&clock_audss EXYNOS_SCLK_I2S>; + clock-names = "iis", "i2s_opclk0"; + dmas = <&pdma1 10>, <&pdma1 9>, <&pdma1 8>; + dma-names = "tx", "rx", "tx-sec"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_bus>; + samsung,idma-addr = <0x03000000>; + status = "disabled"; + }; + + pwm: pwm@139D0000 { + compatible = "samsung,exynos4210-pwm"; + reg = <0x139D0000 0x1000>; + interrupts = <0 104 0>, <0 105 0>, <0 106 0>, + <0 107 0>, <0 108 0>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = <0 18 0>, <0 19 0>, <0 20 0>, <0 21 0>; + }; + }; +}; + +#include "exynos4415-pinctrl.dtsi" -- 1.8.5.5 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCHv3 2/2] ARM: dts: Add dts files for Exynos4415 SoC @ 2014-10-28 4:46 ` Chanwoo Choi 0 siblings, 0 replies; 10+ messages in thread From: Chanwoo Choi @ 2014-10-28 4:46 UTC (permalink / raw) To: linux-arm-kernel This patch adds new exynos4415.dtsi to support Exynos4415 SoC based on Cortex-A9 quad cores and includes following dt nodes: - GIC interrupt controller (GIC-400) - Pinctrl to control three GPIO parts - CMU (Clock Management Unit) for CMU/CMU_DMC/AUDSS - CPU information (Cortex-A9 quad cores) - UART to support serial port - MCT (Multi Core Timer) - ADC (Analog Digital Converter) - RTC (Real Time Clock) - I2C/SPI busses - Power domains (CAM, TV, MFC, G3D, LCD0, ISP0/1) - PMU (Performance Monitoring Unit) - MSHC (Mobile Storage Host Controller) - EHCI (Enhanced Host Controller Interface) - OHIC (Open Host Controller Interface) - USB 2.0 device with hsotg - PWM (Pluse Width Modulation) Timer - AMBA bus for PDMA0/1 - SYSRAM node for memory mapping - SYSREG node for memory mapping - PMU (Power Management Unit) node for memory mapping Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: Ben Dooks <ben-linux@fluff.org> Cc: Russell King <linux@arm.linux.org.uk> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Olof Johansson <olof@lixom.net> Cc: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com> [m.szyprowski: Add OHCI node and correct EHCI node] Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> [yj44.cho: Add mipi-phy node] Signed-off-by: YoungJun Cho <yj44.cho@samsung.com> [jaewon02: Add EHCI and SPI_2 node] Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com> [ideal.song: Add I2S0 node for audio interface] Signed-off-by: Inha Song <ideal.song@samsung.com> [tomasz.figa: Add L2 cache node] Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> Acked-by: Kyungmin Park <Kyungmin Park@samsung.com> --- arch/arm/boot/dts/exynos4415-pinctrl.dtsi | 613 +++++++++++++++++++++++++++++ arch/arm/boot/dts/exynos4415.dtsi | 627 ++++++++++++++++++++++++++++++ 2 files changed, 1240 insertions(+) create mode 100644 arch/arm/boot/dts/exynos4415-pinctrl.dtsi create mode 100644 arch/arm/boot/dts/exynos4415.dtsi diff --git a/arch/arm/boot/dts/exynos4415-pinctrl.dtsi b/arch/arm/boot/dts/exynos4415-pinctrl.dtsi new file mode 100644 index 0000000..5ce4314 --- /dev/null +++ b/arch/arm/boot/dts/exynos4415-pinctrl.dtsi @@ -0,0 +1,613 @@ +/* + * Samsung's Exynos4415 SoCs pin-mux and pin-config device tree source + * + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * + * Samsung's Exynos4415 SoCs pin-mux and pin-config optiosn are listed as device + * tree nodes are listed in this file. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +&pinctrl_0 { + gpa0: gpa0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa1: gpa1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb: gpb { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc0: gpc0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc1: gpc1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd0: gpd0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd1: gpd1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf0: gpf0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf1: gpf1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf2: gpf2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + uart0_data: uart0-data { + samsung,pins = "gpa0-0", "gpa0-1"; + samsung,pin-function = <0x2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart0_fctl: uart0-fctl { + samsung,pins = "gpa0-2", "gpa0-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart1_data: uart1-data { + samsung,pins = "gpa0-4", "gpa0-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart1_fctl: uart1-fctl { + samsung,pins = "gpa0-6", "gpa0-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart2_data: uart2-data { + samsung,pins = "gpa1-0", "gpa1-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart2_fctl: uart2-fctl { + samsung,pins = "gpa1-2", "gpa1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart3_data: uart3-data { + samsung,pins = "gpa1-4", "gpa1-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + i2c2_bus: i2c2-bus { + samsung,pins = "gpa0-6", "gpa0-7"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c3_bus: i2c3-bus { + samsung,pins = "gpa1-2", "gpa1-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + spi0_bus: spi0-bus { + samsung,pins = "gpb-0", "gpb-2", "gpb-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c4_bus: i2c4-bus { + samsung,pins = "gpb-0", "gpb-1"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + spi1_bus: spi1-bus { + samsung,pins = "gpb-4", "gpb-6", "gpb-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c5_bus: i2c5-bus { + samsung,pins = "gpb-2", "gpb-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2s1_bus: i2s1-bus { + samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", + "gpc0-4"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + i2s2_bus: i2s2-bus { + samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", + "gpc1-4"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + pcm2_bus: pcm2-bus { + samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", + "gpc1-4"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + i2c6_bus: i2c6-bus { + samsung,pins = "gpc1-3", "gpc1-4"; + samsung,pin-function = <4>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + spi2_bus: spi2-bus { + samsung,pins = "gpc1-1", "gpc1-3", "gpc1-4"; + samsung,pin-function = <5>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + pwm0_out: pwm0-out { + samsung,pins = "gpd0-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + pwm1_out: pwm1-out { + samsung,pins = "gpd0-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + pwm2_out: pwm2-out { + samsung,pins = "gpd0-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + pwm3_out: pwm3-out { + samsung,pins = "gpd0-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + i2c7_bus: i2c7-bus { + samsung,pins = "gpd0-2", "gpd0-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c0_bus: i2c0-bus { + samsung,pins = "gpd1-0", "gpd1-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c1_bus: i2c1-bus { + samsung,pins = "gpd1-2", "gpd1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; +}; + +&pinctrl_1 { + gpk0: gpk0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpk1: gpk1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpk2: gpk2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpk3: gpk3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpl0: gpl0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + mp00: mp00 { + gpio-controller; + #gpio-cells = <2>; + }; + + mp01: mp01 { + gpio-controller; + #gpio-cells = <2>; + }; + + mp02: mp02 { + gpio-controller; + #gpio-cells = <2>; + }; + + mp03: mp03 { + gpio-controller; + #gpio-cells = <2>; + }; + + mp04: mp04 { + gpio-controller; + #gpio-cells = <2>; + }; + + mp05: mp05 { + gpio-controller; + #gpio-cells = <2>; + }; + + mp06: mp06 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpm0: gpm0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpm1: gpm1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpm2: gpm2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpm3: gpm3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpm4: gpm4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx0: gpx0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&gic>; + interrupts = <0 32 0>, <0 33 0>, <0 34 0>, <0 35 0>, + <0 36 0>, <0 37 0>, <0 38 0>, <0 39 0>; + #interrupt-cells = <2>; + }; + + gpx1: gpx1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&gic>; + interrupts = <0 40 0>, <0 41 0>, <0 42 0>, <0 43 0>, + <0 44 0>, <0 45 0>, <0 46 0>, <0 47 0>; + #interrupt-cells = <2>; + }; + + gpx2: gpx2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx3: gpx3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + sd0_clk: sd0-clk { + samsung,pins = "gpk0-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd0_cmd: sd0-cmd { + samsung,pins = "gpk0-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd0_cd: sd0-cd { + samsung,pins = "gpk0-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd0_rdqs: sd0-rdqs { + samsung,pins = "gpk0-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd0_bus1: sd0-bus-width1 { + samsung,pins = "gpk0-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd0_bus4: sd0-bus-width4 { + samsung,pins = "gpk0-4", "gpk0-5", "gpk0-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd0_bus8: sd0-bus-width8 { + samsung,pins = "gpl0-0", "gpl0-1", "gpl0-2", "gpl0-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd1_clk: sd1-clk { + samsung,pins = "gpk1-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd1_cmd: sd1-cmd { + samsung,pins = "gpk1-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd1_cd: sd1-cd { + samsung,pins = "gpk1-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd1_bus1: sd1-bus-width1 { + samsung,pins = "gpk1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd1_bus4: sd1-bus-width4 { + samsung,pins = "gpk1-4", "gpk1-5", "gpk1-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd2_clk: sd2-clk { + samsung,pins = "gpk2-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <4>; + }; + + sd2_cmd: sd2-cmd { + samsung,pins = "gpk2-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <4>; + }; + + sd2_cd: sd2-cd { + samsung,pins = "gpk2-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd2_bus1: sd2-bus-width1 { + samsung,pins = "gpk2-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <4>; + }; + + sd2_bus4: sd2-bus-width4 { + samsung,pins = "gpk2-4", "gpk2-5", "gpk2-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <4>; + }; + + cam_port_b_io: cam-port-b-io { + samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3", + "gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7", + "gpm1-0", "gpm1-1", "gpm2-0", "gpm2-1"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + cam_port_b_clk_active: cam-port-b-clk-active { + samsung,pins = "gpm2-2"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + cam_port_b_clk_idle: cam-port-b-clk-idle { + samsung,pins = "gpm2-2"; + samsung,pin-function = <0>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + fimc_is_i2c0: fimc-is-i2c0 { + samsung,pins = "gpm4-0", "gpm4-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + fimc_is_i2c1: fimc-is-i2c1 { + samsung,pins = "gpm4-2", "gpm4-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + fimc_is_uart: fimc-is-uart { + samsung,pins = "gpm3-5", "gpm3-7"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; +}; + +&pinctrl_2 { + gpz: gpz { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + i2s0_bus: i2s0-bus { + samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", + "gpz-4", "gpz-5", "gpz-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + etc: etc { + gpio-controller; + #gpio-cells = <2>; + }; +}; diff --git a/arch/arm/boot/dts/exynos4415.dtsi b/arch/arm/boot/dts/exynos4415.dtsi new file mode 100644 index 0000000..078b1b8 --- /dev/null +++ b/arch/arm/boot/dts/exynos4415.dtsi @@ -0,0 +1,627 @@ +/* + * Samsung's Exynos4415 SoC device tree source + * + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * + * Samsung's Exynos4415 SoC device nodes are listed in this file. Exynos4415 + * based board files can include this file and provide values for board specfic + * bindings. + * + * Note: This file does not include device nodes for all the controllers in + * Exynos4415 SoC. As device tree coverage for Exynos4415 increases, additional + * nodes can be added to this file. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "skeleton.dtsi" +#include <dt-bindings/clock/exynos4415.h> +#include <dt-bindings/clock/exynos-audss-clk.h> + +/ { + compatible = "samsung,exynos4415"; + interrupt-parent = <&gic>; + + aliases { + pinctrl0 = &pinctrl_0; + pinctrl1 = &pinctrl_1; + pinctrl2 = &pinctrl_2; + mshc0 = &mshc_0; + mshc1 = &mshc_1; + mshc2 = &mshc_2; + spi0 = &spi_0; + spi1 = &spi_1; + spi2 = &spi_2; + i2c0 = &i2c_0; + i2c1 = &i2c_1; + i2c2 = &i2c_2; + i2c3 = &i2c_3; + i2c4 = &i2c_4; + i2c5 = &i2c_5; + i2c6 = &i2c_6; + i2c7 = &i2c_7; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu at 0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0xa00>; + clock-frequency = <1600000000>; + }; + + cpu1: cpu at 1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0xa01>; + clock-frequency = <1600000000>; + }; + + cpu2: cpu at 2 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0xa02>; + clock-frequency = <1600000000>; + }; + + cpu3: cpu at 3 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0xa03>; + clock-frequency = <1600000000>; + }; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + fixed-rate-clocks { + #address-cells = <1>; + #size-cells = <0>; + + xusbxti: clock at 0 { + compatible = "fixed-clock"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + clock-frequency = <0>; + #clock-cells = <0>; + clock-output-names = "xusbxti"; + }; + + xxti: clock at 1 { + compatible = "fixed-clock"; + reg = <1>; + clock-frequency = <0>; + #clock-cells = <0>; + clock-output-names = "xxti"; + }; + }; + + sysram at 02020000 { + compatible = "mmio-sram"; + reg = <0x02020000 0x50000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x02020000 0x50000>; + + smp-sysram at 0 { + compatible = "samsung,exynos4210-sysram"; + reg = <0x0 0x1000>; + }; + + smp-sysram at 4f000 { + compatible = "samsung,exynos4210-sysram-ns"; + reg = <0x4f000 0x1000>; + }; + }; + + pinctrl_2: pinctrl at 03860000 { + compatible = "samsung,exynos4415-pinctrl"; + reg = <0x03860000 0x1000>; + interrupts = <0 242 0>; + }; + + chipid at 10000000 { + compatible = "samsung,exynos4210-chipid"; + reg = <0x10000000 0x100>; + }; + + sysreg_system_controller: syscon at 10010000 { + compatible = "samsung,exynos4-sysreg", "syscon"; + reg = <0x10010000 0x400>; + }; + + pmu_system_controller: system-controller at 10020000 { + compatible = "samsung,exynos4415-pmu", "syscon"; + reg = <0x10020000 0x4000>; + }; + + mipi_phy: video-phy at 10020710 { + compatible = "samsung,s5pv210-mipi-video-phy"; + reg = <0x10020710 8>; + #phy-cells = <1>; + }; + + pd_cam: cam-power-domain at 10024000 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10024000 0x20>; + }; + + pd_tv: tv-power-domain at 10024020 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10024020 0x20>; + }; + + pd_mfc: mfc-power-domain at 10024040 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10024040 0x20>; + }; + + pd_g3d: g3d-power-domain at 10024060 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10024060 0x20>; + }; + + pd_lcd0: lcd0-power-domain at 10024080 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10024080 0x20>; + }; + + pd_isp0: isp0-power-domain at 100240A0 { + compatible = "samsung,exynos4210-pd"; + reg = <0x100240A0 0x20>; + }; + + pd_isp1: isp1-power-domain at 100240E0 { + compatible = "samsung,exynos4210-pd"; + reg = <0x100240E0 0x20>; + }; + + cmu: clock-controller at 10030000 { + compatible = "samsung,exynos4415-cmu"; + reg = <0x10030000 0x18000>; + #clock-cells = <1>; + }; + + rtc: rtc at 10070000 { + compatible = "samsung,exynos3250-rtc"; + reg = <0x10070000 0x100>; + interrupts = <0 73 0>, <0 74 0>; + status = "disabled"; + }; + + mct at 10050000 { + compatible = "samsung,exynos4210-mct"; + reg = <0x10050000 0x800>; + interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>, + <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>; + clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>; + clock-names = "fin_pll", "mct"; + }; + + gic: interrupt-controller at 10481000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x10481000 0x1000>, + <0x10482000 0x1000>, + <0x10484000 0x2000>, + <0x10486000 0x2000>; + interrupts = <1 9 0xf04>; + }; + + l2c: l2-cache-controller at 10502000 { + compatible = "arm,pl310-cache"; + reg = <0x10502000 0x1000>; + cache-unified; + cache-level = <2>; + arm,tag-latency = <2 2 1>; + arm,data-latency = <3 2 1>; + arm,double-linefill = <1>; + arm,double-linefill-incr = <0>; + arm,double-linefill-wrap = <1>; + arm,prefetch-drop = <1>; + arm,prefetch-offset = <7>; + }; + + cmu_dmc: clock-controller at 105C0000 { + compatible = "samsung,exynos4415-cmu-dmc"; + reg = <0x105C0000 0x3000>; + #clock-cells = <1>; + }; + + pinctrl_1: pinctrl at 11000000 { + compatible = "samsung,exynos4415-pinctrl"; + reg = <0x11000000 0x1000>; + interrupts = <0 225 0>; + + wakeup-interrupt-controller { + compatible = "samsung,exynos4210-wakeup-eint"; + interrupt-parent = <&gic>; + interrupts = <0 48 0>; + }; + }; + + pinctrl_0: pinctrl at 11400000 { + compatible = "samsung,exynos4415-pinctrl"; + reg = <0x11400000 0x1000>; + interrupts = <0 240 0>; + }; + + hsotg: hsotg at 12480000 { + compatible = "samsung,s3c6400-hsotg"; + reg = <0x12480000 0x20000>; + interrupts = <0 141 0>; + clocks = <&cmu CLK_USBDEVICE>; + clock-names = "otg"; + phys = <&exynos_usbphy 0>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + mshc_0: mshc at 12510000 { + compatible = "samsung,exynos5250-dw-mshc"; + reg = <0x12510000 0x1000>; + interrupts = <0 142 0>; + clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>; + clock-names = "biu", "ciu"; + fifo-depth = <0x80>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + mshc_1: mshc at 12520000 { + compatible = "samsung,exynos5250-dw-mshc"; + reg = <0x12520000 0x1000>; + interrupts = <0 143 0>; + clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>; + clock-names = "biu", "ciu"; + fifo-depth = <0x80>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + mshc_2: mshc at 12530000 { + compatible = "samsung,exynos5250-dw-mshc"; + reg = <0x12530000 0x1000>; + interrupts = <0 144 0>; + clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>; + clock-names = "biu", "ciu"; + fifo-depth = <0x80>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + ehci: ehci at 12580000 { + compatible = "samsung,exynos4210-ehci"; + reg = <0x12580000 0x100>; + interrupts = <0 140 0>; + clocks = <&cmu CLK_USBHOST>; + clock-names = "usbhost"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + port at 0 { + reg = <0>; + phys = <&exynos_usbphy 1>; + status = "disabled"; + }; + port at 1 { + reg = <1>; + phys = <&exynos_usbphy 2>; + status = "disabled"; + }; + port at 2 { + reg = <2>; + phys = <&exynos_usbphy 3>; + status = "disabled"; + }; + }; + + ohci: ohci at 12590000 { + compatible = "samsung,exynos4210-ohci"; + reg = <0x12590000 0x100>; + interrupts = <0 140 0>; + clocks = <&cmu CLK_USBHOST>; + clock-names = "usbhost"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + port at 0 { + reg = <0>; + phys = <&exynos_usbphy 1>; + status = "disabled"; + }; + }; + + exynos_usbphy: exynos-usbphy at 125B0000 { + compatible = "samsung,exynos4x12-usb2-phy"; + reg = <0x125B0000 0x100>; + samsung,pmureg-phandle = <&pmu_system_controller>; + samsung,sysreg-phandle = <&sysreg_system_controller>; + clocks = <&cmu CLK_USBDEVICE>, <&xusbxti>; + clock-names = "phy", "ref"; + #phy-cells = <1>; + status = "disabled"; + }; + + amba { + compatible = "arm,amba-bus"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + ranges; + + pdma0: pdma at 12680000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x12680000 0x1000>; + interrupts = <0 138 0>; + clocks = <&cmu CLK_PDMA0>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + }; + + pdma1: pdma at 12690000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x12690000 0x1000>; + interrupts = <0 139 0>; + clocks = <&cmu CLK_PDMA1>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + }; + }; + + adc: adc at 126C0000 { + compatible = "samsung,exynos3250-adc", + "samsung,exynos-adc-v2"; + reg = <0x126C0000 0x100>, <0x10020718 0x4>; + interrupts = <0 137 0>; + clock-names = "adc", "sclk"; + clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>; + #io-channel-cells = <1>; + io-channel-ranges; + status = "disabled"; + }; + + serial_0: serial at 13800000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13800000 0x100>; + interrupts = <0 109 0>; + clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>; + clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; + }; + + serial_1: serial at 13810000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13810000 0x100>; + interrupts = <0 110 0>; + clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>; + clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; + }; + + serial_2: serial at 13820000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13820000 0x100>; + interrupts = <0 111 0>; + clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>; + clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; + }; + + serial_3: serial at 13830000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13830000 0x100>; + interrupts = <0 112 0>; + clocks = <&cmu CLK_UART3>, <&cmu CLK_SCLK_UART3>; + clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; + }; + + i2c_0: i2c at 13860000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x13860000 0x100>; + interrupts = <0 113 0>; + clocks = <&cmu CLK_I2C0>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_bus>; + status = "disabled"; + }; + + i2c_1: i2c at 13870000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x13870000 0x100>; + interrupts = <0 114 0>; + clocks = <&cmu CLK_I2C1>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_bus>; + status = "disabled"; + }; + + i2c_2: i2c at 13880000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x13880000 0x100>; + interrupts = <0 115 0>; + clocks = <&cmu CLK_I2C2>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_bus>; + status = "disabled"; + }; + + i2c_3: i2c at 13890000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x13890000 0x100>; + interrupts = <0 116 0>; + clocks = <&cmu CLK_I2C3>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_bus>; + status = "disabled"; + }; + + i2c_4: i2c at 138A0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x138A0000 0x100>; + interrupts = <0 117 0>; + clocks = <&cmu CLK_I2C4>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_bus>; + status = "disabled"; + }; + + i2c_5: i2c at 138B0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x138B0000 0x100>; + interrupts = <0 118 0>; + clocks = <&cmu CLK_I2C5>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_bus>; + status = "disabled"; + }; + + i2c_6: i2c at 138C0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x138C0000 0x100>; + interrupts = <0 119 0>; + clocks = <&cmu CLK_I2C6>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_bus>; + status = "disabled"; + }; + + i2c_7: i2c at 138D0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x138D0000 0x100>; + interrupts = <0 120 0>; + clocks = <&cmu CLK_I2C7>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7_bus>; + status = "disabled"; + }; + + spi_0: spi at 13920000 { + compatible = "samsung,exynos4210-spi"; + reg = <0x13920000 0x100>; + interrupts = <0 121 0>; + dmas = <&pdma0 7>, <&pdma0 6>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>; + clock-names = "spi", "spi_busclk0"; + samsung,spi-src-clk = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_bus>; + status = "disabled"; + }; + + spi_1: spi at 13930000 { + compatible = "samsung,exynos4210-spi"; + reg = <0x13930000 0x100>; + interrupts = <0 122 0>; + dmas = <&pdma1 7>, <&pdma1 6>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>; + clock-names = "spi", "spi_busclk0"; + samsung,spi-src-clk = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_bus>; + status = "disabled"; + }; + + spi_2: spi at 13940000 { + compatible = "samsung,exynos4210-spi"; + reg = <0x13940000 0x100>; + interrupts = <0 123 0>; + dmas = <&pdma0 9>, <&pdma0 8>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu CLK_SPI2>, <&cmu CLK_SCLK_SPI2>; + clock-names = "spi", "spi_busclk0"; + samsung,spi-src-clk = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_bus>; + status = "disabled"; + }; + + clock_audss: clock-controller at 03810000 { + compatible = "samsung,exynos4210-audss-clock"; + reg = <0x03810000 0x0C>; + #clock-cells = <1>; + }; + + i2s0: i2s at 3830000 { + compatible = "samsung,s5pv210-i2s"; + reg = <0x03830000 0x100>; + interrupts = <0 124 0>; + clocks = <&clock_audss EXYNOS_I2S_BUS>, + <&clock_audss EXYNOS_SCLK_I2S>; + clock-names = "iis", "i2s_opclk0"; + dmas = <&pdma1 10>, <&pdma1 9>, <&pdma1 8>; + dma-names = "tx", "rx", "tx-sec"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_bus>; + samsung,idma-addr = <0x03000000>; + status = "disabled"; + }; + + pwm: pwm at 139D0000 { + compatible = "samsung,exynos4210-pwm"; + reg = <0x139D0000 0x1000>; + interrupts = <0 104 0>, <0 105 0>, <0 106 0>, + <0 107 0>, <0 108 0>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = <0 18 0>, <0 19 0>, <0 20 0>, <0 21 0>; + }; + }; +}; + +#include "exynos4415-pinctrl.dtsi" -- 1.8.5.5 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* RE: [PATCHv3 2/2] ARM: dts: Add dts files for Exynos4415 SoC 2014-10-28 4:46 ` Chanwoo Choi @ 2014-10-28 10:50 ` Kukjin Kim -1 siblings, 0 replies; 10+ messages in thread From: Kukjin Kim @ 2014-10-28 10:50 UTC (permalink / raw) To: 'Chanwoo Choi' Cc: mark.rutland, arnd, olof, tomasz.figa, inki.dae, sw0312.kim, kyungmin.park, m.szyprowski, yj44.cho, jaewon02.kim, ideal.song, linux-samsung-soc, linux-kernel, linux-arm-kernel, 'Ben Dooks', 'Russell King' Chanwoo Choi wrote: > Hi, > This patch adds new exynos4415.dtsi to support Exynos4415 SoC > based on Cortex-A9 quad cores and includes following dt nodes: > > - GIC interrupt controller (GIC-400) > - Pinctrl to control three GPIO parts > - CMU (Clock Management Unit) for CMU/CMU_DMC/AUDSS > - CPU information (Cortex-A9 quad cores) > - UART to support serial port > - MCT (Multi Core Timer) > - ADC (Analog Digital Converter) > - RTC (Real Time Clock) > - I2C/SPI busses > - Power domains (CAM, TV, MFC, G3D, LCD0, ISP0/1) > - PMU (Performance Monitoring Unit) > - MSHC (Mobile Storage Host Controller) > - EHCI (Enhanced Host Controller Interface) > - OHIC (Open Host Controller Interface) > - USB 2.0 device with hsotg > - PWM (Pluse Width Modulation) Timer > - AMBA bus for PDMA0/1 > - SYSRAM node for memory mapping > - SYSREG node for memory mapping > - PMU (Power Management Unit) node for memory mapping > > Cc: Kukjin Kim <kgene.kim@samsung.com> > Cc: Ben Dooks <ben-linux@fluff.org> > Cc: Russell King <linux@arm.linux.org.uk> > Cc: Mark Rutland <mark.rutland@arm.com> > Cc: Olof Johansson <olof@lixom.net> > Cc: Arnd Bergmann <arnd@arndb.de> > Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> > Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com> > [m.szyprowski: Add OHCI node and correct EHCI node] > Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> > [yj44.cho: Add mipi-phy node] > Signed-off-by: YoungJun Cho <yj44.cho@samsung.com> > [jaewon02: Add EHCI and SPI_2 node] > Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com> > [ideal.song: Add I2S0 node for audio interface] > Signed-off-by: Inha Song <ideal.song@samsung.com> > [tomasz.figa: Add L2 cache node] > Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> > Acked-by: Kyungmin Park <Kyungmin Park@samsung.com> > --- > arch/arm/boot/dts/exynos4415-pinctrl.dtsi | 613 +++++++++++++++++++++++++++++ > arch/arm/boot/dts/exynos4415.dtsi | 627 ++++++++++++++++++++++++++++++ > 2 files changed, 1240 insertions(+) > create mode 100644 arch/arm/boot/dts/exynos4415-pinctrl.dtsi > create mode 100644 arch/arm/boot/dts/exynos4415.dtsi [...] > + > + mp00: mp00 { > + gpio-controller; > + #gpio-cells = <2>; > + }; After talking about above gpio ports in intranet, I thought again. And I'm still thinking just to remove them would be better because it will not be used. Let's remove useless mp related gpio ports (nodes) here. > + > + mp01: mp01 { > + gpio-controller; > + #gpio-cells = <2>; > + }; > + > + mp02: mp02 { > + gpio-controller; > + #gpio-cells = <2>; > + }; > + > + mp03: mp03 { > + gpio-controller; > + #gpio-cells = <2>; > + }; > + > + mp04: mp04 { > + gpio-controller; > + #gpio-cells = <2>; > + }; > + > + mp05: mp05 { > + gpio-controller; > + #gpio-cells = <2>; > + }; > + > + mp06: mp06 { > + gpio-controller; > + #gpio-cells = <2>; > + }; Same as above. [...] > + etc: etc { > + gpio-controller; > + #gpio-cells = <2>; > + }; Same, above 'etc' port will not be used I think. > +}; > diff --git a/arch/arm/boot/dts/exynos4415.dtsi b/arch/arm/boot/dts/exynos4415.dtsi > new file mode 100644 > index 0000000..078b1b8 > --- /dev/null > +++ b/arch/arm/boot/dts/exynos4415.dtsi > @@ -0,0 +1,627 @@ > +/* > + * Samsung's Exynos4415 SoC device tree source > + * > + * Copyright (c) 2014 Samsung Electronics Co., Ltd. > + * > + * Samsung's Exynos4415 SoC device nodes are listed in this file. Exynos4415 > + * based board files can include this file and provide values for board specfic > + * bindings. > + * > + * Note: This file does not include device nodes for all the controllers in > + * Exynos4415 SoC. As device tree coverage for Exynos4415 increases, additional > + * nodes can be added to this file. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + */ > + > +#include "skeleton.dtsi" > +#include <dt-bindings/clock/exynos4415.h> > +#include <dt-bindings/clock/exynos-audss-clk.h> > + > +/ { > + compatible = "samsung,exynos4415"; > + interrupt-parent = <&gic>; > + > + aliases { > + pinctrl0 = &pinctrl_0; > + pinctrl1 = &pinctrl_1; > + pinctrl2 = &pinctrl_2; > + mshc0 = &mshc_0; > + mshc1 = &mshc_1; > + mshc2 = &mshc_2; > + spi0 = &spi_0; > + spi1 = &spi_1; > + spi2 = &spi_2; > + i2c0 = &i2c_0; > + i2c1 = &i2c_1; > + i2c2 = &i2c_2; > + i2c3 = &i2c_3; > + i2c4 = &i2c_4; > + i2c5 = &i2c_5; > + i2c6 = &i2c_6; > + i2c7 = &i2c_7; > + }; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a9"; > + reg = <0xa00>; This should be same with above value of 'cpu@0', 0. You need to use one of following: cpu0: cpu@a00 { Or reg = <0x0>; > + clock-frequency = <1600000000>; > + }; > + > + cpu1: cpu@1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a9"; > + reg = <0xa01>; Same as above. > + clock-frequency = <1600000000>; > + }; > + > + cpu2: cpu@2 { > + device_type = "cpu"; > + compatible = "arm,cortex-a9"; > + reg = <0xa02>; Same. > + clock-frequency = <1600000000>; > + }; > + > + cpu3: cpu@3 { > + device_type = "cpu"; > + compatible = "arm,cortex-a9"; > + reg = <0xa03>; Same. > + clock-frequency = <1600000000>; > + }; > + }; > + > + soc: soc { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + fixed-rate-clocks { Maybe 'fixed-rate-clocks' depends on board not SoC so need to move to board dt file? > + #address-cells = <1>; > + #size-cells = <0>; > + > + xusbxti: clock@0 { > + compatible = "fixed-clock"; > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0>; > + clock-frequency = <0>; > + #clock-cells = <0>; > + clock-output-names = "xusbxti"; > + }; > + > + xxti: clock@1 { > + compatible = "fixed-clock"; > + reg = <1>; > + clock-frequency = <0>; > + #clock-cells = <0>; > + clock-output-names = "xxti"; > + }; > + }; [...] ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCHv3 2/2] ARM: dts: Add dts files for Exynos4415 SoC @ 2014-10-28 10:50 ` Kukjin Kim 0 siblings, 0 replies; 10+ messages in thread From: Kukjin Kim @ 2014-10-28 10:50 UTC (permalink / raw) To: linux-arm-kernel Chanwoo Choi wrote: > Hi, > This patch adds new exynos4415.dtsi to support Exynos4415 SoC > based on Cortex-A9 quad cores and includes following dt nodes: > > - GIC interrupt controller (GIC-400) > - Pinctrl to control three GPIO parts > - CMU (Clock Management Unit) for CMU/CMU_DMC/AUDSS > - CPU information (Cortex-A9 quad cores) > - UART to support serial port > - MCT (Multi Core Timer) > - ADC (Analog Digital Converter) > - RTC (Real Time Clock) > - I2C/SPI busses > - Power domains (CAM, TV, MFC, G3D, LCD0, ISP0/1) > - PMU (Performance Monitoring Unit) > - MSHC (Mobile Storage Host Controller) > - EHCI (Enhanced Host Controller Interface) > - OHIC (Open Host Controller Interface) > - USB 2.0 device with hsotg > - PWM (Pluse Width Modulation) Timer > - AMBA bus for PDMA0/1 > - SYSRAM node for memory mapping > - SYSREG node for memory mapping > - PMU (Power Management Unit) node for memory mapping > > Cc: Kukjin Kim <kgene.kim@samsung.com> > Cc: Ben Dooks <ben-linux@fluff.org> > Cc: Russell King <linux@arm.linux.org.uk> > Cc: Mark Rutland <mark.rutland@arm.com> > Cc: Olof Johansson <olof@lixom.net> > Cc: Arnd Bergmann <arnd@arndb.de> > Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> > Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com> > [m.szyprowski: Add OHCI node and correct EHCI node] > Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> > [yj44.cho: Add mipi-phy node] > Signed-off-by: YoungJun Cho <yj44.cho@samsung.com> > [jaewon02: Add EHCI and SPI_2 node] > Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com> > [ideal.song: Add I2S0 node for audio interface] > Signed-off-by: Inha Song <ideal.song@samsung.com> > [tomasz.figa: Add L2 cache node] > Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> > Acked-by: Kyungmin Park <Kyungmin Park@samsung.com> > --- > arch/arm/boot/dts/exynos4415-pinctrl.dtsi | 613 +++++++++++++++++++++++++++++ > arch/arm/boot/dts/exynos4415.dtsi | 627 ++++++++++++++++++++++++++++++ > 2 files changed, 1240 insertions(+) > create mode 100644 arch/arm/boot/dts/exynos4415-pinctrl.dtsi > create mode 100644 arch/arm/boot/dts/exynos4415.dtsi [...] > + > + mp00: mp00 { > + gpio-controller; > + #gpio-cells = <2>; > + }; After talking about above gpio ports in intranet, I thought again. And I'm still thinking just to remove them would be better because it will not be used. Let's remove useless mp related gpio ports (nodes) here. > + > + mp01: mp01 { > + gpio-controller; > + #gpio-cells = <2>; > + }; > + > + mp02: mp02 { > + gpio-controller; > + #gpio-cells = <2>; > + }; > + > + mp03: mp03 { > + gpio-controller; > + #gpio-cells = <2>; > + }; > + > + mp04: mp04 { > + gpio-controller; > + #gpio-cells = <2>; > + }; > + > + mp05: mp05 { > + gpio-controller; > + #gpio-cells = <2>; > + }; > + > + mp06: mp06 { > + gpio-controller; > + #gpio-cells = <2>; > + }; Same as above. [...] > + etc: etc { > + gpio-controller; > + #gpio-cells = <2>; > + }; Same, above 'etc' port will not be used I think. > +}; > diff --git a/arch/arm/boot/dts/exynos4415.dtsi b/arch/arm/boot/dts/exynos4415.dtsi > new file mode 100644 > index 0000000..078b1b8 > --- /dev/null > +++ b/arch/arm/boot/dts/exynos4415.dtsi > @@ -0,0 +1,627 @@ > +/* > + * Samsung's Exynos4415 SoC device tree source > + * > + * Copyright (c) 2014 Samsung Electronics Co., Ltd. > + * > + * Samsung's Exynos4415 SoC device nodes are listed in this file. Exynos4415 > + * based board files can include this file and provide values for board specfic > + * bindings. > + * > + * Note: This file does not include device nodes for all the controllers in > + * Exynos4415 SoC. As device tree coverage for Exynos4415 increases, additional > + * nodes can be added to this file. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + */ > + > +#include "skeleton.dtsi" > +#include <dt-bindings/clock/exynos4415.h> > +#include <dt-bindings/clock/exynos-audss-clk.h> > + > +/ { > + compatible = "samsung,exynos4415"; > + interrupt-parent = <&gic>; > + > + aliases { > + pinctrl0 = &pinctrl_0; > + pinctrl1 = &pinctrl_1; > + pinctrl2 = &pinctrl_2; > + mshc0 = &mshc_0; > + mshc1 = &mshc_1; > + mshc2 = &mshc_2; > + spi0 = &spi_0; > + spi1 = &spi_1; > + spi2 = &spi_2; > + i2c0 = &i2c_0; > + i2c1 = &i2c_1; > + i2c2 = &i2c_2; > + i2c3 = &i2c_3; > + i2c4 = &i2c_4; > + i2c5 = &i2c_5; > + i2c6 = &i2c_6; > + i2c7 = &i2c_7; > + }; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu0: cpu at 0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a9"; > + reg = <0xa00>; This should be same with above value of 'cpu at 0', 0. You need to use one of following: cpu0: cpu at a00 { Or reg = <0x0>; > + clock-frequency = <1600000000>; > + }; > + > + cpu1: cpu at 1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a9"; > + reg = <0xa01>; Same as above. > + clock-frequency = <1600000000>; > + }; > + > + cpu2: cpu at 2 { > + device_type = "cpu"; > + compatible = "arm,cortex-a9"; > + reg = <0xa02>; Same. > + clock-frequency = <1600000000>; > + }; > + > + cpu3: cpu at 3 { > + device_type = "cpu"; > + compatible = "arm,cortex-a9"; > + reg = <0xa03>; Same. > + clock-frequency = <1600000000>; > + }; > + }; > + > + soc: soc { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + fixed-rate-clocks { Maybe 'fixed-rate-clocks' depends on board not SoC so need to move to board dt file? > + #address-cells = <1>; > + #size-cells = <0>; > + > + xusbxti: clock at 0 { > + compatible = "fixed-clock"; > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0>; > + clock-frequency = <0>; > + #clock-cells = <0>; > + clock-output-names = "xusbxti"; > + }; > + > + xxti: clock at 1 { > + compatible = "fixed-clock"; > + reg = <1>; > + clock-frequency = <0>; > + #clock-cells = <0>; > + clock-output-names = "xxti"; > + }; > + }; [...] ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCHv3 2/2] ARM: dts: Add dts files for Exynos4415 SoC 2014-10-28 10:50 ` Kukjin Kim @ 2014-10-28 10:54 ` Chanwoo Choi -1 siblings, 0 replies; 10+ messages in thread From: Chanwoo Choi @ 2014-10-28 10:54 UTC (permalink / raw) To: Kukjin Kim Cc: mark.rutland, arnd, olof, tomasz.figa, inki.dae, sw0312.kim, kyungmin.park, m.szyprowski, yj44.cho, jaewon02.kim, ideal.song, linux-samsung-soc, linux-kernel, linux-arm-kernel, 'Ben Dooks', 'Russell King' Dear Kukjin, On 10/28/2014 07:50 PM, Kukjin Kim wrote: > Chanwoo Choi wrote: >> > Hi, > >> This patch adds new exynos4415.dtsi to support Exynos4415 SoC >> based on Cortex-A9 quad cores and includes following dt nodes: >> >> - GIC interrupt controller (GIC-400) >> - Pinctrl to control three GPIO parts >> - CMU (Clock Management Unit) for CMU/CMU_DMC/AUDSS >> - CPU information (Cortex-A9 quad cores) >> - UART to support serial port >> - MCT (Multi Core Timer) >> - ADC (Analog Digital Converter) >> - RTC (Real Time Clock) >> - I2C/SPI busses >> - Power domains (CAM, TV, MFC, G3D, LCD0, ISP0/1) >> - PMU (Performance Monitoring Unit) >> - MSHC (Mobile Storage Host Controller) >> - EHCI (Enhanced Host Controller Interface) >> - OHIC (Open Host Controller Interface) >> - USB 2.0 device with hsotg >> - PWM (Pluse Width Modulation) Timer >> - AMBA bus for PDMA0/1 >> - SYSRAM node for memory mapping >> - SYSREG node for memory mapping >> - PMU (Power Management Unit) node for memory mapping >> >> Cc: Kukjin Kim <kgene.kim@samsung.com> >> Cc: Ben Dooks <ben-linux@fluff.org> >> Cc: Russell King <linux@arm.linux.org.uk> >> Cc: Mark Rutland <mark.rutland@arm.com> >> Cc: Olof Johansson <olof@lixom.net> >> Cc: Arnd Bergmann <arnd@arndb.de> >> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> >> Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com> >> [m.szyprowski: Add OHCI node and correct EHCI node] >> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> >> [yj44.cho: Add mipi-phy node] >> Signed-off-by: YoungJun Cho <yj44.cho@samsung.com> >> [jaewon02: Add EHCI and SPI_2 node] >> Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com> >> [ideal.song: Add I2S0 node for audio interface] >> Signed-off-by: Inha Song <ideal.song@samsung.com> >> [tomasz.figa: Add L2 cache node] >> Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> >> Acked-by: Kyungmin Park <Kyungmin Park@samsung.com> >> --- >> arch/arm/boot/dts/exynos4415-pinctrl.dtsi | 613 +++++++++++++++++++++++++++++ >> arch/arm/boot/dts/exynos4415.dtsi | 627 ++++++++++++++++++++++++++++++ >> 2 files changed, 1240 insertions(+) >> create mode 100644 arch/arm/boot/dts/exynos4415-pinctrl.dtsi >> create mode 100644 arch/arm/boot/dts/exynos4415.dtsi > > [...] > >> + >> + mp00: mp00 { >> + gpio-controller; >> + #gpio-cells = <2>; >> + }; > > After talking about above gpio ports in intranet, I thought again. And I'm still > thinking just to remove them would be better because it will not be used. Let's > remove useless mp related gpio ports (nodes) here. OK. > >> + >> + mp01: mp01 { >> + gpio-controller; >> + #gpio-cells = <2>; >> + }; >> + >> + mp02: mp02 { >> + gpio-controller; >> + #gpio-cells = <2>; >> + }; >> + >> + mp03: mp03 { >> + gpio-controller; >> + #gpio-cells = <2>; >> + }; >> + >> + mp04: mp04 { >> + gpio-controller; >> + #gpio-cells = <2>; >> + }; >> + >> + mp05: mp05 { >> + gpio-controller; >> + #gpio-cells = <2>; >> + }; >> + >> + mp06: mp06 { >> + gpio-controller; >> + #gpio-cells = <2>; >> + }; > > Same as above. OK. > > [...] > >> + etc: etc { >> + gpio-controller; >> + #gpio-cells = <2>; >> + }; > > Same, above 'etc' port will not be used I think. OK. > >> +}; >> diff --git a/arch/arm/boot/dts/exynos4415.dtsi b/arch/arm/boot/dts/exynos4415.dtsi >> new file mode 100644 >> index 0000000..078b1b8 >> --- /dev/null >> +++ b/arch/arm/boot/dts/exynos4415.dtsi >> @@ -0,0 +1,627 @@ >> +/* >> + * Samsung's Exynos4415 SoC device tree source >> + * >> + * Copyright (c) 2014 Samsung Electronics Co., Ltd. >> + * >> + * Samsung's Exynos4415 SoC device nodes are listed in this file. Exynos4415 >> + * based board files can include this file and provide values for board specfic >> + * bindings. >> + * >> + * Note: This file does not include device nodes for all the controllers in >> + * Exynos4415 SoC. As device tree coverage for Exynos4415 increases, additional >> + * nodes can be added to this file. >> + * >> + * This program is free software; you can redistribute it and/or modify >> + * it under the terms of the GNU General Public License version 2 as >> + * published by the Free Software Foundation. >> + */ >> + >> +#include "skeleton.dtsi" >> +#include <dt-bindings/clock/exynos4415.h> >> +#include <dt-bindings/clock/exynos-audss-clk.h> >> + >> +/ { >> + compatible = "samsung,exynos4415"; >> + interrupt-parent = <&gic>; >> + >> + aliases { >> + pinctrl0 = &pinctrl_0; >> + pinctrl1 = &pinctrl_1; >> + pinctrl2 = &pinctrl_2; >> + mshc0 = &mshc_0; >> + mshc1 = &mshc_1; >> + mshc2 = &mshc_2; >> + spi0 = &spi_0; >> + spi1 = &spi_1; >> + spi2 = &spi_2; >> + i2c0 = &i2c_0; >> + i2c1 = &i2c_1; >> + i2c2 = &i2c_2; >> + i2c3 = &i2c_3; >> + i2c4 = &i2c_4; >> + i2c5 = &i2c_5; >> + i2c6 = &i2c_6; >> + i2c7 = &i2c_7; >> + }; >> + >> + cpus { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + cpu0: cpu@0 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a9"; >> + reg = <0xa00>; > > This should be same with above value of 'cpu@0', 0. > > You need to use one of following: > > cpu0: cpu@a00 { > Or > reg = <0x0>; OK, I'll fix it. > >> + clock-frequency = <1600000000>; >> + }; >> + >> + cpu1: cpu@1 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a9"; >> + reg = <0xa01>; > > Same as above. OK. > >> + clock-frequency = <1600000000>; >> + }; >> + >> + cpu2: cpu@2 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a9"; >> + reg = <0xa02>; > > Same. OK. > >> + clock-frequency = <1600000000>; >> + }; >> + >> + cpu3: cpu@3 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a9"; >> + reg = <0xa03>; > > Same. OK. > >> + clock-frequency = <1600000000>; >> + }; >> + }; >> + >> + soc: soc { >> + compatible = "simple-bus"; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + ranges; >> + >> + fixed-rate-clocks { > > Maybe 'fixed-rate-clocks' depends on board not SoC so need to move to board dt > file? OK, I'll remove fixed-rate-clocks. > >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + xusbxti: clock@0 { >> + compatible = "fixed-clock"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + reg = <0>; >> + clock-frequency = <0>; >> + #clock-cells = <0>; >> + clock-output-names = "xusbxti"; >> + }; >> + >> + xxti: clock@1 { >> + compatible = "fixed-clock"; >> + reg = <1>; >> + clock-frequency = <0>; >> + #clock-cells = <0>; >> + clock-output-names = "xxti"; >> + }; >> + }; > > [...] > > Best Regards, Chanwoo Choi ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCHv3 2/2] ARM: dts: Add dts files for Exynos4415 SoC @ 2014-10-28 10:54 ` Chanwoo Choi 0 siblings, 0 replies; 10+ messages in thread From: Chanwoo Choi @ 2014-10-28 10:54 UTC (permalink / raw) To: linux-arm-kernel Dear Kukjin, On 10/28/2014 07:50 PM, Kukjin Kim wrote: > Chanwoo Choi wrote: >> > Hi, > >> This patch adds new exynos4415.dtsi to support Exynos4415 SoC >> based on Cortex-A9 quad cores and includes following dt nodes: >> >> - GIC interrupt controller (GIC-400) >> - Pinctrl to control three GPIO parts >> - CMU (Clock Management Unit) for CMU/CMU_DMC/AUDSS >> - CPU information (Cortex-A9 quad cores) >> - UART to support serial port >> - MCT (Multi Core Timer) >> - ADC (Analog Digital Converter) >> - RTC (Real Time Clock) >> - I2C/SPI busses >> - Power domains (CAM, TV, MFC, G3D, LCD0, ISP0/1) >> - PMU (Performance Monitoring Unit) >> - MSHC (Mobile Storage Host Controller) >> - EHCI (Enhanced Host Controller Interface) >> - OHIC (Open Host Controller Interface) >> - USB 2.0 device with hsotg >> - PWM (Pluse Width Modulation) Timer >> - AMBA bus for PDMA0/1 >> - SYSRAM node for memory mapping >> - SYSREG node for memory mapping >> - PMU (Power Management Unit) node for memory mapping >> >> Cc: Kukjin Kim <kgene.kim@samsung.com> >> Cc: Ben Dooks <ben-linux@fluff.org> >> Cc: Russell King <linux@arm.linux.org.uk> >> Cc: Mark Rutland <mark.rutland@arm.com> >> Cc: Olof Johansson <olof@lixom.net> >> Cc: Arnd Bergmann <arnd@arndb.de> >> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> >> Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com> >> [m.szyprowski: Add OHCI node and correct EHCI node] >> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> >> [yj44.cho: Add mipi-phy node] >> Signed-off-by: YoungJun Cho <yj44.cho@samsung.com> >> [jaewon02: Add EHCI and SPI_2 node] >> Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com> >> [ideal.song: Add I2S0 node for audio interface] >> Signed-off-by: Inha Song <ideal.song@samsung.com> >> [tomasz.figa: Add L2 cache node] >> Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> >> Acked-by: Kyungmin Park <Kyungmin Park@samsung.com> >> --- >> arch/arm/boot/dts/exynos4415-pinctrl.dtsi | 613 +++++++++++++++++++++++++++++ >> arch/arm/boot/dts/exynos4415.dtsi | 627 ++++++++++++++++++++++++++++++ >> 2 files changed, 1240 insertions(+) >> create mode 100644 arch/arm/boot/dts/exynos4415-pinctrl.dtsi >> create mode 100644 arch/arm/boot/dts/exynos4415.dtsi > > [...] > >> + >> + mp00: mp00 { >> + gpio-controller; >> + #gpio-cells = <2>; >> + }; > > After talking about above gpio ports in intranet, I thought again. And I'm still > thinking just to remove them would be better because it will not be used. Let's > remove useless mp related gpio ports (nodes) here. OK. > >> + >> + mp01: mp01 { >> + gpio-controller; >> + #gpio-cells = <2>; >> + }; >> + >> + mp02: mp02 { >> + gpio-controller; >> + #gpio-cells = <2>; >> + }; >> + >> + mp03: mp03 { >> + gpio-controller; >> + #gpio-cells = <2>; >> + }; >> + >> + mp04: mp04 { >> + gpio-controller; >> + #gpio-cells = <2>; >> + }; >> + >> + mp05: mp05 { >> + gpio-controller; >> + #gpio-cells = <2>; >> + }; >> + >> + mp06: mp06 { >> + gpio-controller; >> + #gpio-cells = <2>; >> + }; > > Same as above. OK. > > [...] > >> + etc: etc { >> + gpio-controller; >> + #gpio-cells = <2>; >> + }; > > Same, above 'etc' port will not be used I think. OK. > >> +}; >> diff --git a/arch/arm/boot/dts/exynos4415.dtsi b/arch/arm/boot/dts/exynos4415.dtsi >> new file mode 100644 >> index 0000000..078b1b8 >> --- /dev/null >> +++ b/arch/arm/boot/dts/exynos4415.dtsi >> @@ -0,0 +1,627 @@ >> +/* >> + * Samsung's Exynos4415 SoC device tree source >> + * >> + * Copyright (c) 2014 Samsung Electronics Co., Ltd. >> + * >> + * Samsung's Exynos4415 SoC device nodes are listed in this file. Exynos4415 >> + * based board files can include this file and provide values for board specfic >> + * bindings. >> + * >> + * Note: This file does not include device nodes for all the controllers in >> + * Exynos4415 SoC. As device tree coverage for Exynos4415 increases, additional >> + * nodes can be added to this file. >> + * >> + * This program is free software; you can redistribute it and/or modify >> + * it under the terms of the GNU General Public License version 2 as >> + * published by the Free Software Foundation. >> + */ >> + >> +#include "skeleton.dtsi" >> +#include <dt-bindings/clock/exynos4415.h> >> +#include <dt-bindings/clock/exynos-audss-clk.h> >> + >> +/ { >> + compatible = "samsung,exynos4415"; >> + interrupt-parent = <&gic>; >> + >> + aliases { >> + pinctrl0 = &pinctrl_0; >> + pinctrl1 = &pinctrl_1; >> + pinctrl2 = &pinctrl_2; >> + mshc0 = &mshc_0; >> + mshc1 = &mshc_1; >> + mshc2 = &mshc_2; >> + spi0 = &spi_0; >> + spi1 = &spi_1; >> + spi2 = &spi_2; >> + i2c0 = &i2c_0; >> + i2c1 = &i2c_1; >> + i2c2 = &i2c_2; >> + i2c3 = &i2c_3; >> + i2c4 = &i2c_4; >> + i2c5 = &i2c_5; >> + i2c6 = &i2c_6; >> + i2c7 = &i2c_7; >> + }; >> + >> + cpus { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + cpu0: cpu at 0 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a9"; >> + reg = <0xa00>; > > This should be same with above value of 'cpu at 0', 0. > > You need to use one of following: > > cpu0: cpu at a00 { > Or > reg = <0x0>; OK, I'll fix it. > >> + clock-frequency = <1600000000>; >> + }; >> + >> + cpu1: cpu at 1 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a9"; >> + reg = <0xa01>; > > Same as above. OK. > >> + clock-frequency = <1600000000>; >> + }; >> + >> + cpu2: cpu at 2 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a9"; >> + reg = <0xa02>; > > Same. OK. > >> + clock-frequency = <1600000000>; >> + }; >> + >> + cpu3: cpu at 3 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a9"; >> + reg = <0xa03>; > > Same. OK. > >> + clock-frequency = <1600000000>; >> + }; >> + }; >> + >> + soc: soc { >> + compatible = "simple-bus"; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + ranges; >> + >> + fixed-rate-clocks { > > Maybe 'fixed-rate-clocks' depends on board not SoC so need to move to board dt > file? OK, I'll remove fixed-rate-clocks. > >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + xusbxti: clock at 0 { >> + compatible = "fixed-clock"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + reg = <0>; >> + clock-frequency = <0>; >> + #clock-cells = <0>; >> + clock-output-names = "xusbxti"; >> + }; >> + >> + xxti: clock at 1 { >> + compatible = "fixed-clock"; >> + reg = <1>; >> + clock-frequency = <0>; >> + #clock-cells = <0>; >> + clock-output-names = "xxti"; >> + }; >> + }; > > [...] > > Best Regards, Chanwoo Choi ^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2014-10-28 10:54 UTC | newest] Thread overview: 10+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2014-10-28 4:46 [PATCHv3 0/2] ARM: EXYNOS: Support new Exynos4415 SoC based on Cortex-A9 quad cores Chanwoo Choi 2014-10-28 4:46 ` Chanwoo Choi 2014-10-28 4:46 ` [PATCHv3 1/2] ARM: EXYNOS: Add EXYNOS4415 SoC Chanwoo Choi 2014-10-28 4:46 ` Chanwoo Choi 2014-10-28 4:46 ` [PATCHv3 2/2] ARM: dts: Add dts files for Exynos4415 SoC Chanwoo Choi 2014-10-28 4:46 ` Chanwoo Choi 2014-10-28 10:50 ` Kukjin Kim 2014-10-28 10:50 ` Kukjin Kim 2014-10-28 10:54 ` Chanwoo Choi 2014-10-28 10:54 ` Chanwoo Choi
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