[PATCH 0/3] selftests/resctrl: Add Hygon CPUs support and bug fixes

[PATCH 0/3] selftests/resctrl: Add Hygon CPUs support and bug fixes

[Xiaochen Shen]

The resctrl selftest currently exhibits several failures on Hygon CPUs
due to missing vendor detection and edge-case handling specific to
Hygon's architecture.

This patch series addresses three distinct issues:
1. Missing CPU vendor detection, causing the test to fail with
   "# Can not get vendor info..." on Hygon CPUs.
2. A division-by-zero crash in SNC detection on Hygon CPUs.
3. Incorrect handling of non-contiguous CBM support on Hygon CPUs.

These changes enable resctrl selftest to run successfully on
Hygon CPUs that support Platform QoS features.

Xiaochen Shen (3):
  selftests/resctrl: Add CPU vendor detection for Hygon
  selftests/resctrl: Fix a division by zero error on Hygon
  selftests/resctrl: Fix non-contiguous CBM check for Hygon

 tools/testing/selftests/resctrl/cat_test.c      |  4 ++--
 tools/testing/selftests/resctrl/resctrl.h       |  1 +
 tools/testing/selftests/resctrl/resctrl_tests.c |  2 ++
 tools/testing/selftests/resctrl/resctrlfs.c     | 10 ++++++++++
 4 files changed, 15 insertions(+), 2 deletions(-)

-- 
2.47.3

[PATCH 1/3] selftests/resctrl: Add CPU vendor detection for Hygon

[Xiaochen Shen]

The resctrl selftest currently fails on Hygon CPUs that support Platform
QoS features, printing the error:

  "# Can not get vendor info..."

This occurs because vendor detection is missing for Hygon CPUs.

Fix this by extending the CPU vendor detection logic to include
Hygon's vendor ID.

Signed-off-by: Xiaochen Shen <shenxiaochen@open-hieco.net>
---
 tools/testing/selftests/resctrl/resctrl.h       | 1 +
 tools/testing/selftests/resctrl/resctrl_tests.c | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/tools/testing/selftests/resctrl/resctrl.h b/tools/testing/selftests/resctrl/resctrl.h
index cd3adfc14969..df2a59e0141e 100644
--- a/tools/testing/selftests/resctrl/resctrl.h
+++ b/tools/testing/selftests/resctrl/resctrl.h
@@ -38,6 +38,7 @@
  */
 #define ARCH_INTEL     1
 #define ARCH_AMD       2
+#define ARCH_HYGON     3
 
 #define END_OF_TESTS	1
 
diff --git a/tools/testing/selftests/resctrl/resctrl_tests.c b/tools/testing/selftests/resctrl/resctrl_tests.c
index 5154ffd821c4..9bf35f3beb6b 100644
--- a/tools/testing/selftests/resctrl/resctrl_tests.c
+++ b/tools/testing/selftests/resctrl/resctrl_tests.c
@@ -42,6 +42,8 @@ static int detect_vendor(void)
 		vendor_id = ARCH_INTEL;
 	else if (s && !strcmp(s, ": AuthenticAMD\n"))
 		vendor_id = ARCH_AMD;
+	else if (s && !strcmp(s, ": HygonGenuine\n"))
+		vendor_id = ARCH_HYGON;
 
 	fclose(inf);
 	free(res);
-- 
2.47.3

[PATCH 2/3] selftests/resctrl: Fix a division by zero error on Hygon

[Xiaochen Shen]

Commit

  a1cd99e700ec ("selftests/resctrl: Adjust effective L3 cache size with SNC enabled")

introduced the snc_nodes_per_l3_cache() function to detect the Intel
Sub-NUMA Clustering (SNC) feature by comparing #CPUs in node0 with #CPUs
sharing LLC with CPU0. The function was designed to return:
  (1) >1: SNC mode is enabled.
  (2)  1: SNC mode is not enabled or not supported.

However, on certain Hygon CPUs, #CPUs sharing LLC with CPU0 is actually
less than #CPUs in node0. This results in snc_nodes_per_l3_cache()
returning 0 (calculated as cache_cpus / node_cpus).

This leads to a division by zero error in get_cache_size():
  *cache_size /= snc_nodes_per_l3_cache();

Causing the resctrl selftest to fail with:
  "Floating point exception (core dumped)"

Fix the issue by ensuring snc_nodes_per_l3_cache() returns 1 when SNC
mode is not supported on the platform.

Fixes: a1cd99e700ec ("selftests/resctrl: Adjust effective L3 cache size with SNC enabled")
Signed-off-by: Xiaochen Shen <shenxiaochen@open-hieco.net>
---
 tools/testing/selftests/resctrl/resctrlfs.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/tools/testing/selftests/resctrl/resctrlfs.c b/tools/testing/selftests/resctrl/resctrlfs.c
index 195f04c4d158..2b075e7334bf 100644
--- a/tools/testing/selftests/resctrl/resctrlfs.c
+++ b/tools/testing/selftests/resctrl/resctrlfs.c
@@ -243,6 +243,16 @@ int snc_nodes_per_l3_cache(void)
 		}
 		snc_mode = cache_cpus / node_cpus;
 
+		/*
+		 * On certain Hygon platforms:
+		 * cache_cpus < node_cpus, the calculated snc_mode is 0.
+		 *
+		 * Set snc_mode = 1 to indicate that SNC mode is not
+		 * supported on the platform.
+		 */
+		if (!snc_mode)
+			snc_mode = 1;
+
 		if (snc_mode > 1)
 			ksft_print_msg("SNC-%d mode discovered.\n", snc_mode);
 	}
-- 
2.47.3

[PATCH 3/3] selftests/resctrl: Fix non-contiguous CBM check for Hygon

[Xiaochen Shen]

The resctrl selftest currently fails on Hygon CPUs that always supports
non-contiguous CBM, printing the error:

  "# Hardware and kernel differ on non-contiguous CBM support!"

This occurs because the arch_supports_noncont_cat() function lacks
vendor detection for Hygon CPUs, preventing proper identification of
their non-contiguous CBM capability.

Fix this by adding Hygon vendor ID detection to
arch_supports_noncont_cat().

Signed-off-by: Xiaochen Shen <shenxiaochen@open-hieco.net>
---
 tools/testing/selftests/resctrl/cat_test.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/tools/testing/selftests/resctrl/cat_test.c b/tools/testing/selftests/resctrl/cat_test.c
index 94cfdba5308d..59a0f80fdc5a 100644
--- a/tools/testing/selftests/resctrl/cat_test.c
+++ b/tools/testing/selftests/resctrl/cat_test.c
@@ -290,8 +290,8 @@ static int cat_run_test(const struct resctrl_test *test, const struct user_param
 
 static bool arch_supports_noncont_cat(const struct resctrl_test *test)
 {
-	/* AMD always supports non-contiguous CBM. */
-	if (get_vendor() == ARCH_AMD)
+	/* AMD and Hygon always supports non-contiguous CBM. */
+	if (get_vendor() == ARCH_AMD || get_vendor() == ARCH_HYGON)
 		return true;
 
 #if defined(__i386__) || defined(__x86_64__) /* arch */
-- 
2.47.3

Re: [PATCH 1/3] selftests/resctrl: Add CPU vendor detection for Hygon

[Reinette Chatre]

Hi Xiaochen,

On 12/4/25 4:38 AM, Xiaochen Shen wrote:
> The resctrl selftest currently fails on Hygon CPUs that support Platform
> QoS features, printing the error:
> 
>   "# Can not get vendor info..."
> 
> This occurs because vendor detection is missing for Hygon CPUs.
> 
> Fix this by extending the CPU vendor detection logic to include
> Hygon's vendor ID.
> 
> Signed-off-by: Xiaochen Shen <shenxiaochen@open-hieco.net>
> ---
>  tools/testing/selftests/resctrl/resctrl.h       | 1 +
>  tools/testing/selftests/resctrl/resctrl_tests.c | 2 ++
>  2 files changed, 3 insertions(+)
> 
> diff --git a/tools/testing/selftests/resctrl/resctrl.h b/tools/testing/selftests/resctrl/resctrl.h
> index cd3adfc14969..df2a59e0141e 100644
> --- a/tools/testing/selftests/resctrl/resctrl.h
> +++ b/tools/testing/selftests/resctrl/resctrl.h
> @@ -38,6 +38,7 @@
>   */
>  #define ARCH_INTEL     1
>  #define ARCH_AMD       2
> +#define ARCH_HYGON     3

The comment before these defines attempts to provide guidance but it is clearly still
quite subtle that these values are required to be unique bits. Consider for example
their usage in test_vendor_specific_check():
	return get_vendor() & test->vendor_specific

This should either be 4 or a better solution is probably to switch all of these to use
BIT() (linux/bits.h is available via tools/include that is already in include path).

Reinette

Re: [PATCH 3/3] selftests/resctrl: Fix non-contiguous CBM check for Hygon

[Reinette Chatre]

Hi Xiaochen,

On 12/4/25 4:38 AM, Xiaochen Shen wrote:
> The resctrl selftest currently fails on Hygon CPUs that always supports
> non-contiguous CBM, printing the error:
> 
>   "# Hardware and kernel differ on non-contiguous CBM support!"
> 
> This occurs because the arch_supports_noncont_cat() function lacks
> vendor detection for Hygon CPUs, preventing proper identification of
> their non-contiguous CBM capability.
> 
> Fix this by adding Hygon vendor ID detection to
> arch_supports_noncont_cat().
> 
> Signed-off-by: Xiaochen Shen <shenxiaochen@open-hieco.net>
> ---

I think it may help to add a maintainer note here to highlight even though this
is a fix it is not a candidate for backport since, based on your other series,
support for Hygon is in process of being added to resctrl.

>  tools/testing/selftests/resctrl/cat_test.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/tools/testing/selftests/resctrl/cat_test.c b/tools/testing/selftests/resctrl/cat_test.c
> index 94cfdba5308d..59a0f80fdc5a 100644
> --- a/tools/testing/selftests/resctrl/cat_test.c
> +++ b/tools/testing/selftests/resctrl/cat_test.c
> @@ -290,8 +290,8 @@ static int cat_run_test(const struct resctrl_test *test, const struct user_param
>  
>  static bool arch_supports_noncont_cat(const struct resctrl_test *test)
>  {
> -	/* AMD always supports non-contiguous CBM. */
> -	if (get_vendor() == ARCH_AMD)
> +	/* AMD and Hygon always supports non-contiguous CBM. */
> +	if (get_vendor() == ARCH_AMD || get_vendor() == ARCH_HYGON)
>  		return true;
>  
>  #if defined(__i386__) || defined(__x86_64__) /* arch */

Reviewed-by: Reinette Chatre <reinette.chatre@intel.com>

Reinette

Re: [PATCH 2/3] selftests/resctrl: Fix a division by zero error on Hygon

[Reinette Chatre]

Hi Xiaochen,

On 12/4/25 4:38 AM, Xiaochen Shen wrote:
> Commit
> 
>   a1cd99e700ec ("selftests/resctrl: Adjust effective L3 cache size with SNC enabled")
> 
> introduced the snc_nodes_per_l3_cache() function to detect the Intel
> Sub-NUMA Clustering (SNC) feature by comparing #CPUs in node0 with #CPUs
> sharing LLC with CPU0. The function was designed to return:
>   (1) >1: SNC mode is enabled.
>   (2)  1: SNC mode is not enabled or not supported.
> 
> However, on certain Hygon CPUs, #CPUs sharing LLC with CPU0 is actually
> less than #CPUs in node0. This results in snc_nodes_per_l3_cache()
> returning 0 (calculated as cache_cpus / node_cpus).
> 
> This leads to a division by zero error in get_cache_size():
>   *cache_size /= snc_nodes_per_l3_cache();
> 
> Causing the resctrl selftest to fail with:
>   "Floating point exception (core dumped)"
> 
> Fix the issue by ensuring snc_nodes_per_l3_cache() returns 1 when SNC
> mode is not supported on the platform.
> 
> Fixes: a1cd99e700ec ("selftests/resctrl: Adjust effective L3 cache size with SNC enabled")
> Signed-off-by: Xiaochen Shen <shenxiaochen@open-hieco.net>
> ---

Could you please include Shuah Khan <shuah@kernel.org> and linux-kselftest@vger.kernel.org 
in resctrl selftest posts?

Reviewed-by: Reinette Chatre <reinette.chatre@intel.com>

Reinette

Re: [PATCH 2/3] selftests/resctrl: Fix a division by zero error on Hygon

[Xiaochen Shen]

Hi Reinette,

On 12/5/2025 8:56 AM, Reinette Chatre wrote:
> Could you please include Shuah Khan <shuah@kernel.org> and linux-kselftest@vger.kernel.org 
> in resctrl selftest posts?
> 

Thank you.
I apologize for omitting the kselftest maintainer and mailing list.
I will ensure they are included in the v2 patch series submission.


> Reviewed-by: Reinette Chatre <reinette.chatre@intel.com>
> 
> Reinette

Thank you very much for code review!

Best regards,
Xiaochen Shen

Re: [PATCH 1/3] selftests/resctrl: Add CPU vendor detection for Hygon

[Xiaochen Shen]

Hi Reinette,

On 12/5/2025 7:48 AM, Reinette Chatre wrote:
>>  #define ARCH_INTEL     1
>>  #define ARCH_AMD       2
>> +#define ARCH_HYGON     3
> The comment before these defines attempts to provide guidance but it is clearly still
> quite subtle that these values are required to be unique bits. Consider for example
> their usage in test_vendor_specific_check():
> 	return get_vendor() & test->vendor_specific
> 
> This should either be 4 or a better solution is probably to switch all of these to use
> BIT() (linux/bits.h is available via tools/include that is already in include path).
> 
> Reinette


Thank you. How about this code change?

+#include <linux/bits.h>

...

-#define ARCH_INTEL     1
-#define ARCH_AMD       2
+#define ARCH_INTEL     BIT(0)
+#define ARCH_AMD       BIT(1)
+#define ARCH_HYGON     BIT(2)


Best regards,
Xiaochen Shen

Re: [PATCH 3/3] selftests/resctrl: Fix non-contiguous CBM check for Hygon

[Xiaochen Shen]

Hi Reinette,

On 12/5/2025 8:55 AM, Reinette Chatre wrote:
>> Signed-off-by: Xiaochen Shen <shenxiaochen@open-hieco.net>
>> ---
> I think it may help to add a maintainer note here to highlight even though this
> is a fix it is not a candidate for backport since, based on your other series,
> support for Hygon is in process of being added to resctrl.
>

Great suggestion.
I will add a maintainer note as you suggested in v2 patch series.

 
>>  tools/testing/selftests/resctrl/cat_test.c | 4 ++--
>>  1 file changed, 2 insertions(+), 2 deletions(-)
> Reviewed-by: Reinette Chatre <reinette.chatre@intel.com>
> 
> Reinette

Thank you very much for code review!


Best regards,
Xiaochen Shen