From: "Liang, Kan" <kan.liang@linux.intel.com>
To: Dave Hansen <dave.hansen@intel.com>,
peterz@infradead.org, mingo@redhat.com, acme@kernel.org,
namhyung@kernel.org, tglx@linutronix.de,
dave.hansen@linux.intel.com, irogers@google.com,
adrian.hunter@intel.com, jolsa@kernel.org,
alexander.shishkin@linux.intel.com, linux-kernel@vger.kernel.org
Cc: dapeng1.mi@linux.intel.com, ak@linux.intel.com, zide.chen@intel.com
Subject: Re: [RFC PATCH 05/12] perf/x86: Support XMM register for non-PEBS and REGS_USER
Date: Fri, 13 Jun 2025 14:14:05 -0400 [thread overview]
Message-ID: <067e0923-d904-4382-bf49-34083f9927e7@linux.intel.com> (raw)
In-Reply-To: <9054bf0d-85db-4bd4-9f67-7c71d7866e6a@intel.com>
On 2025-06-13 11:34 a.m., Dave Hansen wrote:
> On 6/13/25 06:49, kan.liang@linux.intel.com wrote:
>> +static void x86_pmu_get_ext_regs(struct x86_perf_regs *perf_regs, u64 mask)
>> +{
>> + void *xsave = (void *)ALIGN((unsigned long)per_cpu(ext_regs_buf, smp_processor_id()), 64);
>> + struct xregs_state *xregs_xsave = xsave;
>> + u64 xcomp_bv;
>> +
>> + if (WARN_ON_ONCE(!xsave))
>> + return;
>> +
>> + xsaves_nmi(xsave, mask);
>> +
>> + xcomp_bv = xregs_xsave->header.xcomp_bv;
>> + if (mask & XFEATURE_MASK_SSE && xcomp_bv & XFEATURE_SSE)
>> + perf_regs->xmm_regs = (u64 *)xregs_xsave->i387.xmm_space;
>> +}
>
> Now that I'm thinking about the init optimization... This is buggy.
>
> Isn't XSAVE fun?
>
> Here's a little primer:
>
> xcomp_bv - tells you what the format of the buffer is.
> Which states are where.
> xstate_bv - (aka. xfeatures) tells you which things XSAVES
> wrote to the buffer.
I got the definitions of the two reversed. :(
>
> It's totally valid to have a feature set in xcomp_bv but not xstate_bv.
>
> xcomp_bv is actually pretty boring:
>
> The XSAVES instructions sets bit 63 of the XCOMP_BV field of the
> XSAVE header while writing RFBM[62:0] to XCOMP_BV[62:0]
>
> Since you know the RFBM, you also know xstate_bv. You don't need to read
> it out of the buffer even.
>
> Oh, and what's with the:
>
> xcomp_bv & XFEATURE_SSE
>
> ? xcomp_bv is a bitmap, just like 'mask'
>
> So, what do you do when
>
> if (!(xregs_xsave->header.xfeatures & XFEATURE_MASK_SSE))
> ... here?
>
> The "XSAVE-Enabled Registers Group" docs say:
>
> The first eight bytes include the XSAVES instruction’s XSTATE_BV
> bit vector (reflecting INIT optimization). This field
> is in XCR0 format.
>
> So the PEBS parsing code has to know how to deal with this situation too
> and not copy the xmm_regs out to users.
Now, perf will copy all 0 to users if !perf_regs->xmm_regs. But 0 should
be a valid value for the xmm_regs. Perf probably need to dump a bitmap
which indicates what regs are really collected. It may be slightly
different from the requested bitmap because of the above case.
Thanks,
Kan
next prev parent reply other threads:[~2025-06-13 18:14 UTC|newest]
Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-13 13:49 [RFC PATCH 00/12] Support vector and more extended registers in perf kan.liang
2025-06-13 13:49 ` [RFC PATCH 01/12] perf/x86: Use x86_perf_regs in the x86 nmi handler kan.liang
2025-06-13 13:49 ` [RFC PATCH 02/12] perf/x86: Setup the regs data kan.liang
2025-06-13 13:49 ` [RFC PATCH 03/12] x86/fpu/xstate: Add xsaves_nmi kan.liang
2025-06-13 14:39 ` Dave Hansen
2025-06-13 14:54 ` Liang, Kan
2025-06-13 15:19 ` Dave Hansen
2025-06-13 13:49 ` [RFC PATCH 04/12] perf: Move has_extended_regs() to header file kan.liang
2025-06-13 13:49 ` [RFC PATCH 05/12] perf/x86: Support XMM register for non-PEBS and REGS_USER kan.liang
2025-06-13 15:15 ` Dave Hansen
2025-06-13 17:51 ` Liang, Kan
2025-06-13 15:34 ` Dave Hansen
2025-06-13 18:14 ` Liang, Kan [this message]
2025-06-13 13:49 ` [RFC PATCH 06/12] perf: Support extension of sample_regs kan.liang
2025-06-17 8:00 ` Mi, Dapeng
2025-06-17 8:14 ` Peter Zijlstra
2025-06-17 9:49 ` Mi, Dapeng
2025-06-17 10:28 ` Peter Zijlstra
2025-06-17 12:14 ` Mi, Dapeng
2025-06-17 13:33 ` Peter Zijlstra
2025-06-17 14:06 ` Peter Zijlstra
2025-06-17 14:24 ` Mark Rutland
2025-06-17 14:44 ` Peter Zijlstra
2025-06-17 14:55 ` Mark Rutland
2025-06-17 19:00 ` Mark Brown
2025-06-17 20:32 ` Liang, Kan
2025-06-18 9:35 ` Peter Zijlstra
2025-06-18 10:10 ` Liang, Kan
2025-06-18 13:30 ` Peter Zijlstra
2025-06-18 13:52 ` Liang, Kan
2025-06-18 14:30 ` Dave Hansen
2025-06-18 14:47 ` Dave Hansen
2025-06-18 15:24 ` Liang, Kan
2025-06-18 14:45 ` Peter Zijlstra
2025-06-18 15:22 ` Liang, Kan
2025-06-13 13:49 ` [RFC PATCH 07/12] perf/x86: Add YMMH in extended regs kan.liang
2025-06-13 15:48 ` Dave Hansen
2025-06-13 13:49 ` [RFC PATCH 08/12] perf/x86: Add APX " kan.liang
2025-06-13 16:02 ` Dave Hansen
2025-06-13 17:17 ` Liang, Kan
2025-06-17 8:19 ` Peter Zijlstra
2025-06-13 13:49 ` [RFC PATCH 09/12] perf/x86: Add OPMASK " kan.liang
2025-06-13 13:49 ` [RFC PATCH 10/12] perf/x86: Add ZMM " kan.liang
2025-06-13 13:49 ` [RFC PATCH 11/12] perf/x86: Add SSP " kan.liang
2025-06-13 13:49 ` [RFC PATCH 12/12] perf/x86/intel: Support extended registers kan.liang
2025-06-17 7:50 ` [RFC PATCH 00/12] Support vector and more extended registers in perf Mi, Dapeng
2025-06-17 8:24 ` Peter Zijlstra
2025-06-17 13:52 ` Liang, Kan
2025-06-17 14:29 ` Peter Zijlstra
2025-06-17 15:23 ` Liang, Kan
2025-06-17 17:34 ` Peter Zijlstra
2025-06-18 0:57 ` Mi, Dapeng
2025-06-18 10:47 ` Liang, Kan
2025-06-18 12:28 ` Mi, Dapeng
2025-06-18 13:15 ` Liang, Kan
2025-06-19 0:41 ` Mi, Dapeng
2025-06-19 11:11 ` Liang, Kan
2025-06-19 12:26 ` Mi, Dapeng
2025-06-19 13:38 ` Peter Zijlstra
2025-06-19 14:27 ` Liang, Kan
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