* [PATCH 0/5] Add CPU caches information for some MediaTek SoCs
@ 2022-12-06 11:23 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 14+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-12-06 11:23 UTC (permalink / raw)
To: matthias.bgg
Cc: robh+dt, krzysztof.kozlowski+dt, nfraprado, kernel, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel,
AngeloGioacchino Del Regno
In devicetrees for MediaTek SoCs the CPU caches information, if
present, is incomplete as it misses cache size, cache line size
and number of cache sets which, in turn, will also prevent any
cache associativity calculation.
For all of the SoCs that I know and/or I have information for,
I've added the right information for I/D, L2 and L3 where present.
This will also make the cacheinfo driver to correctly export the
CPU cache information to sysfs.
AngeloGioacchino Del Regno (5):
arm64: dts: mt8195: Add complete CPU caches information
arm64: dts: mt8192: Add complete CPU caches information
arm64: dts: mt8186: Add complete CPU caches information
arm64: dts: mt8183: Add complete CPU caches information
arm64: dts: mt6795: Add complete CPU caches information
arch/arm64/boot/dts/mediatek/mt6795.dtsi | 50 ++++++++++++++++
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 74 ++++++++++++++++++++++++
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 58 +++++++++++++++++++
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 58 +++++++++++++++++++
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 58 +++++++++++++++++++
5 files changed, 298 insertions(+)
--
2.38.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 1/5] arm64: dts: mt8195: Add complete CPU caches information
2022-12-06 11:23 ` AngeloGioacchino Del Regno
@ 2022-12-06 11:23 ` AngeloGioacchino Del Regno
-1 siblings, 0 replies; 14+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-12-06 11:23 UTC (permalink / raw)
To: matthias.bgg
Cc: robh+dt, krzysztof.kozlowski+dt, nfraprado, kernel, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel,
AngeloGioacchino Del Regno
This SoC features two clusters composed of:
- 4x Cortex A55: 32KB I-cache and 32KB D-cache, 4-way set associative,
per-cpu 128KB L2 cache, 4-way set associative;
- 4x Cortex A78: 64KB I-cache and 64KB D-cache, 4-way set associative,
per-cpu 256KB L2 cache, 8-way set associative;
Moreover, the two clusters are sharing a DSU L3 cache with size 2MB,
16-way set associative.
With that in mind, add the appropriate properties needed to specify the
caches information for this SoC, which will now be correctly exported
to sysfs.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 58 ++++++++++++++++++++++++
1 file changed, 58 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 5d31536f4c48..539c49324d64 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -39,6 +39,12 @@ cpu0: cpu@0 {
clock-frequency = <1701000000>;
capacity-dmips-mhz = <308>;
cpu-idle-states = <&cpu_off_l &cluster_off_l>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
};
@@ -52,6 +58,12 @@ cpu1: cpu@100 {
clock-frequency = <1701000000>;
capacity-dmips-mhz = <308>;
cpu-idle-states = <&cpu_off_l &cluster_off_l>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
};
@@ -65,6 +77,12 @@ cpu2: cpu@200 {
clock-frequency = <1701000000>;
capacity-dmips-mhz = <308>;
cpu-idle-states = <&cpu_off_l &cluster_off_l>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
};
@@ -78,6 +96,12 @@ cpu3: cpu@300 {
clock-frequency = <1701000000>;
capacity-dmips-mhz = <308>;
cpu-idle-states = <&cpu_off_l &cluster_off_l>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
};
@@ -91,6 +115,12 @@ cpu4: cpu@400 {
clock-frequency = <2171000000>;
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&cpu_off_b &cluster_off_b>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
next-level-cache = <&l2_1>;
#cooling-cells = <2>;
};
@@ -104,6 +134,12 @@ cpu5: cpu@500 {
clock-frequency = <2171000000>;
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&cpu_off_b &cluster_off_b>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
next-level-cache = <&l2_1>;
#cooling-cells = <2>;
};
@@ -117,6 +153,12 @@ cpu6: cpu@600 {
clock-frequency = <2171000000>;
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&cpu_off_b &cluster_off_b>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
next-level-cache = <&l2_1>;
#cooling-cells = <2>;
};
@@ -130,6 +172,12 @@ cpu7: cpu@700 {
clock-frequency = <2171000000>;
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&cpu_off_b &cluster_off_b>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
next-level-cache = <&l2_1>;
#cooling-cells = <2>;
};
@@ -215,18 +263,28 @@ cluster_off_b: cluster-off-b {
l2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
+ cache-size = <131072>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
next-level-cache = <&l3_0>;
};
l2_1: l2-cache1 {
compatible = "cache";
cache-level = <2>;
+ cache-size = <262144>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
next-level-cache = <&l3_0>;
};
l3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
+ cache-size = <2097152>;
+ cache-line-size = <64>;
+ cache-sets = <2048>;
+ cache-unified;
};
};
--
2.38.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH 1/5] arm64: dts: mt8195: Add complete CPU caches information
@ 2022-12-06 11:23 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 14+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-12-06 11:23 UTC (permalink / raw)
To: matthias.bgg
Cc: robh+dt, krzysztof.kozlowski+dt, nfraprado, kernel, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel,
AngeloGioacchino Del Regno
This SoC features two clusters composed of:
- 4x Cortex A55: 32KB I-cache and 32KB D-cache, 4-way set associative,
per-cpu 128KB L2 cache, 4-way set associative;
- 4x Cortex A78: 64KB I-cache and 64KB D-cache, 4-way set associative,
per-cpu 256KB L2 cache, 8-way set associative;
Moreover, the two clusters are sharing a DSU L3 cache with size 2MB,
16-way set associative.
With that in mind, add the appropriate properties needed to specify the
caches information for this SoC, which will now be correctly exported
to sysfs.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 58 ++++++++++++++++++++++++
1 file changed, 58 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 5d31536f4c48..539c49324d64 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -39,6 +39,12 @@ cpu0: cpu@0 {
clock-frequency = <1701000000>;
capacity-dmips-mhz = <308>;
cpu-idle-states = <&cpu_off_l &cluster_off_l>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
};
@@ -52,6 +58,12 @@ cpu1: cpu@100 {
clock-frequency = <1701000000>;
capacity-dmips-mhz = <308>;
cpu-idle-states = <&cpu_off_l &cluster_off_l>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
};
@@ -65,6 +77,12 @@ cpu2: cpu@200 {
clock-frequency = <1701000000>;
capacity-dmips-mhz = <308>;
cpu-idle-states = <&cpu_off_l &cluster_off_l>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
};
@@ -78,6 +96,12 @@ cpu3: cpu@300 {
clock-frequency = <1701000000>;
capacity-dmips-mhz = <308>;
cpu-idle-states = <&cpu_off_l &cluster_off_l>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
};
@@ -91,6 +115,12 @@ cpu4: cpu@400 {
clock-frequency = <2171000000>;
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&cpu_off_b &cluster_off_b>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
next-level-cache = <&l2_1>;
#cooling-cells = <2>;
};
@@ -104,6 +134,12 @@ cpu5: cpu@500 {
clock-frequency = <2171000000>;
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&cpu_off_b &cluster_off_b>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
next-level-cache = <&l2_1>;
#cooling-cells = <2>;
};
@@ -117,6 +153,12 @@ cpu6: cpu@600 {
clock-frequency = <2171000000>;
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&cpu_off_b &cluster_off_b>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
next-level-cache = <&l2_1>;
#cooling-cells = <2>;
};
@@ -130,6 +172,12 @@ cpu7: cpu@700 {
clock-frequency = <2171000000>;
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&cpu_off_b &cluster_off_b>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
next-level-cache = <&l2_1>;
#cooling-cells = <2>;
};
@@ -215,18 +263,28 @@ cluster_off_b: cluster-off-b {
l2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
+ cache-size = <131072>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
next-level-cache = <&l3_0>;
};
l2_1: l2-cache1 {
compatible = "cache";
cache-level = <2>;
+ cache-size = <262144>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
next-level-cache = <&l3_0>;
};
l3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
+ cache-size = <2097152>;
+ cache-line-size = <64>;
+ cache-sets = <2048>;
+ cache-unified;
};
};
--
2.38.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 2/5] arm64: dts: mt8192: Add complete CPU caches information
2022-12-06 11:23 ` AngeloGioacchino Del Regno
@ 2022-12-06 11:23 ` AngeloGioacchino Del Regno
-1 siblings, 0 replies; 14+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-12-06 11:23 UTC (permalink / raw)
To: matthias.bgg
Cc: robh+dt, krzysztof.kozlowski+dt, nfraprado, kernel, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel,
AngeloGioacchino Del Regno
This SoC features two clusters composed of:
- 4x Cortex A55: 32KB I-cache and 32KB D-cache, 4-way set associative,
per-cpu 128KB L2 cache, 4-way set associative;
- 4x Cortex A76: 64KB I-cache and 64KB D-cache, 4-way set associative,
per-cpu 256KB L2 cache, 8-way set associative;
Moreover, the two clusters are sharing a DSU L3 cache with size 2MB,
16-way set associative.
With that in mind, add the appropriate properties needed to specify the
caches information for this SoC, which will now be correctly exported
to sysfs.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 58 ++++++++++++++++++++++++
1 file changed, 58 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 424fc89cc6f7..3b5d49bf174d 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -54,6 +54,12 @@ cpu0: cpu@0 {
enable-method = "psci";
clock-frequency = <1701000000>;
cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
next-level-cache = <&l2_0>;
capacity-dmips-mhz = <530>;
};
@@ -65,6 +71,12 @@ cpu1: cpu@100 {
enable-method = "psci";
clock-frequency = <1701000000>;
cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
next-level-cache = <&l2_0>;
capacity-dmips-mhz = <530>;
};
@@ -76,6 +88,12 @@ cpu2: cpu@200 {
enable-method = "psci";
clock-frequency = <1701000000>;
cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
next-level-cache = <&l2_0>;
capacity-dmips-mhz = <530>;
};
@@ -87,6 +105,12 @@ cpu3: cpu@300 {
enable-method = "psci";
clock-frequency = <1701000000>;
cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
next-level-cache = <&l2_0>;
capacity-dmips-mhz = <530>;
};
@@ -98,6 +122,12 @@ cpu4: cpu@400 {
enable-method = "psci";
clock-frequency = <2171000000>;
cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
next-level-cache = <&l2_1>;
capacity-dmips-mhz = <1024>;
};
@@ -109,6 +139,12 @@ cpu5: cpu@500 {
enable-method = "psci";
clock-frequency = <2171000000>;
cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
next-level-cache = <&l2_1>;
capacity-dmips-mhz = <1024>;
};
@@ -120,6 +156,12 @@ cpu6: cpu@600 {
enable-method = "psci";
clock-frequency = <2171000000>;
cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
next-level-cache = <&l2_1>;
capacity-dmips-mhz = <1024>;
};
@@ -131,6 +173,12 @@ cpu7: cpu@700 {
enable-method = "psci";
clock-frequency = <2171000000>;
cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
next-level-cache = <&l2_1>;
capacity-dmips-mhz = <1024>;
};
@@ -170,18 +218,28 @@ core3 {
l2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
+ cache-size = <131072>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
next-level-cache = <&l3_0>;
};
l2_1: l2-cache1 {
compatible = "cache";
cache-level = <2>;
+ cache-size = <262144>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
next-level-cache = <&l3_0>;
};
l3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
+ cache-size = <2097152>;
+ cache-line-size = <64>;
+ cache-sets = <2048>;
+ cache-unified;
};
idle-states {
--
2.38.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH 2/5] arm64: dts: mt8192: Add complete CPU caches information
@ 2022-12-06 11:23 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 14+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-12-06 11:23 UTC (permalink / raw)
To: matthias.bgg
Cc: robh+dt, krzysztof.kozlowski+dt, nfraprado, kernel, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel,
AngeloGioacchino Del Regno
This SoC features two clusters composed of:
- 4x Cortex A55: 32KB I-cache and 32KB D-cache, 4-way set associative,
per-cpu 128KB L2 cache, 4-way set associative;
- 4x Cortex A76: 64KB I-cache and 64KB D-cache, 4-way set associative,
per-cpu 256KB L2 cache, 8-way set associative;
Moreover, the two clusters are sharing a DSU L3 cache with size 2MB,
16-way set associative.
With that in mind, add the appropriate properties needed to specify the
caches information for this SoC, which will now be correctly exported
to sysfs.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 58 ++++++++++++++++++++++++
1 file changed, 58 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 424fc89cc6f7..3b5d49bf174d 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -54,6 +54,12 @@ cpu0: cpu@0 {
enable-method = "psci";
clock-frequency = <1701000000>;
cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
next-level-cache = <&l2_0>;
capacity-dmips-mhz = <530>;
};
@@ -65,6 +71,12 @@ cpu1: cpu@100 {
enable-method = "psci";
clock-frequency = <1701000000>;
cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
next-level-cache = <&l2_0>;
capacity-dmips-mhz = <530>;
};
@@ -76,6 +88,12 @@ cpu2: cpu@200 {
enable-method = "psci";
clock-frequency = <1701000000>;
cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
next-level-cache = <&l2_0>;
capacity-dmips-mhz = <530>;
};
@@ -87,6 +105,12 @@ cpu3: cpu@300 {
enable-method = "psci";
clock-frequency = <1701000000>;
cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
next-level-cache = <&l2_0>;
capacity-dmips-mhz = <530>;
};
@@ -98,6 +122,12 @@ cpu4: cpu@400 {
enable-method = "psci";
clock-frequency = <2171000000>;
cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
next-level-cache = <&l2_1>;
capacity-dmips-mhz = <1024>;
};
@@ -109,6 +139,12 @@ cpu5: cpu@500 {
enable-method = "psci";
clock-frequency = <2171000000>;
cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
next-level-cache = <&l2_1>;
capacity-dmips-mhz = <1024>;
};
@@ -120,6 +156,12 @@ cpu6: cpu@600 {
enable-method = "psci";
clock-frequency = <2171000000>;
cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
next-level-cache = <&l2_1>;
capacity-dmips-mhz = <1024>;
};
@@ -131,6 +173,12 @@ cpu7: cpu@700 {
enable-method = "psci";
clock-frequency = <2171000000>;
cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
next-level-cache = <&l2_1>;
capacity-dmips-mhz = <1024>;
};
@@ -170,18 +218,28 @@ core3 {
l2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
+ cache-size = <131072>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
next-level-cache = <&l3_0>;
};
l2_1: l2-cache1 {
compatible = "cache";
cache-level = <2>;
+ cache-size = <262144>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
next-level-cache = <&l3_0>;
};
l3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
+ cache-size = <2097152>;
+ cache-line-size = <64>;
+ cache-sets = <2048>;
+ cache-unified;
};
idle-states {
--
2.38.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 3/5] arm64: dts: mt8186: Add complete CPU caches information
2022-12-06 11:23 ` AngeloGioacchino Del Regno
@ 2022-12-06 11:23 ` AngeloGioacchino Del Regno
-1 siblings, 0 replies; 14+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-12-06 11:23 UTC (permalink / raw)
To: matthias.bgg
Cc: robh+dt, krzysztof.kozlowski+dt, nfraprado, kernel, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel,
AngeloGioacchino Del Regno
This SoC features two clusters composed of:
- 6x Cortex A55: 32KB I-cache and 32KB D-cache, 4-way set associative,
per-cpu 128KB L2 cache, 4-way set associative;
- 2x Cortex A76: 64KB I-cache and 64KB D-cache, 4-way set associative,
per-cpu 256KB L2 cache, 8-way set associative;
Moreover, the two clusters are sharing a DSU L3 cache with size 1MB,
16-way set associative.
With that in mind, add the appropriate properties needed to specify the
caches information for this SoC, which will now be correctly exported
to sysfs.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 58 ++++++++++++++++++++++++
1 file changed, 58 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index 4a2f7ad3c6f0..c4a80ce3124c 100644
--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -69,6 +69,12 @@ cpu0: cpu@0 {
clock-frequency = <2000000000>;
capacity-dmips-mhz = <382>;
cpu-idle-states = <&cpu_off_l &cluster_off_l>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
};
@@ -81,6 +87,12 @@ cpu1: cpu@100 {
clock-frequency = <2000000000>;
capacity-dmips-mhz = <382>;
cpu-idle-states = <&cpu_off_l &cluster_off_l>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
};
@@ -93,6 +105,12 @@ cpu2: cpu@200 {
clock-frequency = <2000000000>;
capacity-dmips-mhz = <382>;
cpu-idle-states = <&cpu_off_l &cluster_off_l>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
};
@@ -105,6 +123,12 @@ cpu3: cpu@300 {
clock-frequency = <2000000000>;
capacity-dmips-mhz = <382>;
cpu-idle-states = <&cpu_off_l &cluster_off_l>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
};
@@ -117,6 +141,12 @@ cpu4: cpu@400 {
clock-frequency = <2000000000>;
capacity-dmips-mhz = <382>;
cpu-idle-states = <&cpu_off_l &cluster_off_l>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
};
@@ -129,6 +159,12 @@ cpu5: cpu@500 {
clock-frequency = <2000000000>;
capacity-dmips-mhz = <382>;
cpu-idle-states = <&cpu_off_l &cluster_off_l>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
};
@@ -141,6 +177,12 @@ cpu6: cpu@600 {
clock-frequency = <2050000000>;
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&cpu_off_b &cluster_off_b>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
next-level-cache = <&l2_1>;
#cooling-cells = <2>;
};
@@ -153,6 +195,12 @@ cpu7: cpu@700 {
clock-frequency = <2050000000>;
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&cpu_off_b &cluster_off_b>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
next-level-cache = <&l2_1>;
#cooling-cells = <2>;
};
@@ -200,18 +248,28 @@ cluster_off_b: cluster-off-b {
l2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
+ cache-size = <131072>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
next-level-cache = <&l3_0>;
};
l2_1: l2-cache1 {
compatible = "cache";
cache-level = <2>;
+ cache-size = <262144>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
next-level-cache = <&l3_0>;
};
l3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
+ cache-size = <1048576>;
+ cache-line-size = <64>;
+ cache-sets = <1024>;
+ cache-unified;
};
};
--
2.38.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH 3/5] arm64: dts: mt8186: Add complete CPU caches information
@ 2022-12-06 11:23 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 14+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-12-06 11:23 UTC (permalink / raw)
To: matthias.bgg
Cc: robh+dt, krzysztof.kozlowski+dt, nfraprado, kernel, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel,
AngeloGioacchino Del Regno
This SoC features two clusters composed of:
- 6x Cortex A55: 32KB I-cache and 32KB D-cache, 4-way set associative,
per-cpu 128KB L2 cache, 4-way set associative;
- 2x Cortex A76: 64KB I-cache and 64KB D-cache, 4-way set associative,
per-cpu 256KB L2 cache, 8-way set associative;
Moreover, the two clusters are sharing a DSU L3 cache with size 1MB,
16-way set associative.
With that in mind, add the appropriate properties needed to specify the
caches information for this SoC, which will now be correctly exported
to sysfs.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 58 ++++++++++++++++++++++++
1 file changed, 58 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index 4a2f7ad3c6f0..c4a80ce3124c 100644
--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -69,6 +69,12 @@ cpu0: cpu@0 {
clock-frequency = <2000000000>;
capacity-dmips-mhz = <382>;
cpu-idle-states = <&cpu_off_l &cluster_off_l>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
};
@@ -81,6 +87,12 @@ cpu1: cpu@100 {
clock-frequency = <2000000000>;
capacity-dmips-mhz = <382>;
cpu-idle-states = <&cpu_off_l &cluster_off_l>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
};
@@ -93,6 +105,12 @@ cpu2: cpu@200 {
clock-frequency = <2000000000>;
capacity-dmips-mhz = <382>;
cpu-idle-states = <&cpu_off_l &cluster_off_l>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
};
@@ -105,6 +123,12 @@ cpu3: cpu@300 {
clock-frequency = <2000000000>;
capacity-dmips-mhz = <382>;
cpu-idle-states = <&cpu_off_l &cluster_off_l>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
};
@@ -117,6 +141,12 @@ cpu4: cpu@400 {
clock-frequency = <2000000000>;
capacity-dmips-mhz = <382>;
cpu-idle-states = <&cpu_off_l &cluster_off_l>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
};
@@ -129,6 +159,12 @@ cpu5: cpu@500 {
clock-frequency = <2000000000>;
capacity-dmips-mhz = <382>;
cpu-idle-states = <&cpu_off_l &cluster_off_l>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <128>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
next-level-cache = <&l2_0>;
#cooling-cells = <2>;
};
@@ -141,6 +177,12 @@ cpu6: cpu@600 {
clock-frequency = <2050000000>;
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&cpu_off_b &cluster_off_b>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
next-level-cache = <&l2_1>;
#cooling-cells = <2>;
};
@@ -153,6 +195,12 @@ cpu7: cpu@700 {
clock-frequency = <2050000000>;
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&cpu_off_b &cluster_off_b>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
next-level-cache = <&l2_1>;
#cooling-cells = <2>;
};
@@ -200,18 +248,28 @@ cluster_off_b: cluster-off-b {
l2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
+ cache-size = <131072>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
next-level-cache = <&l3_0>;
};
l2_1: l2-cache1 {
compatible = "cache";
cache-level = <2>;
+ cache-size = <262144>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
next-level-cache = <&l3_0>;
};
l3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
+ cache-size = <1048576>;
+ cache-line-size = <64>;
+ cache-sets = <1024>;
+ cache-unified;
};
};
--
2.38.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 4/5] arm64: dts: mt8183: Add complete CPU caches information
2022-12-06 11:23 ` AngeloGioacchino Del Regno
@ 2022-12-06 11:23 ` AngeloGioacchino Del Regno
-1 siblings, 0 replies; 14+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-12-06 11:23 UTC (permalink / raw)
To: matthias.bgg
Cc: robh+dt, krzysztof.kozlowski+dt, nfraprado, kernel, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel,
AngeloGioacchino Del Regno
This SoC features two clusters composed of:
- 4x Cortex A53: 32KB I-cache, 2-way set associative,
32KB D-cache, 4-way set associative,
unified 1MB L2 cache, 16-way set associative;
- 4x Cortex A73: 64KB I-cache and 64KB D-cache, 4-way set associative,
unified 1MB L2 cache, 16-way set associative;
With that in mind, add the appropriate properties needed to specify the
caches information for this SoC, which will now be correctly exported
to sysfs.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 74 ++++++++++++++++++++++++
1 file changed, 74 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index a70b669c49ba..12f61cd20da5 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -336,6 +336,13 @@ cpu0: cpu@0 {
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cluster0_opp>;
dynamic-power-coefficient = <84>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_0>;
#cooling-cells = <2>;
mediatek,cci = <&cci>;
};
@@ -352,6 +359,13 @@ cpu1: cpu@1 {
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cluster0_opp>;
dynamic-power-coefficient = <84>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_0>;
#cooling-cells = <2>;
mediatek,cci = <&cci>;
};
@@ -368,6 +382,13 @@ cpu2: cpu@2 {
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cluster0_opp>;
dynamic-power-coefficient = <84>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_0>;
#cooling-cells = <2>;
mediatek,cci = <&cci>;
};
@@ -384,6 +405,13 @@ cpu3: cpu@3 {
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cluster0_opp>;
dynamic-power-coefficient = <84>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_0>;
#cooling-cells = <2>;
mediatek,cci = <&cci>;
};
@@ -400,6 +428,13 @@ cpu4: cpu@100 {
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cluster1_opp>;
dynamic-power-coefficient = <211>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_1>;
#cooling-cells = <2>;
mediatek,cci = <&cci>;
};
@@ -416,6 +451,13 @@ cpu5: cpu@101 {
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cluster1_opp>;
dynamic-power-coefficient = <211>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_1>;
#cooling-cells = <2>;
mediatek,cci = <&cci>;
};
@@ -432,6 +474,13 @@ cpu6: cpu@102 {
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cluster1_opp>;
dynamic-power-coefficient = <211>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_1>;
#cooling-cells = <2>;
mediatek,cci = <&cci>;
};
@@ -448,6 +497,13 @@ cpu7: cpu@103 {
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cluster1_opp>;
dynamic-power-coefficient = <211>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_1>;
#cooling-cells = <2>;
mediatek,cci = <&cci>;
};
@@ -481,6 +537,24 @@ CLUSTER_SLEEP1: cluster-sleep-1 {
min-residency-us = <1300>;
};
};
+
+ l2_0: l2-cache0 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <1048576>;
+ cache-line-size = <64>;
+ cache-sets = <1024>;
+ cache-unified;
+ };
+
+ l2_1: l2-cache1 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <1048576>;
+ cache-line-size = <64>;
+ cache-sets = <1024>;
+ cache-unified;
+ };
};
gpu_opp_table: opp-table-0 {
--
2.38.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH 4/5] arm64: dts: mt8183: Add complete CPU caches information
@ 2022-12-06 11:23 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 14+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-12-06 11:23 UTC (permalink / raw)
To: matthias.bgg
Cc: robh+dt, krzysztof.kozlowski+dt, nfraprado, kernel, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel,
AngeloGioacchino Del Regno
This SoC features two clusters composed of:
- 4x Cortex A53: 32KB I-cache, 2-way set associative,
32KB D-cache, 4-way set associative,
unified 1MB L2 cache, 16-way set associative;
- 4x Cortex A73: 64KB I-cache and 64KB D-cache, 4-way set associative,
unified 1MB L2 cache, 16-way set associative;
With that in mind, add the appropriate properties needed to specify the
caches information for this SoC, which will now be correctly exported
to sysfs.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 74 ++++++++++++++++++++++++
1 file changed, 74 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index a70b669c49ba..12f61cd20da5 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -336,6 +336,13 @@ cpu0: cpu@0 {
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cluster0_opp>;
dynamic-power-coefficient = <84>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_0>;
#cooling-cells = <2>;
mediatek,cci = <&cci>;
};
@@ -352,6 +359,13 @@ cpu1: cpu@1 {
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cluster0_opp>;
dynamic-power-coefficient = <84>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_0>;
#cooling-cells = <2>;
mediatek,cci = <&cci>;
};
@@ -368,6 +382,13 @@ cpu2: cpu@2 {
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cluster0_opp>;
dynamic-power-coefficient = <84>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_0>;
#cooling-cells = <2>;
mediatek,cci = <&cci>;
};
@@ -384,6 +405,13 @@ cpu3: cpu@3 {
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cluster0_opp>;
dynamic-power-coefficient = <84>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_0>;
#cooling-cells = <2>;
mediatek,cci = <&cci>;
};
@@ -400,6 +428,13 @@ cpu4: cpu@100 {
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cluster1_opp>;
dynamic-power-coefficient = <211>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_1>;
#cooling-cells = <2>;
mediatek,cci = <&cci>;
};
@@ -416,6 +451,13 @@ cpu5: cpu@101 {
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cluster1_opp>;
dynamic-power-coefficient = <211>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_1>;
#cooling-cells = <2>;
mediatek,cci = <&cci>;
};
@@ -432,6 +474,13 @@ cpu6: cpu@102 {
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cluster1_opp>;
dynamic-power-coefficient = <211>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_1>;
#cooling-cells = <2>;
mediatek,cci = <&cci>;
};
@@ -448,6 +497,13 @@ cpu7: cpu@103 {
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cluster1_opp>;
dynamic-power-coefficient = <211>;
+ i-cache-size = <65536>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <65536>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_1>;
#cooling-cells = <2>;
mediatek,cci = <&cci>;
};
@@ -481,6 +537,24 @@ CLUSTER_SLEEP1: cluster-sleep-1 {
min-residency-us = <1300>;
};
};
+
+ l2_0: l2-cache0 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <1048576>;
+ cache-line-size = <64>;
+ cache-sets = <1024>;
+ cache-unified;
+ };
+
+ l2_1: l2-cache1 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <1048576>;
+ cache-line-size = <64>;
+ cache-sets = <1024>;
+ cache-unified;
+ };
};
gpu_opp_table: opp-table-0 {
--
2.38.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 5/5] arm64: dts: mt6795: Add complete CPU caches information
2022-12-06 11:23 ` AngeloGioacchino Del Regno
@ 2022-12-06 11:23 ` AngeloGioacchino Del Regno
-1 siblings, 0 replies; 14+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-12-06 11:23 UTC (permalink / raw)
To: matthias.bgg
Cc: robh+dt, krzysztof.kozlowski+dt, nfraprado, kernel, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel,
AngeloGioacchino Del Regno
This SoC's AP subsystem has 8x Cortex-A53 CPUs, specifically,
four CPUs per cluster, with two CPU clusters.
Each CPU has:
- A 32KB I-cache, 2-way set associative;
- A 32KB D-cache, 4-way set associative.
Each cluster has a unified 1MB L2 cache, 16-way set associative.
With that in mind, add the appropriate properties needed to specify the
caches information for this SoC, which will now be correctly exported
to sysfs.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt6795.dtsi | 50 ++++++++++++++++++++++++
1 file changed, 50 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
index bb575837e4ce..b3fc76d837a9 100644
--- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
@@ -40,6 +40,12 @@ cpu1: cpu@1 {
enable-method = "psci";
reg = <0x001>;
cci-control-port = <&cci_control2>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
next-level-cache = <&l2_0>;
};
@@ -49,6 +55,12 @@ cpu2: cpu@2 {
enable-method = "psci";
reg = <0x002>;
cci-control-port = <&cci_control2>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
next-level-cache = <&l2_0>;
};
@@ -58,6 +70,12 @@ cpu3: cpu@3 {
enable-method = "psci";
reg = <0x003>;
cci-control-port = <&cci_control2>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
next-level-cache = <&l2_0>;
};
@@ -67,6 +85,12 @@ cpu4: cpu@100 {
enable-method = "psci";
reg = <0x100>;
cci-control-port = <&cci_control1>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
next-level-cache = <&l2_1>;
};
@@ -76,6 +100,12 @@ cpu5: cpu@101 {
enable-method = "psci";
reg = <0x101>;
cci-control-port = <&cci_control1>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
next-level-cache = <&l2_1>;
};
@@ -85,6 +115,12 @@ cpu6: cpu@102 {
enable-method = "psci";
reg = <0x102>;
cci-control-port = <&cci_control1>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
next-level-cache = <&l2_1>;
};
@@ -94,6 +130,12 @@ cpu7: cpu@103 {
enable-method = "psci";
reg = <0x103>;
cci-control-port = <&cci_control1>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
next-level-cache = <&l2_1>;
};
@@ -138,11 +180,19 @@ core3 {
l2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
+ cache-size = <1048576>;
+ cache-line-size = <64>;
+ cache-sets = <1024>;
+ cache-unified;
};
l2_1: l2-cache1 {
compatible = "cache";
cache-level = <2>;
+ cache-size = <1048576>;
+ cache-line-size = <64>;
+ cache-sets = <1024>;
+ cache-unified;
};
};
--
2.38.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH 5/5] arm64: dts: mt6795: Add complete CPU caches information
@ 2022-12-06 11:23 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 14+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-12-06 11:23 UTC (permalink / raw)
To: matthias.bgg
Cc: robh+dt, krzysztof.kozlowski+dt, nfraprado, kernel, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel,
AngeloGioacchino Del Regno
This SoC's AP subsystem has 8x Cortex-A53 CPUs, specifically,
four CPUs per cluster, with two CPU clusters.
Each CPU has:
- A 32KB I-cache, 2-way set associative;
- A 32KB D-cache, 4-way set associative.
Each cluster has a unified 1MB L2 cache, 16-way set associative.
With that in mind, add the appropriate properties needed to specify the
caches information for this SoC, which will now be correctly exported
to sysfs.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt6795.dtsi | 50 ++++++++++++++++++++++++
1 file changed, 50 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
index bb575837e4ce..b3fc76d837a9 100644
--- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
@@ -40,6 +40,12 @@ cpu1: cpu@1 {
enable-method = "psci";
reg = <0x001>;
cci-control-port = <&cci_control2>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
next-level-cache = <&l2_0>;
};
@@ -49,6 +55,12 @@ cpu2: cpu@2 {
enable-method = "psci";
reg = <0x002>;
cci-control-port = <&cci_control2>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
next-level-cache = <&l2_0>;
};
@@ -58,6 +70,12 @@ cpu3: cpu@3 {
enable-method = "psci";
reg = <0x003>;
cci-control-port = <&cci_control2>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
next-level-cache = <&l2_0>;
};
@@ -67,6 +85,12 @@ cpu4: cpu@100 {
enable-method = "psci";
reg = <0x100>;
cci-control-port = <&cci_control1>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
next-level-cache = <&l2_1>;
};
@@ -76,6 +100,12 @@ cpu5: cpu@101 {
enable-method = "psci";
reg = <0x101>;
cci-control-port = <&cci_control1>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
next-level-cache = <&l2_1>;
};
@@ -85,6 +115,12 @@ cpu6: cpu@102 {
enable-method = "psci";
reg = <0x102>;
cci-control-port = <&cci_control1>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
next-level-cache = <&l2_1>;
};
@@ -94,6 +130,12 @@ cpu7: cpu@103 {
enable-method = "psci";
reg = <0x103>;
cci-control-port = <&cci_control1>;
+ i-cache-size = <32768>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <32768>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
next-level-cache = <&l2_1>;
};
@@ -138,11 +180,19 @@ core3 {
l2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
+ cache-size = <1048576>;
+ cache-line-size = <64>;
+ cache-sets = <1024>;
+ cache-unified;
};
l2_1: l2-cache1 {
compatible = "cache";
cache-level = <2>;
+ cache-size = <1048576>;
+ cache-line-size = <64>;
+ cache-sets = <1024>;
+ cache-unified;
};
};
--
2.38.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH 0/5] Add CPU caches information for some MediaTek SoCs
2022-12-06 11:23 ` AngeloGioacchino Del Regno
@ 2022-12-16 11:53 ` Matthias Brugger
-1 siblings, 0 replies; 14+ messages in thread
From: Matthias Brugger @ 2022-12-16 11:53 UTC (permalink / raw)
To: AngeloGioacchino Del Regno
Cc: robh+dt, krzysztof.kozlowski+dt, nfraprado, kernel, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel
On 06/12/2022 12:23, AngeloGioacchino Del Regno wrote:
> In devicetrees for MediaTek SoCs the CPU caches information, if
> present, is incomplete as it misses cache size, cache line size
> and number of cache sets which, in turn, will also prevent any
> cache associativity calculation.
>
> For all of the SoCs that I know and/or I have information for,
> I've added the right information for I/D, L2 and L3 where present.
> This will also make the cacheinfo driver to correctly export the
> CPU cache information to sysfs.
>
Whole series applied, thanks!
> AngeloGioacchino Del Regno (5):
> arm64: dts: mt8195: Add complete CPU caches information
> arm64: dts: mt8192: Add complete CPU caches information
> arm64: dts: mt8186: Add complete CPU caches information
> arm64: dts: mt8183: Add complete CPU caches information
> arm64: dts: mt6795: Add complete CPU caches information
>
> arch/arm64/boot/dts/mediatek/mt6795.dtsi | 50 ++++++++++++++++
> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 74 ++++++++++++++++++++++++
> arch/arm64/boot/dts/mediatek/mt8186.dtsi | 58 +++++++++++++++++++
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 58 +++++++++++++++++++
> arch/arm64/boot/dts/mediatek/mt8195.dtsi | 58 +++++++++++++++++++
> 5 files changed, 298 insertions(+)
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 0/5] Add CPU caches information for some MediaTek SoCs
@ 2022-12-16 11:53 ` Matthias Brugger
0 siblings, 0 replies; 14+ messages in thread
From: Matthias Brugger @ 2022-12-16 11:53 UTC (permalink / raw)
To: AngeloGioacchino Del Regno
Cc: robh+dt, krzysztof.kozlowski+dt, nfraprado, kernel, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel
On 06/12/2022 12:23, AngeloGioacchino Del Regno wrote:
> In devicetrees for MediaTek SoCs the CPU caches information, if
> present, is incomplete as it misses cache size, cache line size
> and number of cache sets which, in turn, will also prevent any
> cache associativity calculation.
>
> For all of the SoCs that I know and/or I have information for,
> I've added the right information for I/D, L2 and L3 where present.
> This will also make the cacheinfo driver to correctly export the
> CPU cache information to sysfs.
>
Whole series applied, thanks!
> AngeloGioacchino Del Regno (5):
> arm64: dts: mt8195: Add complete CPU caches information
> arm64: dts: mt8192: Add complete CPU caches information
> arm64: dts: mt8186: Add complete CPU caches information
> arm64: dts: mt8183: Add complete CPU caches information
> arm64: dts: mt6795: Add complete CPU caches information
>
> arch/arm64/boot/dts/mediatek/mt6795.dtsi | 50 ++++++++++++++++
> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 74 ++++++++++++++++++++++++
> arch/arm64/boot/dts/mediatek/mt8186.dtsi | 58 +++++++++++++++++++
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 58 +++++++++++++++++++
> arch/arm64/boot/dts/mediatek/mt8195.dtsi | 58 +++++++++++++++++++
> 5 files changed, 298 insertions(+)
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 14+ messages in thread