All of lore.kernel.org
 help / color / mirror / Atom feed
From: Harsh Prateek Bora <harshpb@linux.ibm.com>
To: "Philippe Mathieu-Daudé" <philmd@linaro.org>,
	qemu-devel@nongnu.org, "Nicholas Piggin" <npiggin@gmail.com>
Cc: Daniel Henrique Barboza <danielhb413@gmail.com>,
	Richard Henderson <richard.henderson@linaro.org>,
	qemu-ppc@nongnu.org
Subject: Re: [PATCH v2 06/15] target/ppc: Ensure powerpc_checkstop() is only called under TCG
Date: Tue, 28 Jan 2025 12:19:14 +0530	[thread overview]
Message-ID: <083eba50-9f79-4cf4-b5bb-ff9b3eb78322@linux.ibm.com> (raw)
In-Reply-To: <fe541a6b-ab7b-4d61-aad2-2674b1fd3c9b@linux.ibm.com>



On 1/28/25 12:13, Harsh Prateek Bora wrote:
> 
> 
> On 1/27/25 15:56, Philippe Mathieu-Daudé wrote:
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>> ---
>>   target/ppc/excp_helper.c | 6 ++----
>>   1 file changed, 2 insertions(+), 4 deletions(-)
>>
>> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
>> index 8956466db1d..b08cd53688c 100644
>> --- a/target/ppc/excp_helper.c
>> +++ b/target/ppc/excp_helper.c
>> @@ -19,6 +19,7 @@
>>   #include "qemu/osdep.h"
>>   #include "qemu/main-loop.h"
>>   #include "qemu/log.h"
>> +#include "system/tcg.h"
>>   #include "system/system.h"
>>   #include "system/runstate.h"
>>   #include "cpu.h"
>> @@ -30,7 +31,6 @@
>>   #include "trace.h"
>>   #ifdef CONFIG_TCG
>> -#include "system/tcg.h"
>>   #include "exec/helper-proto.h"
>>   #include "exec/cpu_ldst.h"
>>   #endif
>> @@ -443,13 +443,11 @@ void helper_attn(CPUPPCState *env)
>>   static void powerpc_mcheck_checkstop(CPUPPCState *env)
>>   {
>>       /* KVM guests always have MSR[ME] enabled */
>> -#ifdef CONFIG_TCG
>>       if (FIELD_EX64(env->msr, MSR, ME)) {
>>           return;
>>       }
>> -
>> +    assert(tcg_enabled());
> 
> Shouldn't this be a no-op if not TCG ?
> 
> Nick, please advise ?
> 

Also, patch title needs update - it's powerpc_mcheck_checkstop.

> regards,
> Harsh
>>       powerpc_checkstop(env, "machine check with MSR[ME]=0");
>> -#endif
>>   }
>>   static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
> 


  reply	other threads:[~2025-01-28  6:49 UTC|newest]

Thread overview: 39+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-01-27 10:26 [PATCH v2 00/15] target/ppc: Move TCG code from excp_helper.c to tcg-excp_helper.c Philippe Mathieu-Daudé
2025-01-27 10:26 ` [PATCH v2 01/15] hw/ppc/spapr: Restrict CONFER hypercall to TCG Philippe Mathieu-Daudé
2025-01-28  4:59   ` Harsh Prateek Bora
2025-01-27 10:26 ` [PATCH v2 02/15] hw/ppc/spapr: Restrict part of PAGE_INIT " Philippe Mathieu-Daudé
2025-01-28  5:02   ` Harsh Prateek Bora
2025-01-27 10:26 ` [PATCH v2 03/15] target/ppc: Make ppc_ldl_code() declaration public Philippe Mathieu-Daudé
2025-01-28  5:47   ` Harsh Prateek Bora
2025-01-27 10:26 ` [PATCH v2 04/15] target/ppc: Move TCG specific exception handlers to tcg-excp_helper.c Philippe Mathieu-Daudé
2025-01-28  6:07   ` Harsh Prateek Bora
2025-01-28 12:41     ` BALATON Zoltan
2025-01-28 13:44       ` Philippe Mathieu-Daudé
2025-01-27 10:26 ` [PATCH v2 05/15] target/ppc: Move ppc_ldl_code() " Philippe Mathieu-Daudé
2025-01-28  6:13   ` Harsh Prateek Bora
2025-01-28  7:41     ` Philippe Mathieu-Daudé
2025-01-27 10:26 ` [PATCH v2 06/15] target/ppc: Ensure powerpc_checkstop() is only called under TCG Philippe Mathieu-Daudé
2025-01-28  6:43   ` Harsh Prateek Bora
2025-01-28  6:49     ` Harsh Prateek Bora [this message]
2025-02-27  0:46     ` Nicholas Piggin
2025-01-27 10:26 ` [PATCH v2 07/15] target/ppc: Restrict powerpc_checkstop() to TCG Philippe Mathieu-Daudé
2025-01-28  9:31   ` Harsh Prateek Bora
2025-01-27 10:26 ` [PATCH v2 08/15] target/ppc: Remove raise_exception_ra() Philippe Mathieu-Daudé
2025-01-28  9:46   ` Harsh Prateek Bora
2025-01-28 10:08     ` Philippe Mathieu-Daudé
2025-01-27 10:26 ` [PATCH v2 09/15] target/ppc: Restrict exception helpers to TCG Philippe Mathieu-Daudé
2025-01-28  9:59   ` Harsh Prateek Bora
2025-01-28 10:03     ` Philippe Mathieu-Daudé
2025-01-27 10:26 ` [PATCH v2 10/15] target/ppc: Restrict ppc_tcg_hv_emu() " Philippe Mathieu-Daudé
2025-01-28 11:05   ` Harsh Prateek Bora
2025-01-27 10:26 ` [PATCH v2 11/15] target/ppc: Restrict various common helpers " Philippe Mathieu-Daudé
2025-01-29  5:43   ` Harsh Prateek Bora
2025-01-27 10:26 ` [PATCH v2 12/15] target/ppc: Fix style in excp_helper.c Philippe Mathieu-Daudé
2025-01-29  5:54   ` Harsh Prateek Bora
2025-01-27 10:26 ` [PATCH v2 13/15] target/ppc: Make powerpc_excp() prototype public Philippe Mathieu-Daudé
2025-01-29  5:58   ` Harsh Prateek Bora
2025-01-27 10:26 ` [PATCH v2 14/15] target/ppc: Restrict ATTN / SCV / PMINSN helpers to TCG Philippe Mathieu-Daudé
2025-01-29  6:03   ` Harsh Prateek Bora
2025-01-27 10:26 ` [PATCH v2 15/15] target/ppc: Restrict various system " Philippe Mathieu-Daudé
2025-03-11  6:22 ` [PATCH v2 00/15] target/ppc: Move TCG code from excp_helper.c to tcg-excp_helper.c Nicholas Piggin
2025-03-11  7:15   ` Philippe Mathieu-Daudé

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=083eba50-9f79-4cf4-b5bb-ff9b3eb78322@linux.ibm.com \
    --to=harshpb@linux.ibm.com \
    --cc=danielhb413@gmail.com \
    --cc=npiggin@gmail.com \
    --cc=philmd@linaro.org \
    --cc=qemu-devel@nongnu.org \
    --cc=qemu-ppc@nongnu.org \
    --cc=richard.henderson@linaro.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.