From: Nicola Vetrini <nicola.vetrini@bugseng.com>
To: Julien Grall <julien@xen.org>,
Stefano Stabellini <sstabellini@kernel.org>,
Bertrand Marquis <bertrand.marquis@arm.com>,
Michal Orzel <michal.orzel@amd.com>
Cc: sstabellini@kernel.org, michal.orzel@amd.com,
xenia.ragiadakou@amd.com, ayan.kumar.halder@amd.com,
consulting@bugseng.com, andrew.cooper3@citrix.com,
roger.pau@citrix.com, bertrand.marquis@arm.com, julien@xen.org,
Volodymyr Babchuk <Volodymyr_Babchuk@epam.com>,
xen-devel@lists.xenproject.org
Subject: Re: [XEN PATCH 02/10] xen/arm: address some violations of MISRA C Rule 20.7
Date: Mon, 04 Mar 2024 19:17:52 +0100 [thread overview]
Message-ID: <0aae1c64587cfbc67e81a20b36dd5056@bugseng.com> (raw)
In-Reply-To: <7c54b08875406e5b3a61325af124ae7f@bugseng.com>
Hi,
as the maintainers of this subsystem, would you prefer Jan's version or
the one in the patch?
Both are fine w.r.t MISRA Rule 20.7 because the macro arguments
themselves are parenthesized.
>>> --- a/xen/arch/arm/include/asm/vgic-emul.h
>>> +++ b/xen/arch/arm/include/asm/vgic-emul.h
>>> @@ -6,11 +6,11 @@
>>> * a range of registers
>>> */
>>>
>>> -#define VREG32(reg) reg ... reg + 3
>>> -#define VREG64(reg) reg ... reg + 7
>>> +#define VREG32(reg) (reg) ... (reg) + 3
>>> +#define VREG64(reg) (reg) ... (reg) + 7
>>
>> #define VREG32(reg) (reg) ... ((reg) + 3)
>> #define VREG64(reg) (reg) ... ((reg) + 7)
>>
>> ?
>>
>
> The outer parentheses are not required, but I can add them if the
> maintainers share your view.
--
Nicola Vetrini, BSc
Software Engineer, BUGSENG srl (https://bugseng.com)
next prev parent reply other threads:[~2024-03-04 18:18 UTC|newest]
Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-29 15:27 [XEN PATCH 00/10] address some violations of MISRA C Rule 20.7 Nicola Vetrini
2024-02-29 15:27 ` [XEN PATCH 01/10] xen/include: address " Nicola Vetrini
2024-02-29 16:10 ` Andrew Cooper
2024-02-29 16:21 ` Nicola Vetrini
2024-02-29 16:47 ` Andrew Cooper
2024-02-29 16:53 ` Nicola Vetrini
2024-02-29 16:25 ` Jan Beulich
2024-02-29 16:40 ` Nicola Vetrini
2024-02-29 16:47 ` Jan Beulich
2024-02-29 15:27 ` [XEN PATCH 02/10] xen/arm: address some " Nicola Vetrini
2024-02-29 16:34 ` Jan Beulich
2024-03-01 15:30 ` Nicola Vetrini
2024-03-04 18:17 ` Nicola Vetrini [this message]
2024-03-05 1:43 ` Stefano Stabellini
2024-03-05 10:25 ` Nicola Vetrini
2024-02-29 15:27 ` [XEN PATCH 03/10] x86: " Nicola Vetrini
2024-02-29 16:37 ` Jan Beulich
2024-02-29 16:45 ` Nicola Vetrini
2024-02-29 17:05 ` Jan Beulich
2024-03-05 10:26 ` Nicola Vetrini
2024-02-29 15:27 ` [XEN PATCH 04/10] xen/public: address " Nicola Vetrini
2024-02-29 16:40 ` Jan Beulich
2024-02-29 16:49 ` Nicola Vetrini
2024-02-29 22:49 ` Stefano Stabellini
2024-03-05 10:21 ` Nicola Vetrini
2024-03-05 10:26 ` Jan Beulich
2024-03-05 16:17 ` Nicola Vetrini
2024-03-01 7:54 ` Jan Beulich
2024-02-29 15:27 ` [XEN PATCH 05/10] xen/perfc: " Nicola Vetrini
2024-02-29 16:42 ` Jan Beulich
2024-02-29 16:50 ` Nicola Vetrini
2024-02-29 15:27 ` [XEN PATCH 06/10] arm/smmu: address some " Nicola Vetrini
2024-02-29 22:53 ` Stefano Stabellini
2024-03-05 10:23 ` Nicola Vetrini
2024-03-07 1:31 ` Stefano Stabellini
2024-02-29 15:27 ` [XEN PATCH 07/10] xen/arm: smmuv3: address " Nicola Vetrini
2024-02-29 22:54 ` Stefano Stabellini
2024-02-29 15:28 ` [XEN PATCH 08/10] xen/errno: " Nicola Vetrini
2024-02-29 22:55 ` Stefano Stabellini
2024-03-01 8:10 ` Nicola Vetrini
2024-03-04 9:39 ` Jan Beulich
2024-02-29 15:28 ` [XEN PATCH 09/10] xen/include: tasklet: " Nicola Vetrini
2024-02-29 22:56 ` Stefano Stabellini
2024-02-29 15:28 ` [XEN PATCH 10/10] xen/keyhandler: " Nicola Vetrini
2024-02-29 22:57 ` Stefano Stabellini
2024-03-01 8:00 ` Jan Beulich
2024-03-02 1:37 ` Stefano Stabellini
2024-03-04 8:00 ` Jan Beulich
2024-03-05 2:03 ` Stefano Stabellini
2024-03-05 7:00 ` Jan Beulich
2024-03-07 1:39 ` Stefano Stabellini
2024-03-07 7:42 ` Jan Beulich
2024-03-07 13:52 ` Nicola Vetrini
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