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From: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
To: Andy Gross <agross@kernel.org>,
	Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
	Douglas Anderson <dianders@chromium.org>,
	Stephen Boyd <swboyd@chromium.org>
Subject: Re: [PATCHv5 0/2] soc: qcom: llcc: Support chipsets that can write to llcc regs
Date: Mon, 26 Oct 2020 18:03:31 +0530	[thread overview]
Message-ID: <0e203a18049712173818f404b4a32163@codeaurora.org> (raw)
In-Reply-To: <cover.1600151951.git.saiprakash.ranjan@codeaurora.org>

Hi Bjorn,

On 2020-09-15 12:25, Sai Prakash Ranjan wrote:
> Older chipsets may not be allowed to configure certain LLCC registers
> as that is handled by the secure side software. However, this is not
> the case for newer chipsets and they must configure these registers
> according to the contents of the SCT table, while keeping in mind that
> older targets may not have these capabilities. So add support to allow
> such configuration of registers to enable capacity based allocation
> and power collapse retention for capable chipsets.
> 
> Reason for choosing capacity based allocation rather than the default
> way based allocation is because capacity based allocation allows more
> finer grain partition and provides more flexibility in configuration.
> As for the retention through power collapse, it has an advantage where
> the cache hits are more when we wake up from power collapse although
> it does burn more power but the exact power numbers are not known at
> the moment.
> 


Gentle ping!

Thanks,
Sai

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a 
member
of Code Aurora Forum, hosted by The Linux Foundation

WARNING: multiple messages have this Message-ID (diff)
From: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
To: Andy Gross <agross@kernel.org>,
	Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: linux-arm-msm@vger.kernel.org, Stephen Boyd <swboyd@chromium.org>,
	linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	Douglas Anderson <dianders@chromium.org>
Subject: Re: [PATCHv5 0/2] soc: qcom: llcc: Support chipsets that can write to llcc regs
Date: Mon, 26 Oct 2020 18:03:31 +0530	[thread overview]
Message-ID: <0e203a18049712173818f404b4a32163@codeaurora.org> (raw)
In-Reply-To: <cover.1600151951.git.saiprakash.ranjan@codeaurora.org>

Hi Bjorn,

On 2020-09-15 12:25, Sai Prakash Ranjan wrote:
> Older chipsets may not be allowed to configure certain LLCC registers
> as that is handled by the secure side software. However, this is not
> the case for newer chipsets and they must configure these registers
> according to the contents of the SCT table, while keeping in mind that
> older targets may not have these capabilities. So add support to allow
> such configuration of registers to enable capacity based allocation
> and power collapse retention for capable chipsets.
> 
> Reason for choosing capacity based allocation rather than the default
> way based allocation is because capacity based allocation allows more
> finer grain partition and provides more flexibility in configuration.
> As for the retention through power collapse, it has an advantage where
> the cache hits are more when we wake up from power collapse although
> it does burn more power but the exact power numbers are not known at
> the moment.
> 


Gentle ping!

Thanks,
Sai

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a 
member
of Code Aurora Forum, hosted by The Linux Foundation

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  parent reply	other threads:[~2020-10-26 12:33 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-09-15  6:55 [PATCHv5 0/2] soc: qcom: llcc: Support chipsets that can write to llcc regs Sai Prakash Ranjan
2020-09-15  6:55 ` Sai Prakash Ranjan
2020-09-15  6:55 ` [PATCHv5 1/2] soc: qcom: llcc: Move llcc configuration to its own function Sai Prakash Ranjan
2020-09-15  6:55   ` Sai Prakash Ranjan
2020-09-15 16:01   ` Bjorn Andersson
2020-09-15 16:01     ` Bjorn Andersson
2020-09-15 16:10   ` Stephen Boyd
2020-09-15 16:10     ` Stephen Boyd
2020-09-15  6:55 ` [PATCHv5 2/2] soc: qcom: llcc: Support chipsets that can write to llcc Sai Prakash Ranjan
2020-09-15  6:55   ` Sai Prakash Ranjan
2020-09-15 16:11   ` Stephen Boyd
2020-09-15 16:11     ` Stephen Boyd
2020-10-26 12:33 ` Sai Prakash Ranjan [this message]
2020-10-26 12:33   ` [PATCHv5 0/2] soc: qcom: llcc: Support chipsets that can write to llcc regs Sai Prakash Ranjan

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