* [PATCH 01/18] drm/amd/pm: add new vcn enable function pointer
2024-10-02 4:36 [PATCH 00/18] Separating vcn power management by instance boyuan.zhang
@ 2024-10-02 4:36 ` boyuan.zhang
2024-10-02 17:10 ` Alex Deucher
2024-10-02 4:36 ` [PATCH 02/18] drm/amd/pm: enable vcn by instance for smu v13 boyuan.zhang
` (16 subsequent siblings)
17 siblings, 1 reply; 29+ messages in thread
From: boyuan.zhang @ 2024-10-02 4:36 UTC (permalink / raw)
To: amd-gfx, leo.liu, christian.koenig, alexander.deucher,
sunil.khatri
Cc: Boyuan Zhang
From: Boyuan Zhang <boyuan.zhang@amd.com>
The new function dpm_set_vcn_enable_instance() will be used to enable
or disable vcn engine dynamic power for the given vcn instance.
The original function dpm_set_vcn_enable() will still be used to enable
or disable vcn engine dynamic power for all vcn instances as before.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
---
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
index 727da0c37e06..f88241cdf9b9 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
@@ -737,10 +737,16 @@ struct pptable_funcs {
/**
* @dpm_set_vcn_enable: Enable/disable VCN engine dynamic power
- * management.
+ * management for all instance.
*/
int (*dpm_set_vcn_enable)(struct smu_context *smu, bool enable);
+ /**
+ * @dpm_set_vcn_enable_instance: Enable/disable VCN engine dynamic power
+ * management for given instance.
+ */
+ int (*dpm_set_vcn_enable_instance)(struct smu_context *smu, bool enable, int inst);
+
/**
* @dpm_set_jpeg_enable: Enable/disable JPEG engine dynamic power
* management.
--
2.34.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH 01/18] drm/amd/pm: add new vcn enable function pointer
2024-10-02 4:36 ` [PATCH 01/18] drm/amd/pm: add new vcn enable function pointer boyuan.zhang
@ 2024-10-02 17:10 ` Alex Deucher
2024-10-04 18:38 ` Boyuan Zhang
0 siblings, 1 reply; 29+ messages in thread
From: Alex Deucher @ 2024-10-02 17:10 UTC (permalink / raw)
To: boyuan.zhang
Cc: amd-gfx, leo.liu, christian.koenig, alexander.deucher,
sunil.khatri
On Wed, Oct 2, 2024 at 12:38 AM <boyuan.zhang@amd.com> wrote:
>
> From: Boyuan Zhang <boyuan.zhang@amd.com>
>
> The new function dpm_set_vcn_enable_instance() will be used to enable
> or disable vcn engine dynamic power for the given vcn instance.
>
> The original function dpm_set_vcn_enable() will still be used to enable
> or disable vcn engine dynamic power for all vcn instances as before.
>
> Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
> ---
> drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 8 +++++++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
> index 727da0c37e06..f88241cdf9b9 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
> +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
> @@ -737,10 +737,16 @@ struct pptable_funcs {
>
> /**
> * @dpm_set_vcn_enable: Enable/disable VCN engine dynamic power
> - * management.
> + * management for all instance.
> */
> int (*dpm_set_vcn_enable)(struct smu_context *smu, bool enable);
Wouldn't it be cleaner to just add an instance parameter to the
existing function?
Alex
>
> + /**
> + * @dpm_set_vcn_enable_instance: Enable/disable VCN engine dynamic power
> + * management for given instance.
> + */
> + int (*dpm_set_vcn_enable_instance)(struct smu_context *smu, bool enable, int inst);
> +
> /**
> * @dpm_set_jpeg_enable: Enable/disable JPEG engine dynamic power
> * management.
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH 01/18] drm/amd/pm: add new vcn enable function pointer
2024-10-02 17:10 ` Alex Deucher
@ 2024-10-04 18:38 ` Boyuan Zhang
0 siblings, 0 replies; 29+ messages in thread
From: Boyuan Zhang @ 2024-10-04 18:38 UTC (permalink / raw)
To: Alex Deucher
Cc: amd-gfx, leo.liu, christian.koenig, alexander.deucher,
sunil.khatri
On 2024-10-02 13:10, Alex Deucher wrote:
> On Wed, Oct 2, 2024 at 12:38 AM <boyuan.zhang@amd.com> wrote:
>> From: Boyuan Zhang <boyuan.zhang@amd.com>
>>
>> The new function dpm_set_vcn_enable_instance() will be used to enable
>> or disable vcn engine dynamic power for the given vcn instance.
>>
>> The original function dpm_set_vcn_enable() will still be used to enable
>> or disable vcn engine dynamic power for all vcn instances as before.
>>
>> Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
>> ---
>> drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 8 +++++++-
>> 1 file changed, 7 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
>> index 727da0c37e06..f88241cdf9b9 100644
>> --- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
>> +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
>> @@ -737,10 +737,16 @@ struct pptable_funcs {
>>
>> /**
>> * @dpm_set_vcn_enable: Enable/disable VCN engine dynamic power
>> - * management.
>> + * management for all instance.
>> */
>> int (*dpm_set_vcn_enable)(struct smu_context *smu, bool enable);
> Wouldn't it be cleaner to just add an instance parameter to the
> existing function?
>
> Alex
Right, it's much cleaner to use existing function.
Removed all duplicated functions and added instance parameter to
existing functions instead. Please check the new v2 patch set.
Regards,
Boyuan
>
>
>> + /**
>> + * @dpm_set_vcn_enable_instance: Enable/disable VCN engine dynamic power
>> + * management for given instance.
>> + */
>> + int (*dpm_set_vcn_enable_instance)(struct smu_context *smu, bool enable, int inst);
>> +
>> /**
>> * @dpm_set_jpeg_enable: Enable/disable JPEG engine dynamic power
>> * management.
>> --
>> 2.34.1
>>
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH 02/18] drm/amd/pm: enable vcn by instance for smu v13
2024-10-02 4:36 [PATCH 00/18] Separating vcn power management by instance boyuan.zhang
2024-10-02 4:36 ` [PATCH 01/18] drm/amd/pm: add new vcn enable function pointer boyuan.zhang
@ 2024-10-02 4:36 ` boyuan.zhang
2024-10-02 4:36 ` [PATCH 03/18] drm/amd/pm: enable vcn by instance for smu v14 boyuan.zhang
` (15 subsequent siblings)
17 siblings, 0 replies; 29+ messages in thread
From: boyuan.zhang @ 2024-10-02 4:36 UTC (permalink / raw)
To: amd-gfx, leo.liu, christian.koenig, alexander.deucher,
sunil.khatri
Cc: Boyuan Zhang
From: Boyuan Zhang <boyuan.zhang@amd.com>
For smu v13, set vcn enable or disable by the given instance instead of
setting it for all vcn instances.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
---
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h | 5 +++--
.../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 21 ++++++++-----------
.../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 2 +-
.../drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c | 2 +-
.../drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 2 +-
5 files changed, 15 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
index e58220a7ee2f..7b4761ad1902 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
@@ -254,8 +254,9 @@ int smu_v13_0_gfx_ulv_control(struct smu_context *smu,
int smu_v13_0_wait_for_event(struct smu_context *smu, enum smu_event_type event,
uint64_t event_arg);
-int smu_v13_0_set_vcn_enable(struct smu_context *smu,
- bool enable);
+int smu_v13_0_set_vcn_enable_instance(struct smu_context *smu,
+ bool enable,
+ int inst);
int smu_v13_0_set_jpeg_enable(struct smu_context *smu,
bool enable);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index e17466cc1952..d87a1e288b0a 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -2087,22 +2087,19 @@ int smu_v13_0_get_current_pcie_link_speed(struct smu_context *smu)
return link_speed[speed_level];
}
-int smu_v13_0_set_vcn_enable(struct smu_context *smu,
- bool enable)
+int smu_v13_0_set_vcn_enable_instance(struct smu_context *smu,
+ bool enable,
+ int inst)
{
struct amdgpu_device *adev = smu->adev;
- int i, ret = 0;
+ int ret = 0;
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return ret;
- ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
- SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn,
- i << 16U, NULL);
- if (ret)
- return ret;
- }
+ ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
+ SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn,
+ inst << 16U, NULL);
return ret;
}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index 866dc77d1005..94a23b330d5e 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -3028,7 +3028,7 @@ static const struct pptable_funcs smu_v13_0_0_ppt_funcs = {
.system_features_control = smu_v13_0_0_system_features_control,
.set_allowed_mask = smu_v13_0_set_allowed_mask,
.get_enabled_mask = smu_cmn_get_enabled_mask,
- .dpm_set_vcn_enable = smu_v13_0_set_vcn_enable,
+ .dpm_set_vcn_enable_instance = smu_v13_0_set_vcn_enable_instance,
.dpm_set_jpeg_enable = smu_v13_0_set_jpeg_enable,
.get_dpm_ultimate_freq = smu_v13_0_0_get_dpm_ultimate_freq,
.get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
index b081ae3e8f43..18d14f96b506 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c
@@ -1099,7 +1099,7 @@ static const struct pptable_funcs smu_v13_0_4_ppt_funcs = {
.system_features_control = smu_v13_0_4_system_features_control,
.send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
.send_smc_msg = smu_cmn_send_smc_msg,
- .dpm_set_vcn_enable = smu_v13_0_set_vcn_enable,
+ .dpm_set_vcn_enable_instance = smu_v13_0_set_vcn_enable_instance,
.dpm_set_jpeg_enable = smu_v13_0_set_jpeg_enable,
.set_default_dpm_table = smu_v13_0_set_default_dpm_tables,
.read_sensor = smu_v13_0_4_read_sensor,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
index f7d7cae16d9b..416ba5efbf1d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
@@ -2607,7 +2607,7 @@ static const struct pptable_funcs smu_v13_0_7_ppt_funcs = {
.system_features_control = smu_v13_0_system_features_control,
.set_allowed_mask = smu_v13_0_set_allowed_mask,
.get_enabled_mask = smu_cmn_get_enabled_mask,
- .dpm_set_vcn_enable = smu_v13_0_set_vcn_enable,
+ .dpm_set_vcn_enable_instance = smu_v13_0_set_vcn_enable_instance,
.dpm_set_jpeg_enable = smu_v13_0_set_jpeg_enable,
.init_pptable_microcode = smu_v13_0_init_pptable_microcode,
.populate_umd_state_clk = smu_v13_0_7_populate_umd_state_clk,
--
2.34.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH 03/18] drm/amd/pm: enable vcn by instance for smu v14
2024-10-02 4:36 [PATCH 00/18] Separating vcn power management by instance boyuan.zhang
2024-10-02 4:36 ` [PATCH 01/18] drm/amd/pm: add new vcn enable function pointer boyuan.zhang
2024-10-02 4:36 ` [PATCH 02/18] drm/amd/pm: enable vcn by instance for smu v13 boyuan.zhang
@ 2024-10-02 4:36 ` boyuan.zhang
2024-10-02 4:36 ` [PATCH 04/18] drm/amd/pm: enable vcn by instance for smu 11 boyuan.zhang
` (14 subsequent siblings)
17 siblings, 0 replies; 29+ messages in thread
From: boyuan.zhang @ 2024-10-02 4:36 UTC (permalink / raw)
To: amd-gfx, leo.liu, christian.koenig, alexander.deucher,
sunil.khatri
Cc: Boyuan Zhang
From: Boyuan Zhang <boyuan.zhang@amd.com>
For smu v14, set vcn enable or disable by the given instance instead of
setting it for all vcn instances.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
---
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h | 5 ++-
.../gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c | 40 +++++++++----------
.../drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c | 2 +-
.../drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c | 2 +-
4 files changed, 23 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h
index 46b456590a08..7d697f585443 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h
@@ -209,8 +209,9 @@ int smu_v14_0_gfx_ulv_control(struct smu_context *smu,
int smu_v14_0_wait_for_event(struct smu_context *smu, enum smu_event_type event,
uint64_t event_arg);
-int smu_v14_0_set_vcn_enable(struct smu_context *smu,
- bool enable);
+int smu_v14_0_set_vcn_enable_instance(struct smu_context *smu,
+ bool enable,
+ int inst);
int smu_v14_0_set_jpeg_enable(struct smu_context *smu,
bool enable);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
index 865e916fc425..bb521d3bedf7 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
@@ -1491,33 +1491,29 @@ int smu_v14_0_set_single_dpm_table(struct smu_context *smu,
return 0;
}
-int smu_v14_0_set_vcn_enable(struct smu_context *smu,
- bool enable)
+int smu_v14_0_set_vcn_enable_instance(struct smu_context *smu,
+ bool enable,
+ int inst)
{
struct amdgpu_device *adev = smu->adev;
- int i, ret = 0;
+ int ret = 0;
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return ret;
- if (smu->is_apu) {
- if (i == 0)
- ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
- SMU_MSG_PowerUpVcn0 : SMU_MSG_PowerDownVcn0,
- i << 16U, NULL);
- else if (i == 1)
- ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
- SMU_MSG_PowerUpVcn1 : SMU_MSG_PowerDownVcn1,
- i << 16U, NULL);
- } else {
+ if (smu->is_apu) {
+ if (inst == 0)
ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
- SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn,
- i << 16U, NULL);
- }
-
- if (ret)
- return ret;
+ SMU_MSG_PowerUpVcn0 : SMU_MSG_PowerDownVcn0,
+ inst << 16U, NULL);
+ else if (inst == 1)
+ ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
+ SMU_MSG_PowerUpVcn1 : SMU_MSG_PowerDownVcn1,
+ inst << 16U, NULL);
+ } else {
+ ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
+ SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn,
+ inst << 16U, NULL);
}
return ret;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
index 8798ebfcea83..9e4fadb8024a 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c
@@ -1648,7 +1648,7 @@ static const struct pptable_funcs smu_v14_0_0_ppt_funcs = {
.system_features_control = smu_v14_0_0_system_features_control,
.send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
.send_smc_msg = smu_cmn_send_smc_msg,
- .dpm_set_vcn_enable = smu_v14_0_set_vcn_enable,
+ .dpm_set_vcn_enable_instance = smu_v14_0_set_vcn_enable_instance,
.dpm_set_jpeg_enable = smu_v14_0_set_jpeg_enable,
.set_default_dpm_table = smu_v14_0_set_default_dpm_tables,
.read_sensor = smu_v14_0_0_read_sensor,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
index ade3ee398e3d..00f1f1bc2652 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
@@ -2808,7 +2808,7 @@ static const struct pptable_funcs smu_v14_0_2_ppt_funcs = {
.system_features_control = smu_v14_0_system_features_control,
.set_allowed_mask = smu_v14_0_set_allowed_mask,
.get_enabled_mask = smu_cmn_get_enabled_mask,
- .dpm_set_vcn_enable = smu_v14_0_set_vcn_enable,
+ .dpm_set_vcn_enable_instance = smu_v14_0_set_vcn_enable_instance,
.dpm_set_jpeg_enable = smu_v14_0_set_jpeg_enable,
.get_dpm_ultimate_freq = smu_v14_0_2_get_dpm_ultimate_freq,
.get_vbios_bootup_values = smu_v14_0_get_vbios_bootup_values,
--
2.34.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH 04/18] drm/amd/pm: enable vcn by instance for smu 11
2024-10-02 4:36 [PATCH 00/18] Separating vcn power management by instance boyuan.zhang
` (2 preceding siblings ...)
2024-10-02 4:36 ` [PATCH 03/18] drm/amd/pm: enable vcn by instance for smu v14 boyuan.zhang
@ 2024-10-02 4:36 ` boyuan.zhang
2024-10-02 4:36 ` [PATCH 05/18] drm/amd/pm: set vcn enable by instance boyuan.zhang
` (13 subsequent siblings)
17 siblings, 0 replies; 29+ messages in thread
From: boyuan.zhang @ 2024-10-02 4:36 UTC (permalink / raw)
To: amd-gfx, leo.liu, christian.koenig, alexander.deucher,
sunil.khatri
Cc: Boyuan Zhang
From: Boyuan Zhang <boyuan.zhang@amd.com>
For sienna_cichlid, set vcn enable or disable by the given instance
instead of setting it for all vcn instances.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
---
.../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 24 ++++++++-----------
1 file changed, 10 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 3b29cb74c47b..8ecf49ae489c 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -1152,22 +1152,18 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
return 0;
}
-static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
+static int sienna_cichlid_dpm_set_vcn_enable_instance(struct smu_context *smu, bool enable, int inst)
{
struct amdgpu_device *adev = smu->adev;
- int i, ret = 0;
+ int ret = 0;
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
- /* vcn dpm on is a prerequisite for vcn power gate messages */
- if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
- ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
- SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn,
- 0x10000 * i, NULL);
- if (ret)
- return ret;
- }
+ if (adev->vcn.harvest_config & (1 << inst))
+ return ret;
+ /* vcn dpm on is a prerequisite for vcn power gate messages */
+ if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
+ ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
+ SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn,
+ 0x10000 * inst, NULL);
}
return ret;
@@ -3106,7 +3102,7 @@ static int sienna_cichlid_mode2_reset(struct smu_context *smu)
static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
.get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
.set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
- .dpm_set_vcn_enable = sienna_cichlid_dpm_set_vcn_enable,
+ .dpm_set_vcn_enable_instance = sienna_cichlid_dpm_set_vcn_enable_instance,
.dpm_set_jpeg_enable = sienna_cichlid_dpm_set_jpeg_enable,
.i2c_init = sienna_cichlid_i2c_control_init,
.i2c_fini = sienna_cichlid_i2c_control_fini,
--
2.34.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH 05/18] drm/amd/pm: set vcn enable by instance
2024-10-02 4:36 [PATCH 00/18] Separating vcn power management by instance boyuan.zhang
` (3 preceding siblings ...)
2024-10-02 4:36 ` [PATCH 04/18] drm/amd/pm: enable vcn by instance for smu 11 boyuan.zhang
@ 2024-10-02 4:36 ` boyuan.zhang
2024-10-02 11:19 ` Christian König
2024-10-02 4:36 ` [PATCH 06/18] drm/amd/pm: set powergating by smu " boyuan.zhang
` (12 subsequent siblings)
17 siblings, 1 reply; 29+ messages in thread
From: boyuan.zhang @ 2024-10-02 4:36 UTC (permalink / raw)
To: amd-gfx, leo.liu, christian.koenig, alexander.deucher,
sunil.khatri
Cc: Boyuan Zhang
From: Boyuan Zhang <boyuan.zhang@amd.com>
The new function smu_dpm_set_vcn_enable_instance() will be used to enable
or disable vcn engine dynamic power for the given vcn instance only.
The original function smu_dpm_set_vcn_enable() will still be used to enable
or disable vcn engine dynamic power for all VCN instances as before.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 132 +++++++++++++++---
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 2 +-
2 files changed, 115 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 939e15b24f86..ddfed7189708 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -232,12 +232,15 @@ static bool is_vcn_enabled(struct amdgpu_device *adev)
return true;
}
-static int smu_dpm_set_vcn_enable(struct smu_context *smu,
- bool enable)
+static int smu_dpm_set_vcn_enable_instance(struct smu_context *smu,
+ bool enable,
+ int inst)
{
struct smu_power_context *smu_power = &smu->smu_power;
struct smu_power_gate *power_gate = &smu_power->power_gate;
+ struct amdgpu_device *adev = smu->adev;
int ret = 0;
+ bool single_inst = (adev->vcn.num_vcn_inst == 1);
/*
* don't poweron vcn/jpeg when they are skipped.
@@ -245,15 +248,33 @@ static int smu_dpm_set_vcn_enable(struct smu_context *smu,
if (!is_vcn_enabled(smu->adev))
return 0;
- if (!smu->ppt_funcs->dpm_set_vcn_enable)
+ if (!smu->ppt_funcs->dpm_set_vcn_enable_instance && !single_inst)
return 0;
- if (atomic_read(&power_gate->vcn_gated) ^ enable)
+ if (!smu->ppt_funcs->dpm_set_vcn_enable && single_inst)
return 0;
- ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable);
+ if (atomic_read(&power_gate->vcn_gated[inst]) ^ enable)
+ return 0;
+
+ if (single_inst)
+ ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable);
+ else
+ ret = smu->ppt_funcs->dpm_set_vcn_enable_instance(smu, enable, inst);
if (!ret)
- atomic_set(&power_gate->vcn_gated, !enable);
+ atomic_set(&power_gate->vcn_gated[inst], !enable);
+
+ return ret;
+}
+
+static int smu_dpm_set_vcn_enable(struct smu_context *smu,
+ bool enable)
+{
+ struct amdgpu_device *adev = smu->adev;
+ int ret = 0;
+
+ for (int i = 0; i < adev->vcn.num_vcn_inst; i++)
+ ret = smu_dpm_set_vcn_enable_instance(smu, enable, i);
return ret;
}
@@ -408,6 +429,81 @@ static int smu_dpm_set_power_gate(void *handle,
return ret;
}
+/**
+ * smu_dpm_set_power_gate_instance - power gate/ungate the specific IP block
+ * for the specific instance
+ *
+ * @handle: smu_context pointer
+ * @block_type: the IP block to power gate/ungate
+ * @gate: to power gate if true, ungate otherwise
+ * @inst: the instance to power gate/ungate
+ *
+ * This API uses no smu->mutex lock protection due to:
+ * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce).
+ * This is guarded to be race condition free by the caller.
+ * 2. Or get called on user setting request of power_dpm_force_performance_level.
+ * Under this case, the smu->mutex lock protection is already enforced on
+ * the parent API smu_force_performance_level of the call path.
+ */
+static int smu_dpm_set_power_gate_instance(void *handle,
+ uint32_t block_type,
+ bool gate,
+ int inst)
+{
+ struct smu_context *smu = handle;
+ int ret = 0;
+
+ if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) {
+ dev_WARN(smu->adev->dev,
+ "SMU uninitialized but power %s requested for %u!\n",
+ gate ? "gate" : "ungate", block_type);
+ return -EOPNOTSUPP;
+ }
+
+ switch (block_type) {
+ /*
+ * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses
+ * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept.
+ */
+ case AMD_IP_BLOCK_TYPE_UVD:
+ case AMD_IP_BLOCK_TYPE_VCN:
+ ret = smu_dpm_set_vcn_enable_instance(smu, !gate, inst);
+ if (ret)
+ dev_err(smu->adev->dev, "Failed to power %s VCN!\n",
+ gate ? "gate" : "ungate");
+ break;
+ case AMD_IP_BLOCK_TYPE_GFX:
+ ret = smu_gfx_off_control(smu, gate);
+ if (ret)
+ dev_err(smu->adev->dev, "Failed to %s gfxoff!\n",
+ gate ? "enable" : "disable");
+ break;
+ case AMD_IP_BLOCK_TYPE_SDMA:
+ ret = smu_powergate_sdma(smu, gate);
+ if (ret)
+ dev_err(smu->adev->dev, "Failed to power %s SDMA!\n",
+ gate ? "gate" : "ungate");
+ break;
+ case AMD_IP_BLOCK_TYPE_JPEG:
+ ret = smu_dpm_set_jpeg_enable(smu, !gate);
+ if (ret)
+ dev_err(smu->adev->dev, "Failed to power %s JPEG!\n",
+ gate ? "gate" : "ungate");
+ break;
+ case AMD_IP_BLOCK_TYPE_VPE:
+ ret = smu_dpm_set_vpe_enable(smu, !gate);
+ if (ret)
+ dev_err(smu->adev->dev, "Failed to power %s VPE!\n",
+ gate ? "gate" : "ungate");
+ break;
+ default:
+ dev_err(smu->adev->dev, "Unsupported block type!\n");
+ return -EINVAL;
+ }
+
+ return ret;
+}
+
/**
* smu_set_user_clk_dependencies - set user profile clock dependencies
*
@@ -774,19 +870,11 @@ static int smu_early_init(struct amdgpu_ip_block *ip_block)
static int smu_set_default_dpm_table(struct smu_context *smu)
{
struct amdgpu_device *adev = smu->adev;
- struct smu_power_context *smu_power = &smu->smu_power;
- struct smu_power_gate *power_gate = &smu_power->power_gate;
- int vcn_gate, jpeg_gate;
int ret = 0;
if (!smu->ppt_funcs->set_default_dpm_table)
return 0;
- if (adev->pg_flags & AMD_PG_SUPPORT_VCN)
- vcn_gate = atomic_read(&power_gate->vcn_gated);
- if (adev->pg_flags & AMD_PG_SUPPORT_JPEG)
- jpeg_gate = atomic_read(&power_gate->jpeg_gated);
-
if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
ret = smu_dpm_set_vcn_enable(smu, true);
if (ret)
@@ -805,10 +893,10 @@ static int smu_set_default_dpm_table(struct smu_context *smu)
"Failed to setup default dpm clock tables!\n");
if (adev->pg_flags & AMD_PG_SUPPORT_JPEG)
- smu_dpm_set_jpeg_enable(smu, !jpeg_gate);
+ smu_dpm_set_jpeg_enable(smu, false);
err_out:
if (adev->pg_flags & AMD_PG_SUPPORT_VCN)
- smu_dpm_set_vcn_enable(smu, !vcn_gate);
+ smu_dpm_set_vcn_enable(smu, false);
return ret;
}
@@ -1253,7 +1341,8 @@ static int smu_sw_init(struct amdgpu_ip_block *ip_block)
smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
- atomic_set(&smu->smu_power.power_gate.vcn_gated, 1);
+ for (int i = 0; i < adev->vcn.num_vcn_inst; i++)
+ atomic_set(&smu->smu_power.power_gate.vcn_gated[i], 1);
atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1);
atomic_set(&smu->smu_power.power_gate.vpe_gated, 1);
atomic_set(&smu->smu_power.power_gate.umsch_mm_gated, 1);
@@ -2932,6 +3021,7 @@ static int smu_read_sensor(void *handle,
int *size_arg)
{
struct smu_context *smu = handle;
+ struct amdgpu_device *adev = smu->adev;
struct smu_umd_pstate_table *pstate_table =
&smu->pstate_table;
int ret = 0;
@@ -2980,7 +3070,13 @@ static int smu_read_sensor(void *handle,
*size = 4;
break;
case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
- *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0 : 1;
+ *(uint32_t *)data = 0;
+ for (int i = 0; i < adev->vcn.num_vcn_inst; i++) {
+ if (!atomic_read(&smu->smu_power.power_gate.vcn_gated[i])) {
+ *(uint32_t *)data = 1;
+ break;
+ }
+ }
*size = 4;
break;
case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
index f88241cdf9b9..b8b6050877c1 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
@@ -399,7 +399,7 @@ struct smu_dpm_context {
struct smu_power_gate {
bool uvd_gated;
bool vce_gated;
- atomic_t vcn_gated;
+ atomic_t vcn_gated[AMDGPU_MAX_VCN_INSTANCES];
atomic_t jpeg_gated;
atomic_t vpe_gated;
atomic_t umsch_mm_gated;
--
2.34.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH 05/18] drm/amd/pm: set vcn enable by instance
2024-10-02 4:36 ` [PATCH 05/18] drm/amd/pm: set vcn enable by instance boyuan.zhang
@ 2024-10-02 11:19 ` Christian König
2024-10-04 18:40 ` Boyuan Zhang
0 siblings, 1 reply; 29+ messages in thread
From: Christian König @ 2024-10-02 11:19 UTC (permalink / raw)
To: boyuan.zhang, amd-gfx, leo.liu, christian.koenig,
alexander.deucher, sunil.khatri
Am 02.10.24 um 06:36 schrieb boyuan.zhang@amd.com:
> From: Boyuan Zhang <boyuan.zhang@amd.com>
>
> The new function smu_dpm_set_vcn_enable_instance() will be used to enable
> or disable vcn engine dynamic power for the given vcn instance only.
>
> The original function smu_dpm_set_vcn_enable() will still be used to enable
> or disable vcn engine dynamic power for all VCN instances as before.
>
> Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
> ---
> drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 132 +++++++++++++++---
> drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 2 +-
> 2 files changed, 115 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> index 939e15b24f86..ddfed7189708 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> @@ -232,12 +232,15 @@ static bool is_vcn_enabled(struct amdgpu_device *adev)
> return true;
> }
>
> -static int smu_dpm_set_vcn_enable(struct smu_context *smu,
> - bool enable)
> +static int smu_dpm_set_vcn_enable_instance(struct smu_context *smu,
> + bool enable,
> + int inst)
> {
> struct smu_power_context *smu_power = &smu->smu_power;
> struct smu_power_gate *power_gate = &smu_power->power_gate;
> + struct amdgpu_device *adev = smu->adev;
> int ret = 0;
> + bool single_inst = (adev->vcn.num_vcn_inst == 1);
Please keep the reverse xmas tree order, e.g. defines like ret last.
Apart from that patches #1-'6 are Acked-by: Christian König
<christian.koenig@amd.com>, but Alex should probably take a look as well
since I'm not that deep into PM.
Regards,
Christian.
>
> /*
> * don't poweron vcn/jpeg when they are skipped.
> @@ -245,15 +248,33 @@ static int smu_dpm_set_vcn_enable(struct smu_context *smu,
> if (!is_vcn_enabled(smu->adev))
> return 0;
>
> - if (!smu->ppt_funcs->dpm_set_vcn_enable)
> + if (!smu->ppt_funcs->dpm_set_vcn_enable_instance && !single_inst)
> return 0;
>
> - if (atomic_read(&power_gate->vcn_gated) ^ enable)
> + if (!smu->ppt_funcs->dpm_set_vcn_enable && single_inst)
> return 0;
>
> - ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable);
> + if (atomic_read(&power_gate->vcn_gated[inst]) ^ enable)
> + return 0;
> +
> + if (single_inst)
> + ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable);
> + else
> + ret = smu->ppt_funcs->dpm_set_vcn_enable_instance(smu, enable, inst);
> if (!ret)
> - atomic_set(&power_gate->vcn_gated, !enable);
> + atomic_set(&power_gate->vcn_gated[inst], !enable);
> +
> + return ret;
> +}
> +
> +static int smu_dpm_set_vcn_enable(struct smu_context *smu,
> + bool enable)
> +{
> + struct amdgpu_device *adev = smu->adev;
> + int ret = 0;
> +
> + for (int i = 0; i < adev->vcn.num_vcn_inst; i++)
> + ret = smu_dpm_set_vcn_enable_instance(smu, enable, i);
>
> return ret;
> }
> @@ -408,6 +429,81 @@ static int smu_dpm_set_power_gate(void *handle,
> return ret;
> }
>
> +/**
> + * smu_dpm_set_power_gate_instance - power gate/ungate the specific IP block
> + * for the specific instance
> + *
> + * @handle: smu_context pointer
> + * @block_type: the IP block to power gate/ungate
> + * @gate: to power gate if true, ungate otherwise
> + * @inst: the instance to power gate/ungate
> + *
> + * This API uses no smu->mutex lock protection due to:
> + * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce).
> + * This is guarded to be race condition free by the caller.
> + * 2. Or get called on user setting request of power_dpm_force_performance_level.
> + * Under this case, the smu->mutex lock protection is already enforced on
> + * the parent API smu_force_performance_level of the call path.
> + */
> +static int smu_dpm_set_power_gate_instance(void *handle,
> + uint32_t block_type,
> + bool gate,
> + int inst)
> +{
> + struct smu_context *smu = handle;
> + int ret = 0;
> +
> + if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) {
> + dev_WARN(smu->adev->dev,
> + "SMU uninitialized but power %s requested for %u!\n",
> + gate ? "gate" : "ungate", block_type);
> + return -EOPNOTSUPP;
> + }
> +
> + switch (block_type) {
> + /*
> + * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses
> + * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept.
> + */
> + case AMD_IP_BLOCK_TYPE_UVD:
> + case AMD_IP_BLOCK_TYPE_VCN:
> + ret = smu_dpm_set_vcn_enable_instance(smu, !gate, inst);
> + if (ret)
> + dev_err(smu->adev->dev, "Failed to power %s VCN!\n",
> + gate ? "gate" : "ungate");
> + break;
> + case AMD_IP_BLOCK_TYPE_GFX:
> + ret = smu_gfx_off_control(smu, gate);
> + if (ret)
> + dev_err(smu->adev->dev, "Failed to %s gfxoff!\n",
> + gate ? "enable" : "disable");
> + break;
> + case AMD_IP_BLOCK_TYPE_SDMA:
> + ret = smu_powergate_sdma(smu, gate);
> + if (ret)
> + dev_err(smu->adev->dev, "Failed to power %s SDMA!\n",
> + gate ? "gate" : "ungate");
> + break;
> + case AMD_IP_BLOCK_TYPE_JPEG:
> + ret = smu_dpm_set_jpeg_enable(smu, !gate);
> + if (ret)
> + dev_err(smu->adev->dev, "Failed to power %s JPEG!\n",
> + gate ? "gate" : "ungate");
> + break;
> + case AMD_IP_BLOCK_TYPE_VPE:
> + ret = smu_dpm_set_vpe_enable(smu, !gate);
> + if (ret)
> + dev_err(smu->adev->dev, "Failed to power %s VPE!\n",
> + gate ? "gate" : "ungate");
> + break;
> + default:
> + dev_err(smu->adev->dev, "Unsupported block type!\n");
> + return -EINVAL;
> + }
> +
> + return ret;
> +}
> +
> /**
> * smu_set_user_clk_dependencies - set user profile clock dependencies
> *
> @@ -774,19 +870,11 @@ static int smu_early_init(struct amdgpu_ip_block *ip_block)
> static int smu_set_default_dpm_table(struct smu_context *smu)
> {
> struct amdgpu_device *adev = smu->adev;
> - struct smu_power_context *smu_power = &smu->smu_power;
> - struct smu_power_gate *power_gate = &smu_power->power_gate;
> - int vcn_gate, jpeg_gate;
> int ret = 0;
>
> if (!smu->ppt_funcs->set_default_dpm_table)
> return 0;
>
> - if (adev->pg_flags & AMD_PG_SUPPORT_VCN)
> - vcn_gate = atomic_read(&power_gate->vcn_gated);
> - if (adev->pg_flags & AMD_PG_SUPPORT_JPEG)
> - jpeg_gate = atomic_read(&power_gate->jpeg_gated);
> -
> if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
> ret = smu_dpm_set_vcn_enable(smu, true);
> if (ret)
> @@ -805,10 +893,10 @@ static int smu_set_default_dpm_table(struct smu_context *smu)
> "Failed to setup default dpm clock tables!\n");
>
> if (adev->pg_flags & AMD_PG_SUPPORT_JPEG)
> - smu_dpm_set_jpeg_enable(smu, !jpeg_gate);
> + smu_dpm_set_jpeg_enable(smu, false);
> err_out:
> if (adev->pg_flags & AMD_PG_SUPPORT_VCN)
> - smu_dpm_set_vcn_enable(smu, !vcn_gate);
> + smu_dpm_set_vcn_enable(smu, false);
>
> return ret;
> }
> @@ -1253,7 +1341,8 @@ static int smu_sw_init(struct amdgpu_ip_block *ip_block)
> smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
> smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
>
> - atomic_set(&smu->smu_power.power_gate.vcn_gated, 1);
> + for (int i = 0; i < adev->vcn.num_vcn_inst; i++)
> + atomic_set(&smu->smu_power.power_gate.vcn_gated[i], 1);
> atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1);
> atomic_set(&smu->smu_power.power_gate.vpe_gated, 1);
> atomic_set(&smu->smu_power.power_gate.umsch_mm_gated, 1);
> @@ -2932,6 +3021,7 @@ static int smu_read_sensor(void *handle,
> int *size_arg)
> {
> struct smu_context *smu = handle;
> + struct amdgpu_device *adev = smu->adev;
> struct smu_umd_pstate_table *pstate_table =
> &smu->pstate_table;
> int ret = 0;
> @@ -2980,7 +3070,13 @@ static int smu_read_sensor(void *handle,
> *size = 4;
> break;
> case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
> - *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0 : 1;
> + *(uint32_t *)data = 0;
> + for (int i = 0; i < adev->vcn.num_vcn_inst; i++) {
> + if (!atomic_read(&smu->smu_power.power_gate.vcn_gated[i])) {
> + *(uint32_t *)data = 1;
> + break;
> + }
> + }
> *size = 4;
> break;
> case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
> index f88241cdf9b9..b8b6050877c1 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
> +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
> @@ -399,7 +399,7 @@ struct smu_dpm_context {
> struct smu_power_gate {
> bool uvd_gated;
> bool vce_gated;
> - atomic_t vcn_gated;
> + atomic_t vcn_gated[AMDGPU_MAX_VCN_INSTANCES];
> atomic_t jpeg_gated;
> atomic_t vpe_gated;
> atomic_t umsch_mm_gated;
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH 05/18] drm/amd/pm: set vcn enable by instance
2024-10-02 11:19 ` Christian König
@ 2024-10-04 18:40 ` Boyuan Zhang
0 siblings, 0 replies; 29+ messages in thread
From: Boyuan Zhang @ 2024-10-04 18:40 UTC (permalink / raw)
To: Christian König, amd-gfx, leo.liu, christian.koenig,
alexander.deucher, sunil.khatri
On 2024-10-02 07:19, Christian König wrote:
> Am 02.10.24 um 06:36 schrieb boyuan.zhang@amd.com:
>> From: Boyuan Zhang <boyuan.zhang@amd.com>
>>
>> The new function smu_dpm_set_vcn_enable_instance() will be used to
>> enable
>> or disable vcn engine dynamic power for the given vcn instance only.
>>
>> The original function smu_dpm_set_vcn_enable() will still be used to
>> enable
>> or disable vcn engine dynamic power for all VCN instances as before.
>>
>> Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
>> ---
>> drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 132 +++++++++++++++---
>> drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 2 +-
>> 2 files changed, 115 insertions(+), 19 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
>> b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
>> index 939e15b24f86..ddfed7189708 100644
>> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
>> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
>> @@ -232,12 +232,15 @@ static bool is_vcn_enabled(struct amdgpu_device
>> *adev)
>> return true;
>> }
>> -static int smu_dpm_set_vcn_enable(struct smu_context *smu,
>> - bool enable)
>> +static int smu_dpm_set_vcn_enable_instance(struct smu_context *smu,
>> + bool enable,
>> + int inst)
>> {
>> struct smu_power_context *smu_power = &smu->smu_power;
>> struct smu_power_gate *power_gate = &smu_power->power_gate;
>> + struct amdgpu_device *adev = smu->adev;
>> int ret = 0;
>> + bool single_inst = (adev->vcn.num_vcn_inst == 1);
>
> Please keep the reverse xmas tree order, e.g. defines like ret last.
>
> Apart from that patches #1-'6 are Acked-by: Christian König
> <christian.koenig@amd.com>, but Alex should probably take a look as
> well since I'm not that deep into PM.
>
> Regards,
> Christian.
Fixed the format. Also re-worked all PM patches to remove all duplicated
functions. Please check the new v2 patch set.
Regards,
Boyuan
>
>> /*
>> * don't poweron vcn/jpeg when they are skipped.
>> @@ -245,15 +248,33 @@ static int smu_dpm_set_vcn_enable(struct
>> smu_context *smu,
>> if (!is_vcn_enabled(smu->adev))
>> return 0;
>> - if (!smu->ppt_funcs->dpm_set_vcn_enable)
>> + if (!smu->ppt_funcs->dpm_set_vcn_enable_instance && !single_inst)
>> return 0;
>> - if (atomic_read(&power_gate->vcn_gated) ^ enable)
>> + if (!smu->ppt_funcs->dpm_set_vcn_enable && single_inst)
>> return 0;
>> - ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable);
>> + if (atomic_read(&power_gate->vcn_gated[inst]) ^ enable)
>> + return 0;
>> +
>> + if (single_inst)
>> + ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable);
>> + else
>> + ret = smu->ppt_funcs->dpm_set_vcn_enable_instance(smu,
>> enable, inst);
>> if (!ret)
>> - atomic_set(&power_gate->vcn_gated, !enable);
>> + atomic_set(&power_gate->vcn_gated[inst], !enable);
>> +
>> + return ret;
>> +}
>> +
>> +static int smu_dpm_set_vcn_enable(struct smu_context *smu,
>> + bool enable)
>> +{
>> + struct amdgpu_device *adev = smu->adev;
>> + int ret = 0;
>> +
>> + for (int i = 0; i < adev->vcn.num_vcn_inst; i++)
>> + ret = smu_dpm_set_vcn_enable_instance(smu, enable, i);
>> return ret;
>> }
>> @@ -408,6 +429,81 @@ static int smu_dpm_set_power_gate(void *handle,
>> return ret;
>> }
>> +/**
>> + * smu_dpm_set_power_gate_instance - power gate/ungate the specific
>> IP block
>> + * for the specific instance
>> + *
>> + * @handle: smu_context pointer
>> + * @block_type: the IP block to power gate/ungate
>> + * @gate: to power gate if true, ungate otherwise
>> + * @inst: the instance to power gate/ungate
>> + *
>> + * This API uses no smu->mutex lock protection due to:
>> + * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce).
>> + * This is guarded to be race condition free by the caller.
>> + * 2. Or get called on user setting request of
>> power_dpm_force_performance_level.
>> + * Under this case, the smu->mutex lock protection is already
>> enforced on
>> + * the parent API smu_force_performance_level of the call path.
>> + */
>> +static int smu_dpm_set_power_gate_instance(void *handle,
>> + uint32_t block_type,
>> + bool gate,
>> + int inst)
>> +{
>> + struct smu_context *smu = handle;
>> + int ret = 0;
>> +
>> + if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) {
>> + dev_WARN(smu->adev->dev,
>> + "SMU uninitialized but power %s requested for %u!\n",
>> + gate ? "gate" : "ungate", block_type);
>> + return -EOPNOTSUPP;
>> + }
>> +
>> + switch (block_type) {
>> + /*
>> + * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses
>> + * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept.
>> + */
>> + case AMD_IP_BLOCK_TYPE_UVD:
>> + case AMD_IP_BLOCK_TYPE_VCN:
>> + ret = smu_dpm_set_vcn_enable_instance(smu, !gate, inst);
>> + if (ret)
>> + dev_err(smu->adev->dev, "Failed to power %s VCN!\n",
>> + gate ? "gate" : "ungate");
>> + break;
>> + case AMD_IP_BLOCK_TYPE_GFX:
>> + ret = smu_gfx_off_control(smu, gate);
>> + if (ret)
>> + dev_err(smu->adev->dev, "Failed to %s gfxoff!\n",
>> + gate ? "enable" : "disable");
>> + break;
>> + case AMD_IP_BLOCK_TYPE_SDMA:
>> + ret = smu_powergate_sdma(smu, gate);
>> + if (ret)
>> + dev_err(smu->adev->dev, "Failed to power %s SDMA!\n",
>> + gate ? "gate" : "ungate");
>> + break;
>> + case AMD_IP_BLOCK_TYPE_JPEG:
>> + ret = smu_dpm_set_jpeg_enable(smu, !gate);
>> + if (ret)
>> + dev_err(smu->adev->dev, "Failed to power %s JPEG!\n",
>> + gate ? "gate" : "ungate");
>> + break;
>> + case AMD_IP_BLOCK_TYPE_VPE:
>> + ret = smu_dpm_set_vpe_enable(smu, !gate);
>> + if (ret)
>> + dev_err(smu->adev->dev, "Failed to power %s VPE!\n",
>> + gate ? "gate" : "ungate");
>> + break;
>> + default:
>> + dev_err(smu->adev->dev, "Unsupported block type!\n");
>> + return -EINVAL;
>> + }
>> +
>> + return ret;
>> +}
>> +
>> /**
>> * smu_set_user_clk_dependencies - set user profile clock dependencies
>> *
>> @@ -774,19 +870,11 @@ static int smu_early_init(struct
>> amdgpu_ip_block *ip_block)
>> static int smu_set_default_dpm_table(struct smu_context *smu)
>> {
>> struct amdgpu_device *adev = smu->adev;
>> - struct smu_power_context *smu_power = &smu->smu_power;
>> - struct smu_power_gate *power_gate = &smu_power->power_gate;
>> - int vcn_gate, jpeg_gate;
>> int ret = 0;
>> if (!smu->ppt_funcs->set_default_dpm_table)
>> return 0;
>> - if (adev->pg_flags & AMD_PG_SUPPORT_VCN)
>> - vcn_gate = atomic_read(&power_gate->vcn_gated);
>> - if (adev->pg_flags & AMD_PG_SUPPORT_JPEG)
>> - jpeg_gate = atomic_read(&power_gate->jpeg_gated);
>> -
>> if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
>> ret = smu_dpm_set_vcn_enable(smu, true);
>> if (ret)
>> @@ -805,10 +893,10 @@ static int smu_set_default_dpm_table(struct
>> smu_context *smu)
>> "Failed to setup default dpm clock tables!\n");
>> if (adev->pg_flags & AMD_PG_SUPPORT_JPEG)
>> - smu_dpm_set_jpeg_enable(smu, !jpeg_gate);
>> + smu_dpm_set_jpeg_enable(smu, false);
>> err_out:
>> if (adev->pg_flags & AMD_PG_SUPPORT_VCN)
>> - smu_dpm_set_vcn_enable(smu, !vcn_gate);
>> + smu_dpm_set_vcn_enable(smu, false);
>> return ret;
>> }
>> @@ -1253,7 +1341,8 @@ static int smu_sw_init(struct amdgpu_ip_block
>> *ip_block)
>> smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
>> smu->default_power_profile_mode =
>> PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
>> - atomic_set(&smu->smu_power.power_gate.vcn_gated, 1);
>> + for (int i = 0; i < adev->vcn.num_vcn_inst; i++)
>> + atomic_set(&smu->smu_power.power_gate.vcn_gated[i], 1);
>> atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1);
>> atomic_set(&smu->smu_power.power_gate.vpe_gated, 1);
>> atomic_set(&smu->smu_power.power_gate.umsch_mm_gated, 1);
>> @@ -2932,6 +3021,7 @@ static int smu_read_sensor(void *handle,
>> int *size_arg)
>> {
>> struct smu_context *smu = handle;
>> + struct amdgpu_device *adev = smu->adev;
>> struct smu_umd_pstate_table *pstate_table =
>> &smu->pstate_table;
>> int ret = 0;
>> @@ -2980,7 +3070,13 @@ static int smu_read_sensor(void *handle,
>> *size = 4;
>> break;
>> case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
>> - *(uint32_t *)data =
>> atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0 : 1;
>> + *(uint32_t *)data = 0;
>> + for (int i = 0; i < adev->vcn.num_vcn_inst; i++) {
>> + if
>> (!atomic_read(&smu->smu_power.power_gate.vcn_gated[i])) {
>> + *(uint32_t *)data = 1;
>> + break;
>> + }
>> + }
>> *size = 4;
>> break;
>> case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
>> diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
>> b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
>> index f88241cdf9b9..b8b6050877c1 100644
>> --- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
>> +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
>> @@ -399,7 +399,7 @@ struct smu_dpm_context {
>> struct smu_power_gate {
>> bool uvd_gated;
>> bool vce_gated;
>> - atomic_t vcn_gated;
>> + atomic_t vcn_gated[AMDGPU_MAX_VCN_INSTANCES];
>> atomic_t jpeg_gated;
>> atomic_t vpe_gated;
>> atomic_t umsch_mm_gated;
>
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH 06/18] drm/amd/pm: set powergating by smu by instance
2024-10-02 4:36 [PATCH 00/18] Separating vcn power management by instance boyuan.zhang
` (4 preceding siblings ...)
2024-10-02 4:36 ` [PATCH 05/18] drm/amd/pm: set vcn enable by instance boyuan.zhang
@ 2024-10-02 4:36 ` boyuan.zhang
2024-10-02 4:36 ` [PATCH 07/18] drm/amdgpu/vcn: separate gating state " boyuan.zhang
` (11 subsequent siblings)
17 siblings, 0 replies; 29+ messages in thread
From: boyuan.zhang @ 2024-10-02 4:36 UTC (permalink / raw)
To: amd-gfx, leo.liu, christian.koenig, alexander.deucher,
sunil.khatri
Cc: Boyuan Zhang
From: Boyuan Zhang <boyuan.zhang@amd.com>
Add a new function to set powergating_by_smu for the given instance
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
---
.../gpu/drm/amd/include/kgd_pp_interface.h | 2 +
drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 67 +++++++++++++++++++
drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h | 4 ++
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 1 +
4 files changed, 74 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index 2fa71f68205e..cdd891f51422 100644
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -406,6 +406,8 @@ struct amd_pm_funcs {
int (*wait_for_fw_loading_complete)(void *handle);
int (*set_powergating_by_smu)(void *handle,
uint32_t block_type, bool gate);
+ int (*set_powergating_by_smu_instance)(void *handle,
+ uint32_t block_type, bool gate, int inst);
int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id);
int (*set_power_limit)(void *handle, uint32_t n);
int (*get_power_limit)(void *handle, uint32_t *limit,
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
index 9dc82f4d7c93..f2d2f85476dc 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
@@ -110,6 +110,49 @@ int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, uint32_t block
return ret;
}
+int amdgpu_dpm_set_powergating_by_smu_instance(struct amdgpu_device *adev, uint32_t block_type, bool gate, int inst)
+{
+ int ret = 0;
+ const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
+ enum ip_power_state pwr_state = gate ? POWER_STATE_OFF : POWER_STATE_ON;
+ bool is_vcn = (block_type == AMD_IP_BLOCK_TYPE_UVD || block_type == AMD_IP_BLOCK_TYPE_VCN);
+
+ if (atomic_read(&adev->pm.pwr_state[block_type]) == pwr_state &&
+ (!is_vcn || adev->vcn.num_vcn_inst == 1)) {
+ dev_dbg(adev->dev, "IP block%d already in the target %s state!",
+ block_type, gate ? "gate" : "ungate");
+ return 0;
+ }
+
+ mutex_lock(&adev->pm.mutex);
+
+ switch (block_type) {
+ case AMD_IP_BLOCK_TYPE_UVD:
+ case AMD_IP_BLOCK_TYPE_VCE:
+ case AMD_IP_BLOCK_TYPE_GFX:
+ case AMD_IP_BLOCK_TYPE_VCN:
+ case AMD_IP_BLOCK_TYPE_SDMA:
+ case AMD_IP_BLOCK_TYPE_JPEG:
+ case AMD_IP_BLOCK_TYPE_GMC:
+ case AMD_IP_BLOCK_TYPE_ACP:
+ case AMD_IP_BLOCK_TYPE_VPE:
+ if (pp_funcs && pp_funcs->set_powergating_by_smu_instance) {
+ ret = (pp_funcs->set_powergating_by_smu_instance(
+ (adev)->powerplay.pp_handle, block_type, gate, inst));
+ }
+ break;
+ default:
+ break;
+ }
+
+ if (!ret)
+ atomic_set(&adev->pm.pwr_state[block_type], pwr_state);
+
+ mutex_unlock(&adev->pm.mutex);
+
+ return ret;
+}
+
int amdgpu_dpm_set_gfx_power_up_by_imu(struct amdgpu_device *adev)
{
struct smu_context *smu = adev->powerplay.pp_handle;
@@ -572,6 +615,30 @@ void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
enable ? "enable" : "disable", ret);
}
+void amdgpu_dpm_enable_vcn(struct amdgpu_device *adev, bool enable, int inst)
+{
+ int ret = 0;
+
+ if (adev->family == AMDGPU_FAMILY_SI) {
+ mutex_lock(&adev->pm.mutex);
+ if (enable) {
+ adev->pm.dpm.uvd_active = true;
+ adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD;
+ } else {
+ adev->pm.dpm.uvd_active = false;
+ }
+ mutex_unlock(&adev->pm.mutex);
+
+ amdgpu_dpm_compute_clocks(adev);
+ return;
+ }
+
+ ret = amdgpu_dpm_set_powergating_by_smu_instance(adev, AMD_IP_BLOCK_TYPE_UVD, !enable, inst);
+ if (ret)
+ DRM_ERROR("Dpm %s uvd failed, ret = %d. \n",
+ enable ? "enable" : "disable", ret);
+}
+
void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
{
int ret = 0;
diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
index f5bf41f21c41..f4cd60ffba47 100644
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
@@ -395,6 +395,9 @@ int amdgpu_dpm_set_apu_thermal_limit(struct amdgpu_device *adev, uint32_t limit)
int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev,
uint32_t block_type, bool gate);
+int amdgpu_dpm_set_powergating_by_smu_instance(struct amdgpu_device *adev,
+ uint32_t block_type, bool gate, int inst);
+
extern int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low);
extern int amdgpu_dpm_get_mclk(struct amdgpu_device *adev, bool low);
@@ -442,6 +445,7 @@ void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev);
void amdgpu_dpm_compute_clocks(struct amdgpu_device *adev);
void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable);
+void amdgpu_dpm_enable_vcn(struct amdgpu_device *adev, bool enable, int inst);
void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable);
void amdgpu_dpm_enable_jpeg(struct amdgpu_device *adev, bool enable);
void amdgpu_dpm_enable_vpe(struct amdgpu_device *adev, bool enable);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index ddfed7189708..449925105889 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -3744,6 +3744,7 @@ static const struct amd_pm_funcs swsmu_pm_funcs = {
.dispatch_tasks = smu_handle_dpm_task,
.load_firmware = smu_load_microcode,
.set_powergating_by_smu = smu_dpm_set_power_gate,
+ .set_powergating_by_smu_instance = smu_dpm_set_power_gate_instance,
.set_power_limit = smu_set_power_limit,
.get_power_limit = smu_get_power_limit,
.get_power_profile_mode = smu_get_power_profile_mode,
--
2.34.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH 07/18] drm/amdgpu/vcn: separate gating state by instance
2024-10-02 4:36 [PATCH 00/18] Separating vcn power management by instance boyuan.zhang
` (5 preceding siblings ...)
2024-10-02 4:36 ` [PATCH 06/18] drm/amd/pm: set powergating by smu " boyuan.zhang
@ 2024-10-02 4:36 ` boyuan.zhang
2024-10-02 11:28 ` Christian König
2024-10-02 4:36 ` [PATCH 08/18] drm/amdgpu/vcn: separate idle work " boyuan.zhang
` (10 subsequent siblings)
17 siblings, 1 reply; 29+ messages in thread
From: boyuan.zhang @ 2024-10-02 4:36 UTC (permalink / raw)
To: amd-gfx, leo.liu, christian.koenig, alexander.deucher,
sunil.khatri
Cc: Boyuan Zhang
From: Boyuan Zhang <boyuan.zhang@amd.com>
vcn gating state should now be based on instance. For example, instance 0
can be gated while instance 1 is ungated, or vice versa.
Therefore, change the cur_state to be an array, so that it can track the
gating status for each vcn instance now.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 2 +-
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 6 ++--
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 8 ++---
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 23 +++++++------
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 38 +++++++++++----------
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 41 ++++++++++++-----------
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 41 +++++++++++++----------
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 23 +++++++------
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 23 +++++++------
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 3 +-
10 files changed, 114 insertions(+), 94 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index 2a1f3dbb14d3..f6717f780acd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -308,7 +308,7 @@ struct amdgpu_vcn {
struct delayed_work idle_work;
const struct firmware *fw[AMDGPU_MAX_VCN_INSTANCES]; /* VCN firmware */
unsigned num_enc_rings;
- enum amd_powergating_state cur_state;
+ enum amd_powergating_state cur_state[AMDGPU_MAX_VCN_INSTANCES];
bool indirect_sram;
uint8_t num_vcn_inst;
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 6717ff692d8d..bafdd6d5ff24 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -279,7 +279,7 @@ static int vcn_v1_0_hw_fini(void *handle)
cancel_delayed_work_sync(&adev->vcn.idle_work);
if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
- (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
+ (adev->vcn.cur_state[0] != AMD_PG_STATE_GATE &&
RREG32_SOC15(VCN, 0, mmUVD_STATUS))) {
vcn_v1_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
}
@@ -1813,7 +1813,7 @@ static int vcn_v1_0_set_powergating_state(void *handle,
int ret;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- if (state == adev->vcn.cur_state)
+ if (state == adev->vcn.cur_state[0])
return 0;
if (state == AMD_PG_STATE_GATE)
@@ -1822,7 +1822,7 @@ static int vcn_v1_0_set_powergating_state(void *handle,
ret = vcn_v1_0_start(adev);
if (!ret)
- adev->vcn.cur_state = state;
+ adev->vcn.cur_state[0] = state;
return ret;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index be6998ed56bc..72e36fbaad39 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -316,7 +316,7 @@ static int vcn_v2_0_hw_fini(void *handle)
cancel_delayed_work_sync(&adev->vcn.idle_work);
if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
- (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
+ (adev->vcn.cur_state[0] != AMD_PG_STATE_GATE &&
RREG32_SOC15(VCN, 0, mmUVD_STATUS)))
vcn_v2_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
@@ -1812,11 +1812,11 @@ static int vcn_v2_0_set_powergating_state(void *handle,
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
if (amdgpu_sriov_vf(adev)) {
- adev->vcn.cur_state = AMD_PG_STATE_UNGATE;
+ adev->vcn.cur_state[0] = AMD_PG_STATE_UNGATE;
return 0;
}
- if (state == adev->vcn.cur_state)
+ if (state == adev->vcn.cur_state[0])
return 0;
if (state == AMD_PG_STATE_GATE)
@@ -1825,7 +1825,7 @@ static int vcn_v2_0_set_powergating_state(void *handle,
ret = vcn_v2_0_start(adev);
if (!ret)
- adev->vcn.cur_state = state;
+ adev->vcn.cur_state[0] = state;
return ret;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
index 7ab0314b27ec..09b342ad02cd 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
@@ -397,9 +397,10 @@ static int vcn_v2_5_hw_fini(void *handle)
continue;
if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
- (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
- RREG32_SOC15(VCN, i, mmUVD_STATUS)))
+ (adev->vcn.cur_state[i] != AMD_PG_STATE_GATE &&
+ RREG32_SOC15(VCN, i, mmUVD_STATUS))) {
vcn_v2_5_set_powergating_state(adev, AMD_PG_STATE_GATE);
+ }
if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN))
amdgpu_irq_put(adev, &adev->vcn.inst[i].ras_poison_irq, 0);
@@ -1832,16 +1833,18 @@ static int vcn_v2_5_set_powergating_state(void *handle,
if (amdgpu_sriov_vf(adev))
return 0;
- if(state == adev->vcn.cur_state)
- return 0;
+ for (int i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+ if (state == adev->vcn.cur_state[i])
+ return 0;
- if (state == AMD_PG_STATE_GATE)
- ret = vcn_v2_5_stop(adev);
- else
- ret = vcn_v2_5_start(adev);
+ if (state == AMD_PG_STATE_GATE)
+ ret = vcn_v2_5_stop(adev);
+ else
+ ret = vcn_v2_5_start(adev);
- if(!ret)
- adev->vcn.cur_state = state;
+ if (!ret)
+ adev->vcn.cur_state[i] = state;
+ }
return ret;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index 38452446fcb0..ee9a40443d65 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -430,8 +430,8 @@ static int vcn_v3_0_hw_fini(void *handle)
if (!amdgpu_sriov_vf(adev)) {
if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
- (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
- RREG32_SOC15(VCN, i, mmUVD_STATUS))) {
+ (adev->vcn.cur_state[i] != AMD_PG_STATE_GATE &&
+ RREG32_SOC15(VCN, i, mmUVD_STATUS))) {
vcn_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
}
}
@@ -2163,25 +2163,27 @@ static int vcn_v3_0_set_powergating_state(void *handle,
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
int ret;
- /* for SRIOV, guest should not control VCN Power-gating
- * MMSCH FW should control Power-gating and clock-gating
- * guest should avoid touching CGC and PG
- */
- if (amdgpu_sriov_vf(adev)) {
- adev->vcn.cur_state = AMD_PG_STATE_UNGATE;
- return 0;
- }
+ for (int i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+ /* for SRIOV, guest should not control VCN Power-gating
+ * MMSCH FW should control Power-gating and clock-gating
+ * guest should avoid touching CGC and PG
+ */
+ if (amdgpu_sriov_vf(adev)) {
+ adev->vcn.cur_state[i] = AMD_PG_STATE_UNGATE;
+ return 0;
+ }
- if (state == adev->vcn.cur_state)
- return 0;
+ if (state == adev->vcn.cur_state[i])
+ return 0;
- if (state == AMD_PG_STATE_GATE)
- ret = vcn_v3_0_stop(adev);
- else
- ret = vcn_v3_0_start(adev);
+ if (state == AMD_PG_STATE_GATE)
+ ret = vcn_v3_0_stop(adev);
+ else
+ ret = vcn_v3_0_start(adev);
- if (!ret)
- adev->vcn.cur_state = state;
+ if (!ret)
+ adev->vcn.cur_state[i] = state;
+ }
return ret;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
index 078bb30497e0..aaecc680b631 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
@@ -355,11 +355,12 @@ static int vcn_v4_0_hw_fini(void *handle)
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
if (adev->vcn.harvest_config & (1 << i))
continue;
+
if (!amdgpu_sriov_vf(adev)) {
if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
- (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
- RREG32_SOC15(VCN, i, regUVD_STATUS))) {
- vcn_v4_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
+ (adev->vcn.cur_state[i] != AMD_PG_STATE_GATE &&
+ RREG32_SOC15(VCN, i, regUVD_STATUS))) {
+ vcn_v4_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
}
}
if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN))
@@ -2040,25 +2041,27 @@ static int vcn_v4_0_set_powergating_state(void *handle, enum amd_powergating_sta
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
int ret;
- /* for SRIOV, guest should not control VCN Power-gating
- * MMSCH FW should control Power-gating and clock-gating
- * guest should avoid touching CGC and PG
- */
- if (amdgpu_sriov_vf(adev)) {
- adev->vcn.cur_state = AMD_PG_STATE_UNGATE;
- return 0;
- }
+ for (int i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+ /* for SRIOV, guest should not control VCN Power-gating
+ * MMSCH FW should control Power-gating and clock-gating
+ * guest should avoid touching CGC and PG
+ */
+ if (amdgpu_sriov_vf(adev)) {
+ adev->vcn.cur_state[i] = AMD_PG_STATE_UNGATE;
+ return 0;
+ }
- if (state == adev->vcn.cur_state)
- return 0;
+ if (state == adev->vcn.cur_state[i])
+ return 0;
- if (state == AMD_PG_STATE_GATE)
- ret = vcn_v4_0_stop(adev);
- else
- ret = vcn_v4_0_start(adev);
+ if (state == AMD_PG_STATE_GATE)
+ ret = vcn_v4_0_stop(adev);
+ else
+ ret = vcn_v4_0_start(adev);
- if (!ret)
- adev->vcn.cur_state = state;
+ if (!ret)
+ adev->vcn.cur_state[i] = state;
+ }
return ret;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
index be7b0bfba27a..87c04c512357 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
@@ -318,8 +318,11 @@ static int vcn_v4_0_3_hw_fini(void *handle)
cancel_delayed_work_sync(&adev->vcn.idle_work);
- if (adev->vcn.cur_state != AMD_PG_STATE_GATE)
- vcn_v4_0_3_set_powergating_state(adev, AMD_PG_STATE_GATE);
+ for (int i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+ if (adev->vcn.cur_state[i] != AMD_PG_STATE_GATE) {
+ vcn_v4_0_3_set_powergating_state(adev, AMD_PG_STATE_GATE);
+ }
+ }
return 0;
}
@@ -1627,25 +1630,27 @@ static int vcn_v4_0_3_set_powergating_state(void *handle,
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
int ret;
- /* for SRIOV, guest should not control VCN Power-gating
- * MMSCH FW should control Power-gating and clock-gating
- * guest should avoid touching CGC and PG
- */
- if (amdgpu_sriov_vf(adev)) {
- adev->vcn.cur_state = AMD_PG_STATE_UNGATE;
- return 0;
- }
+ for (int i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+ /* for SRIOV, guest should not control VCN Power-gating
+ * MMSCH FW should control Power-gating and clock-gating
+ * guest should avoid touching CGC and PG
+ */
+ if (amdgpu_sriov_vf(adev)) {
+ adev->vcn.cur_state[i] = AMD_PG_STATE_UNGATE;
+ return 0;
+ }
- if (state == adev->vcn.cur_state)
- return 0;
+ if (state == adev->vcn.cur_state[i])
+ return 0;
- if (state == AMD_PG_STATE_GATE)
- ret = vcn_v4_0_3_stop(adev);
- else
- ret = vcn_v4_0_3_start(adev);
+ if (state == AMD_PG_STATE_GATE)
+ ret = vcn_v4_0_3_stop(adev);
+ else
+ ret = vcn_v4_0_3_start(adev);
- if (!ret)
- adev->vcn.cur_state = state;
+ if (!ret)
+ adev->vcn.cur_state[i] = state;
+ }
return ret;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
index 0e70df04ceb9..2092360e133a 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
@@ -305,10 +305,11 @@ static int vcn_v4_0_5_hw_fini(void *handle)
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
if (adev->vcn.harvest_config & (1 << i))
continue;
+
if (!amdgpu_sriov_vf(adev)) {
if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
- (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
- RREG32_SOC15(VCN, i, regUVD_STATUS))) {
+ (adev->vcn.cur_state[i] != AMD_PG_STATE_GATE &&
+ RREG32_SOC15(VCN, i, regUVD_STATUS))) {
vcn_v4_0_5_set_powergating_state(adev, AMD_PG_STATE_GATE);
}
}
@@ -1534,16 +1535,18 @@ static int vcn_v4_0_5_set_powergating_state(void *handle, enum amd_powergating_s
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
int ret;
- if (state == adev->vcn.cur_state)
- return 0;
+ for (int i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+ if (state == adev->vcn.cur_state[i])
+ return 0;
- if (state == AMD_PG_STATE_GATE)
- ret = vcn_v4_0_5_stop(adev);
- else
- ret = vcn_v4_0_5_start(adev);
+ if (state == AMD_PG_STATE_GATE)
+ ret = vcn_v4_0_5_stop(adev);
+ else
+ ret = vcn_v4_0_5_start(adev);
- if (!ret)
- adev->vcn.cur_state = state;
+ if (!ret)
+ adev->vcn.cur_state[i] = state;
+ }
return ret;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
index 6b38927024d1..045ac9c8d8be 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
@@ -269,10 +269,11 @@ static int vcn_v5_0_0_hw_fini(void *handle)
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
if (adev->vcn.harvest_config & (1 << i))
continue;
+
if (!amdgpu_sriov_vf(adev)) {
if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
- (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
- RREG32_SOC15(VCN, i, regUVD_STATUS))) {
+ (adev->vcn.cur_state[i] != AMD_PG_STATE_GATE &&
+ RREG32_SOC15(VCN, i, regUVD_STATUS))) {
vcn_v5_0_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
}
}
@@ -1261,16 +1262,18 @@ static int vcn_v5_0_0_set_powergating_state(void *handle, enum amd_powergating_s
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
int ret;
- if (state == adev->vcn.cur_state)
- return 0;
+ for (int i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+ if (state == adev->vcn.cur_state[i])
+ return 0;
- if (state == AMD_PG_STATE_GATE)
- ret = vcn_v5_0_0_stop(adev);
- else
- ret = vcn_v5_0_0_start(adev);
+ if (state == AMD_PG_STATE_GATE)
+ ret = vcn_v5_0_0_stop(adev);
+ else
+ ret = vcn_v5_0_0_start(adev);
- if (!ret)
- adev->vcn.cur_state = state;
+ if (!ret)
+ adev->vcn.cur_state[i] = state;
+ }
return ret;
}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 449925105889..86001682e13e 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -2112,7 +2112,8 @@ static int smu_hw_fini(void *handle)
smu_dpm_set_vpe_enable(smu, false);
smu_dpm_set_umsch_mm_enable(smu, false);
- adev->vcn.cur_state = AMD_PG_STATE_GATE;
+ for (int i = 0; i < adev->vcn.num_vcn_inst; ++i)
+ adev->vcn.cur_state[i] = AMD_PG_STATE_GATE;
adev->jpeg.cur_state = AMD_PG_STATE_GATE;
if (!smu->pm_enabled)
--
2.34.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH 07/18] drm/amdgpu/vcn: separate gating state by instance
2024-10-02 4:36 ` [PATCH 07/18] drm/amdgpu/vcn: separate gating state " boyuan.zhang
@ 2024-10-02 11:28 ` Christian König
2024-10-04 18:42 ` Boyuan Zhang
0 siblings, 1 reply; 29+ messages in thread
From: Christian König @ 2024-10-02 11:28 UTC (permalink / raw)
To: boyuan.zhang, amd-gfx, leo.liu, christian.koenig,
alexander.deucher, sunil.khatri
Am 02.10.24 um 06:36 schrieb boyuan.zhang@amd.com:
> From: Boyuan Zhang <boyuan.zhang@amd.com>
>
> vcn gating state should now be based on instance. For example, instance 0
> can be gated while instance 1 is ungated, or vice versa.
>
> Therefore, change the cur_state to be an array, so that it can track the
> gating status for each vcn instance now.
>
> Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Mhm, some questions. See below.
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 2 +-
> drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 6 ++--
> drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 8 ++---
> drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 23 +++++++------
> drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 38 +++++++++++----------
> drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 41 ++++++++++++-----------
> drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 41 +++++++++++++----------
> drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 23 +++++++------
> drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 23 +++++++------
> drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 3 +-
> 10 files changed, 114 insertions(+), 94 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
> index 2a1f3dbb14d3..f6717f780acd 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
> @@ -308,7 +308,7 @@ struct amdgpu_vcn {
> struct delayed_work idle_work;
> const struct firmware *fw[AMDGPU_MAX_VCN_INSTANCES]; /* VCN firmware */
> unsigned num_enc_rings;
> - enum amd_powergating_state cur_state;
> + enum amd_powergating_state cur_state[AMDGPU_MAX_VCN_INSTANCES];
> bool indirect_sram;
>
> uint8_t num_vcn_inst;
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> index 6717ff692d8d..bafdd6d5ff24 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> @@ -279,7 +279,7 @@ static int vcn_v1_0_hw_fini(void *handle)
> cancel_delayed_work_sync(&adev->vcn.idle_work);
>
> if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
> - (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
> + (adev->vcn.cur_state[0] != AMD_PG_STATE_GATE &&
> RREG32_SOC15(VCN, 0, mmUVD_STATUS))) {
> vcn_v1_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
> }
> @@ -1813,7 +1813,7 @@ static int vcn_v1_0_set_powergating_state(void *handle,
> int ret;
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> - if (state == adev->vcn.cur_state)
> + if (state == adev->vcn.cur_state[0])
> return 0;
>
> if (state == AMD_PG_STATE_GATE)
> @@ -1822,7 +1822,7 @@ static int vcn_v1_0_set_powergating_state(void *handle,
> ret = vcn_v1_0_start(adev);
>
> if (!ret)
> - adev->vcn.cur_state = state;
> + adev->vcn.cur_state[0] = state;
> return ret;
> }
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> index be6998ed56bc..72e36fbaad39 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> @@ -316,7 +316,7 @@ static int vcn_v2_0_hw_fini(void *handle)
> cancel_delayed_work_sync(&adev->vcn.idle_work);
>
> if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
> - (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
> + (adev->vcn.cur_state[0] != AMD_PG_STATE_GATE &&
> RREG32_SOC15(VCN, 0, mmUVD_STATUS)))
> vcn_v2_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
>
> @@ -1812,11 +1812,11 @@ static int vcn_v2_0_set_powergating_state(void *handle,
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> if (amdgpu_sriov_vf(adev)) {
> - adev->vcn.cur_state = AMD_PG_STATE_UNGATE;
> + adev->vcn.cur_state[0] = AMD_PG_STATE_UNGATE;
> return 0;
> }
>
> - if (state == adev->vcn.cur_state)
> + if (state == adev->vcn.cur_state[0])
> return 0;
>
> if (state == AMD_PG_STATE_GATE)
> @@ -1825,7 +1825,7 @@ static int vcn_v2_0_set_powergating_state(void *handle,
> ret = vcn_v2_0_start(adev);
>
> if (!ret)
> - adev->vcn.cur_state = state;
> + adev->vcn.cur_state[0] = state;
> return ret;
> }
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> index 7ab0314b27ec..09b342ad02cd 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> @@ -397,9 +397,10 @@ static int vcn_v2_5_hw_fini(void *handle)
> continue;
>
> if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
> - (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
> - RREG32_SOC15(VCN, i, mmUVD_STATUS)))
> + (adev->vcn.cur_state[i] != AMD_PG_STATE_GATE &&
> + RREG32_SOC15(VCN, i, mmUVD_STATUS))) {
> vcn_v2_5_set_powergating_state(adev, AMD_PG_STATE_GATE);
> + }
>
> if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN))
> amdgpu_irq_put(adev, &adev->vcn.inst[i].ras_poison_irq, 0);
> @@ -1832,16 +1833,18 @@ static int vcn_v2_5_set_powergating_state(void *handle,
> if (amdgpu_sriov_vf(adev))
> return 0;
>
> - if(state == adev->vcn.cur_state)
> - return 0;
> + for (int i = 0; i < adev->vcn.num_vcn_inst; ++i) {
> + if (state == adev->vcn.cur_state[i])
> + return 0;
Shouldn't this only check the first instance for the HW generations
which work with only one instance?
Could be that this becomes redundant when the function is called per
instance later on.
Regards,
Christian.
>
> - if (state == AMD_PG_STATE_GATE)
> - ret = vcn_v2_5_stop(adev);
> - else
> - ret = vcn_v2_5_start(adev);
> + if (state == AMD_PG_STATE_GATE)
> + ret = vcn_v2_5_stop(adev);
> + else
> + ret = vcn_v2_5_start(adev);
>
> - if(!ret)
> - adev->vcn.cur_state = state;
> + if (!ret)
> + adev->vcn.cur_state[i] = state;
> + }
>
> return ret;
> }
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> index 38452446fcb0..ee9a40443d65 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> @@ -430,8 +430,8 @@ static int vcn_v3_0_hw_fini(void *handle)
>
> if (!amdgpu_sriov_vf(adev)) {
> if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
> - (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
> - RREG32_SOC15(VCN, i, mmUVD_STATUS))) {
> + (adev->vcn.cur_state[i] != AMD_PG_STATE_GATE &&
> + RREG32_SOC15(VCN, i, mmUVD_STATUS))) {
> vcn_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
> }
> }
> @@ -2163,25 +2163,27 @@ static int vcn_v3_0_set_powergating_state(void *handle,
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> int ret;
>
> - /* for SRIOV, guest should not control VCN Power-gating
> - * MMSCH FW should control Power-gating and clock-gating
> - * guest should avoid touching CGC and PG
> - */
> - if (amdgpu_sriov_vf(adev)) {
> - adev->vcn.cur_state = AMD_PG_STATE_UNGATE;
> - return 0;
> - }
> + for (int i = 0; i < adev->vcn.num_vcn_inst; ++i) {
> + /* for SRIOV, guest should not control VCN Power-gating
> + * MMSCH FW should control Power-gating and clock-gating
> + * guest should avoid touching CGC and PG
> + */
> + if (amdgpu_sriov_vf(adev)) {
> + adev->vcn.cur_state[i] = AMD_PG_STATE_UNGATE;
> + return 0;
> + }
>
> - if (state == adev->vcn.cur_state)
> - return 0;
> + if (state == adev->vcn.cur_state[i])
> + return 0;
>
> - if (state == AMD_PG_STATE_GATE)
> - ret = vcn_v3_0_stop(adev);
> - else
> - ret = vcn_v3_0_start(adev);
> + if (state == AMD_PG_STATE_GATE)
> + ret = vcn_v3_0_stop(adev);
> + else
> + ret = vcn_v3_0_start(adev);
>
> - if (!ret)
> - adev->vcn.cur_state = state;
> + if (!ret)
> + adev->vcn.cur_state[i] = state;
> + }
>
> return ret;
> }
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
> index 078bb30497e0..aaecc680b631 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
> @@ -355,11 +355,12 @@ static int vcn_v4_0_hw_fini(void *handle)
> for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
> if (adev->vcn.harvest_config & (1 << i))
> continue;
> +
> if (!amdgpu_sriov_vf(adev)) {
> if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
> - (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
> - RREG32_SOC15(VCN, i, regUVD_STATUS))) {
> - vcn_v4_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
> + (adev->vcn.cur_state[i] != AMD_PG_STATE_GATE &&
> + RREG32_SOC15(VCN, i, regUVD_STATUS))) {
> + vcn_v4_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
> }
> }
> if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN))
> @@ -2040,25 +2041,27 @@ static int vcn_v4_0_set_powergating_state(void *handle, enum amd_powergating_sta
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> int ret;
>
> - /* for SRIOV, guest should not control VCN Power-gating
> - * MMSCH FW should control Power-gating and clock-gating
> - * guest should avoid touching CGC and PG
> - */
> - if (amdgpu_sriov_vf(adev)) {
> - adev->vcn.cur_state = AMD_PG_STATE_UNGATE;
> - return 0;
> - }
> + for (int i = 0; i < adev->vcn.num_vcn_inst; ++i) {
> + /* for SRIOV, guest should not control VCN Power-gating
> + * MMSCH FW should control Power-gating and clock-gating
> + * guest should avoid touching CGC and PG
> + */
> + if (amdgpu_sriov_vf(adev)) {
> + adev->vcn.cur_state[i] = AMD_PG_STATE_UNGATE;
> + return 0;
> + }
>
> - if (state == adev->vcn.cur_state)
> - return 0;
> + if (state == adev->vcn.cur_state[i])
> + return 0;
>
> - if (state == AMD_PG_STATE_GATE)
> - ret = vcn_v4_0_stop(adev);
> - else
> - ret = vcn_v4_0_start(adev);
> + if (state == AMD_PG_STATE_GATE)
> + ret = vcn_v4_0_stop(adev);
> + else
> + ret = vcn_v4_0_start(adev);
>
> - if (!ret)
> - adev->vcn.cur_state = state;
> + if (!ret)
> + adev->vcn.cur_state[i] = state;
> + }
>
> return ret;
> }
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> index be7b0bfba27a..87c04c512357 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> @@ -318,8 +318,11 @@ static int vcn_v4_0_3_hw_fini(void *handle)
>
> cancel_delayed_work_sync(&adev->vcn.idle_work);
>
> - if (adev->vcn.cur_state != AMD_PG_STATE_GATE)
> - vcn_v4_0_3_set_powergating_state(adev, AMD_PG_STATE_GATE);
> + for (int i = 0; i < adev->vcn.num_vcn_inst; ++i) {
> + if (adev->vcn.cur_state[i] != AMD_PG_STATE_GATE) {
> + vcn_v4_0_3_set_powergating_state(adev, AMD_PG_STATE_GATE);
> + }
> + }
>
> return 0;
> }
> @@ -1627,25 +1630,27 @@ static int vcn_v4_0_3_set_powergating_state(void *handle,
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> int ret;
>
> - /* for SRIOV, guest should not control VCN Power-gating
> - * MMSCH FW should control Power-gating and clock-gating
> - * guest should avoid touching CGC and PG
> - */
> - if (amdgpu_sriov_vf(adev)) {
> - adev->vcn.cur_state = AMD_PG_STATE_UNGATE;
> - return 0;
> - }
> + for (int i = 0; i < adev->vcn.num_vcn_inst; ++i) {
> + /* for SRIOV, guest should not control VCN Power-gating
> + * MMSCH FW should control Power-gating and clock-gating
> + * guest should avoid touching CGC and PG
> + */
> + if (amdgpu_sriov_vf(adev)) {
> + adev->vcn.cur_state[i] = AMD_PG_STATE_UNGATE;
> + return 0;
> + }
>
> - if (state == adev->vcn.cur_state)
> - return 0;
> + if (state == adev->vcn.cur_state[i])
> + return 0;
>
> - if (state == AMD_PG_STATE_GATE)
> - ret = vcn_v4_0_3_stop(adev);
> - else
> - ret = vcn_v4_0_3_start(adev);
> + if (state == AMD_PG_STATE_GATE)
> + ret = vcn_v4_0_3_stop(adev);
> + else
> + ret = vcn_v4_0_3_start(adev);
>
> - if (!ret)
> - adev->vcn.cur_state = state;
> + if (!ret)
> + adev->vcn.cur_state[i] = state;
> + }
>
> return ret;
> }
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
> index 0e70df04ceb9..2092360e133a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
> @@ -305,10 +305,11 @@ static int vcn_v4_0_5_hw_fini(void *handle)
> for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
> if (adev->vcn.harvest_config & (1 << i))
> continue;
> +
> if (!amdgpu_sriov_vf(adev)) {
> if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
> - (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
> - RREG32_SOC15(VCN, i, regUVD_STATUS))) {
> + (adev->vcn.cur_state[i] != AMD_PG_STATE_GATE &&
> + RREG32_SOC15(VCN, i, regUVD_STATUS))) {
> vcn_v4_0_5_set_powergating_state(adev, AMD_PG_STATE_GATE);
> }
> }
> @@ -1534,16 +1535,18 @@ static int vcn_v4_0_5_set_powergating_state(void *handle, enum amd_powergating_s
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> int ret;
>
> - if (state == adev->vcn.cur_state)
> - return 0;
> + for (int i = 0; i < adev->vcn.num_vcn_inst; ++i) {
> + if (state == adev->vcn.cur_state[i])
> + return 0;
>
> - if (state == AMD_PG_STATE_GATE)
> - ret = vcn_v4_0_5_stop(adev);
> - else
> - ret = vcn_v4_0_5_start(adev);
> + if (state == AMD_PG_STATE_GATE)
> + ret = vcn_v4_0_5_stop(adev);
> + else
> + ret = vcn_v4_0_5_start(adev);
>
> - if (!ret)
> - adev->vcn.cur_state = state;
> + if (!ret)
> + adev->vcn.cur_state[i] = state;
> + }
>
> return ret;
> }
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
> index 6b38927024d1..045ac9c8d8be 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
> @@ -269,10 +269,11 @@ static int vcn_v5_0_0_hw_fini(void *handle)
> for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
> if (adev->vcn.harvest_config & (1 << i))
> continue;
> +
> if (!amdgpu_sriov_vf(adev)) {
> if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
> - (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
> - RREG32_SOC15(VCN, i, regUVD_STATUS))) {
> + (adev->vcn.cur_state[i] != AMD_PG_STATE_GATE &&
> + RREG32_SOC15(VCN, i, regUVD_STATUS))) {
> vcn_v5_0_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
> }
> }
> @@ -1261,16 +1262,18 @@ static int vcn_v5_0_0_set_powergating_state(void *handle, enum amd_powergating_s
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> int ret;
>
> - if (state == adev->vcn.cur_state)
> - return 0;
> + for (int i = 0; i < adev->vcn.num_vcn_inst; ++i) {
> + if (state == adev->vcn.cur_state[i])
> + return 0;
>
> - if (state == AMD_PG_STATE_GATE)
> - ret = vcn_v5_0_0_stop(adev);
> - else
> - ret = vcn_v5_0_0_start(adev);
> + if (state == AMD_PG_STATE_GATE)
> + ret = vcn_v5_0_0_stop(adev);
> + else
> + ret = vcn_v5_0_0_start(adev);
>
> - if (!ret)
> - adev->vcn.cur_state = state;
> + if (!ret)
> + adev->vcn.cur_state[i] = state;
> + }
>
> return ret;
> }
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> index 449925105889..86001682e13e 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> @@ -2112,7 +2112,8 @@ static int smu_hw_fini(void *handle)
> smu_dpm_set_vpe_enable(smu, false);
> smu_dpm_set_umsch_mm_enable(smu, false);
>
> - adev->vcn.cur_state = AMD_PG_STATE_GATE;
> + for (int i = 0; i < adev->vcn.num_vcn_inst; ++i)
> + adev->vcn.cur_state[i] = AMD_PG_STATE_GATE;
> adev->jpeg.cur_state = AMD_PG_STATE_GATE;
>
> if (!smu->pm_enabled)
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH 07/18] drm/amdgpu/vcn: separate gating state by instance
2024-10-02 11:28 ` Christian König
@ 2024-10-04 18:42 ` Boyuan Zhang
0 siblings, 0 replies; 29+ messages in thread
From: Boyuan Zhang @ 2024-10-04 18:42 UTC (permalink / raw)
To: Christian König, amd-gfx, leo.liu, christian.koenig,
alexander.deucher, sunil.khatri
On 2024-10-02 07:28, Christian König wrote:
> Am 02.10.24 um 06:36 schrieb boyuan.zhang@amd.com:
>> From: Boyuan Zhang <boyuan.zhang@amd.com>
>>
>> vcn gating state should now be based on instance. For example,
>> instance 0
>> can be gated while instance 1 is ungated, or vice versa.
>>
>> Therefore, change the cur_state to be an array, so that it can track the
>> gating status for each vcn instance now.
>>
>> Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
>
> Mhm, some questions. See below.
>
>> ---
>> drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 2 +-
>> drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 6 ++--
>> drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 8 ++---
>> drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 23 +++++++------
>> drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 38 +++++++++++----------
>> drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 41 ++++++++++++-----------
>> drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 41 +++++++++++++----------
>> drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 23 +++++++------
>> drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 23 +++++++------
>> drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 3 +-
>> 10 files changed, 114 insertions(+), 94 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
>> index 2a1f3dbb14d3..f6717f780acd 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
>> @@ -308,7 +308,7 @@ struct amdgpu_vcn {
>> struct delayed_work idle_work;
>> const struct firmware *fw[AMDGPU_MAX_VCN_INSTANCES]; /* VCN
>> firmware */
>> unsigned num_enc_rings;
>> - enum amd_powergating_state cur_state;
>> + enum amd_powergating_state cur_state[AMDGPU_MAX_VCN_INSTANCES];
>> bool indirect_sram;
>> uint8_t num_vcn_inst;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
>> b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
>> index 6717ff692d8d..bafdd6d5ff24 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
>> @@ -279,7 +279,7 @@ static int vcn_v1_0_hw_fini(void *handle)
>> cancel_delayed_work_sync(&adev->vcn.idle_work);
>> if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
>> - (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
>> + (adev->vcn.cur_state[0] != AMD_PG_STATE_GATE &&
>> RREG32_SOC15(VCN, 0, mmUVD_STATUS))) {
>> vcn_v1_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
>> }
>> @@ -1813,7 +1813,7 @@ static int vcn_v1_0_set_powergating_state(void
>> *handle,
>> int ret;
>> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> - if (state == adev->vcn.cur_state)
>> + if (state == adev->vcn.cur_state[0])
>> return 0;
>> if (state == AMD_PG_STATE_GATE)
>> @@ -1822,7 +1822,7 @@ static int vcn_v1_0_set_powergating_state(void
>> *handle,
>> ret = vcn_v1_0_start(adev);
>> if (!ret)
>> - adev->vcn.cur_state = state;
>> + adev->vcn.cur_state[0] = state;
>> return ret;
>> }
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
>> b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
>> index be6998ed56bc..72e36fbaad39 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
>> @@ -316,7 +316,7 @@ static int vcn_v2_0_hw_fini(void *handle)
>> cancel_delayed_work_sync(&adev->vcn.idle_work);
>> if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
>> - (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
>> + (adev->vcn.cur_state[0] != AMD_PG_STATE_GATE &&
>> RREG32_SOC15(VCN, 0, mmUVD_STATUS)))
>> vcn_v2_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
>> @@ -1812,11 +1812,11 @@ static int
>> vcn_v2_0_set_powergating_state(void *handle,
>> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> if (amdgpu_sriov_vf(adev)) {
>> - adev->vcn.cur_state = AMD_PG_STATE_UNGATE;
>> + adev->vcn.cur_state[0] = AMD_PG_STATE_UNGATE;
>> return 0;
>> }
>> - if (state == adev->vcn.cur_state)
>> + if (state == adev->vcn.cur_state[0])
>> return 0;
>> if (state == AMD_PG_STATE_GATE)
>> @@ -1825,7 +1825,7 @@ static int vcn_v2_0_set_powergating_state(void
>> *handle,
>> ret = vcn_v2_0_start(adev);
>> if (!ret)
>> - adev->vcn.cur_state = state;
>> + adev->vcn.cur_state[0] = state;
>> return ret;
>> }
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
>> b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
>> index 7ab0314b27ec..09b342ad02cd 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
>> @@ -397,9 +397,10 @@ static int vcn_v2_5_hw_fini(void *handle)
>> continue;
>> if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
>> - (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
>> - RREG32_SOC15(VCN, i, mmUVD_STATUS)))
>> + (adev->vcn.cur_state[i] != AMD_PG_STATE_GATE &&
>> + RREG32_SOC15(VCN, i, mmUVD_STATUS))) {
>> vcn_v2_5_set_powergating_state(adev, AMD_PG_STATE_GATE);
>> + }
>> if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN))
>> amdgpu_irq_put(adev, &adev->vcn.inst[i].ras_poison_irq,
>> 0);
>> @@ -1832,16 +1833,18 @@ static int
>> vcn_v2_5_set_powergating_state(void *handle,
>> if (amdgpu_sriov_vf(adev))
>> return 0;
>> - if(state == adev->vcn.cur_state)
>> - return 0;
>> + for (int i = 0; i < adev->vcn.num_vcn_inst; ++i) {
>> + if (state == adev->vcn.cur_state[i])
>> + return 0;
>
> Shouldn't this only check the first instance for the HW generations
> which work with only one instance?
>
> Could be that this becomes redundant when the function is called per
> instance later on.
>
> Regards,
> Christian.
Yes, there are some redundant codes, removed all of them in v2.
For vcn generations with only one instance (v1.0, v2.0) always use 0 as
instance number. For vcn generations with multiple instances (v2.5,
v3.0, v4.0, v4.0.3, v4.0.5, v5.0.0) use the actual instance number.
Please check the updated v2 patch set.
Regards,
Boyuan
>
>> - if (state == AMD_PG_STATE_GATE)
>> - ret = vcn_v2_5_stop(adev);
>> - else
>> - ret = vcn_v2_5_start(adev);
>> + if (state == AMD_PG_STATE_GATE)
>> + ret = vcn_v2_5_stop(adev);
>> + else
>> + ret = vcn_v2_5_start(adev);
>> - if(!ret)
>> - adev->vcn.cur_state = state;
>> + if (!ret)
>> + adev->vcn.cur_state[i] = state;
>> + }
>> return ret;
>> }
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
>> b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
>> index 38452446fcb0..ee9a40443d65 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
>> @@ -430,8 +430,8 @@ static int vcn_v3_0_hw_fini(void *handle)
>> if (!amdgpu_sriov_vf(adev)) {
>> if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
>> - (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
>> - RREG32_SOC15(VCN, i, mmUVD_STATUS))) {
>> + (adev->vcn.cur_state[i] != AMD_PG_STATE_GATE &&
>> + RREG32_SOC15(VCN, i, mmUVD_STATUS))) {
>> vcn_v3_0_set_powergating_state(adev,
>> AMD_PG_STATE_GATE);
>> }
>> }
>> @@ -2163,25 +2163,27 @@ static int
>> vcn_v3_0_set_powergating_state(void *handle,
>> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> int ret;
>> - /* for SRIOV, guest should not control VCN Power-gating
>> - * MMSCH FW should control Power-gating and clock-gating
>> - * guest should avoid touching CGC and PG
>> - */
>> - if (amdgpu_sriov_vf(adev)) {
>> - adev->vcn.cur_state = AMD_PG_STATE_UNGATE;
>> - return 0;
>> - }
>> + for (int i = 0; i < adev->vcn.num_vcn_inst; ++i) {
>> + /* for SRIOV, guest should not control VCN Power-gating
>> + * MMSCH FW should control Power-gating and clock-gating
>> + * guest should avoid touching CGC and PG
>> + */
>> + if (amdgpu_sriov_vf(adev)) {
>> + adev->vcn.cur_state[i] = AMD_PG_STATE_UNGATE;
>> + return 0;
>> + }
>> - if (state == adev->vcn.cur_state)
>> - return 0;
>> + if (state == adev->vcn.cur_state[i])
>> + return 0;
>> - if (state == AMD_PG_STATE_GATE)
>> - ret = vcn_v3_0_stop(adev);
>> - else
>> - ret = vcn_v3_0_start(adev);
>> + if (state == AMD_PG_STATE_GATE)
>> + ret = vcn_v3_0_stop(adev);
>> + else
>> + ret = vcn_v3_0_start(adev);
>> - if (!ret)
>> - adev->vcn.cur_state = state;
>> + if (!ret)
>> + adev->vcn.cur_state[i] = state;
>> + }
>> return ret;
>> }
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
>> b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
>> index 078bb30497e0..aaecc680b631 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
>> @@ -355,11 +355,12 @@ static int vcn_v4_0_hw_fini(void *handle)
>> for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
>> if (adev->vcn.harvest_config & (1 << i))
>> continue;
>> +
>> if (!amdgpu_sriov_vf(adev)) {
>> if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
>> - (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
>> - RREG32_SOC15(VCN, i, regUVD_STATUS))) {
>> - vcn_v4_0_set_powergating_state(adev,
>> AMD_PG_STATE_GATE);
>> + (adev->vcn.cur_state[i] != AMD_PG_STATE_GATE &&
>> + RREG32_SOC15(VCN, i, regUVD_STATUS))) {
>> + vcn_v4_0_set_powergating_state(adev,
>> AMD_PG_STATE_GATE);
>> }
>> }
>> if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN))
>> @@ -2040,25 +2041,27 @@ static int
>> vcn_v4_0_set_powergating_state(void *handle, enum amd_powergating_sta
>> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> int ret;
>> - /* for SRIOV, guest should not control VCN Power-gating
>> - * MMSCH FW should control Power-gating and clock-gating
>> - * guest should avoid touching CGC and PG
>> - */
>> - if (amdgpu_sriov_vf(adev)) {
>> - adev->vcn.cur_state = AMD_PG_STATE_UNGATE;
>> - return 0;
>> - }
>> + for (int i = 0; i < adev->vcn.num_vcn_inst; ++i) {
>> + /* for SRIOV, guest should not control VCN Power-gating
>> + * MMSCH FW should control Power-gating and clock-gating
>> + * guest should avoid touching CGC and PG
>> + */
>> + if (amdgpu_sriov_vf(adev)) {
>> + adev->vcn.cur_state[i] = AMD_PG_STATE_UNGATE;
>> + return 0;
>> + }
>> - if (state == adev->vcn.cur_state)
>> - return 0;
>> + if (state == adev->vcn.cur_state[i])
>> + return 0;
>> - if (state == AMD_PG_STATE_GATE)
>> - ret = vcn_v4_0_stop(adev);
>> - else
>> - ret = vcn_v4_0_start(adev);
>> + if (state == AMD_PG_STATE_GATE)
>> + ret = vcn_v4_0_stop(adev);
>> + else
>> + ret = vcn_v4_0_start(adev);
>> - if (!ret)
>> - adev->vcn.cur_state = state;
>> + if (!ret)
>> + adev->vcn.cur_state[i] = state;
>> + }
>> return ret;
>> }
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
>> b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
>> index be7b0bfba27a..87c04c512357 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
>> @@ -318,8 +318,11 @@ static int vcn_v4_0_3_hw_fini(void *handle)
>> cancel_delayed_work_sync(&adev->vcn.idle_work);
>> - if (adev->vcn.cur_state != AMD_PG_STATE_GATE)
>> - vcn_v4_0_3_set_powergating_state(adev, AMD_PG_STATE_GATE);
>> + for (int i = 0; i < adev->vcn.num_vcn_inst; ++i) {
>> + if (adev->vcn.cur_state[i] != AMD_PG_STATE_GATE) {
>> + vcn_v4_0_3_set_powergating_state(adev, AMD_PG_STATE_GATE);
>> + }
>> + }
>> return 0;
>> }
>> @@ -1627,25 +1630,27 @@ static int
>> vcn_v4_0_3_set_powergating_state(void *handle,
>> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> int ret;
>> - /* for SRIOV, guest should not control VCN Power-gating
>> - * MMSCH FW should control Power-gating and clock-gating
>> - * guest should avoid touching CGC and PG
>> - */
>> - if (amdgpu_sriov_vf(adev)) {
>> - adev->vcn.cur_state = AMD_PG_STATE_UNGATE;
>> - return 0;
>> - }
>> + for (int i = 0; i < adev->vcn.num_vcn_inst; ++i) {
>> + /* for SRIOV, guest should not control VCN Power-gating
>> + * MMSCH FW should control Power-gating and clock-gating
>> + * guest should avoid touching CGC and PG
>> + */
>> + if (amdgpu_sriov_vf(adev)) {
>> + adev->vcn.cur_state[i] = AMD_PG_STATE_UNGATE;
>> + return 0;
>> + }
>> - if (state == adev->vcn.cur_state)
>> - return 0;
>> + if (state == adev->vcn.cur_state[i])
>> + return 0;
>> - if (state == AMD_PG_STATE_GATE)
>> - ret = vcn_v4_0_3_stop(adev);
>> - else
>> - ret = vcn_v4_0_3_start(adev);
>> + if (state == AMD_PG_STATE_GATE)
>> + ret = vcn_v4_0_3_stop(adev);
>> + else
>> + ret = vcn_v4_0_3_start(adev);
>> - if (!ret)
>> - adev->vcn.cur_state = state;
>> + if (!ret)
>> + adev->vcn.cur_state[i] = state;
>> + }
>> return ret;
>> }
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
>> b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
>> index 0e70df04ceb9..2092360e133a 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
>> @@ -305,10 +305,11 @@ static int vcn_v4_0_5_hw_fini(void *handle)
>> for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
>> if (adev->vcn.harvest_config & (1 << i))
>> continue;
>> +
>> if (!amdgpu_sriov_vf(adev)) {
>> if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
>> - (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
>> - RREG32_SOC15(VCN, i, regUVD_STATUS))) {
>> + (adev->vcn.cur_state[i] != AMD_PG_STATE_GATE &&
>> + RREG32_SOC15(VCN, i, regUVD_STATUS))) {
>> vcn_v4_0_5_set_powergating_state(adev,
>> AMD_PG_STATE_GATE);
>> }
>> }
>> @@ -1534,16 +1535,18 @@ static int
>> vcn_v4_0_5_set_powergating_state(void *handle, enum amd_powergating_s
>> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> int ret;
>> - if (state == adev->vcn.cur_state)
>> - return 0;
>> + for (int i = 0; i < adev->vcn.num_vcn_inst; ++i) {
>> + if (state == adev->vcn.cur_state[i])
>> + return 0;
>> - if (state == AMD_PG_STATE_GATE)
>> - ret = vcn_v4_0_5_stop(adev);
>> - else
>> - ret = vcn_v4_0_5_start(adev);
>> + if (state == AMD_PG_STATE_GATE)
>> + ret = vcn_v4_0_5_stop(adev);
>> + else
>> + ret = vcn_v4_0_5_start(adev);
>> - if (!ret)
>> - adev->vcn.cur_state = state;
>> + if (!ret)
>> + adev->vcn.cur_state[i] = state;
>> + }
>> return ret;
>> }
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
>> b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
>> index 6b38927024d1..045ac9c8d8be 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
>> @@ -269,10 +269,11 @@ static int vcn_v5_0_0_hw_fini(void *handle)
>> for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
>> if (adev->vcn.harvest_config & (1 << i))
>> continue;
>> +
>> if (!amdgpu_sriov_vf(adev)) {
>> if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
>> - (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
>> - RREG32_SOC15(VCN, i, regUVD_STATUS))) {
>> + (adev->vcn.cur_state[i] != AMD_PG_STATE_GATE &&
>> + RREG32_SOC15(VCN, i, regUVD_STATUS))) {
>> vcn_v5_0_0_set_powergating_state(adev,
>> AMD_PG_STATE_GATE);
>> }
>> }
>> @@ -1261,16 +1262,18 @@ static int
>> vcn_v5_0_0_set_powergating_state(void *handle, enum amd_powergating_s
>> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> int ret;
>> - if (state == adev->vcn.cur_state)
>> - return 0;
>> + for (int i = 0; i < adev->vcn.num_vcn_inst; ++i) {
>> + if (state == adev->vcn.cur_state[i])
>> + return 0;
>> - if (state == AMD_PG_STATE_GATE)
>> - ret = vcn_v5_0_0_stop(adev);
>> - else
>> - ret = vcn_v5_0_0_start(adev);
>> + if (state == AMD_PG_STATE_GATE)
>> + ret = vcn_v5_0_0_stop(adev);
>> + else
>> + ret = vcn_v5_0_0_start(adev);
>> - if (!ret)
>> - adev->vcn.cur_state = state;
>> + if (!ret)
>> + adev->vcn.cur_state[i] = state;
>> + }
>> return ret;
>> }
>> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
>> b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
>> index 449925105889..86001682e13e 100644
>> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
>> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
>> @@ -2112,7 +2112,8 @@ static int smu_hw_fini(void *handle)
>> smu_dpm_set_vpe_enable(smu, false);
>> smu_dpm_set_umsch_mm_enable(smu, false);
>> - adev->vcn.cur_state = AMD_PG_STATE_GATE;
>> + for (int i = 0; i < adev->vcn.num_vcn_inst; ++i)
>> + adev->vcn.cur_state[i] = AMD_PG_STATE_GATE;
>> adev->jpeg.cur_state = AMD_PG_STATE_GATE;
>> if (!smu->pm_enabled)
>
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH 08/18] drm/amdgpu/vcn: separate idle work by instance
2024-10-02 4:36 [PATCH 00/18] Separating vcn power management by instance boyuan.zhang
` (6 preceding siblings ...)
2024-10-02 4:36 ` [PATCH 07/18] drm/amdgpu/vcn: separate gating state " boyuan.zhang
@ 2024-10-02 4:36 ` boyuan.zhang
2024-10-02 4:36 ` [PATCH 09/18] drm/amdgpu: pass ip_block in set_powergating_state boyuan.zhang
` (9 subsequent siblings)
17 siblings, 0 replies; 29+ messages in thread
From: boyuan.zhang @ 2024-10-02 4:36 UTC (permalink / raw)
To: amd-gfx, leo.liu, christian.koenig, alexander.deucher,
sunil.khatri
Cc: Boyuan Zhang
From: Boyuan Zhang <boyuan.zhang@amd.com>
Previously idle working handling is for all VCN instances. As a result, when one
of the instance finishes its job, the idle work can't be triggered if the other
instance is still busy.
Now, move the idle_work from amdgpu_vcn to amdgpu_vcn_inst, in order to
track work by vcn instance. Add work_inst to track the instance number
that the work belongs to. As a result, the idle work can now be triggered
once the job is done on one of the vcn instance, and no need to consider
the work on the other vcn instance.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 66 ++++++++++++------------
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 4 +-
drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c | 2 +-
drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c | 2 +-
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 14 ++---
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 3 +-
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 3 +-
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 3 +-
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 6 ++-
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 3 +-
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 3 +-
17 files changed, 66 insertions(+), 55 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 43f44cc201cb..28c5e15d166d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -118,7 +118,11 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
unsigned int fw_shared_size, log_offset;
int i, r;
- INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler);
+ for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
+ adev->vcn.inst[i].adev = adev;
+ adev->vcn.inst[i].work_inst = i;
+ INIT_DELAYED_WORK(&adev->vcn.inst[i].idle_work, amdgpu_vcn_idle_work_handler);
+ }
mutex_init(&adev->vcn.vcn_pg_lock);
mutex_init(&adev->vcn.vcn1_jpeg1_workaround);
atomic_set(&adev->vcn.total_submission_cnt, 0);
@@ -302,7 +306,8 @@ int amdgpu_vcn_suspend(struct amdgpu_device *adev)
bool in_ras_intr = amdgpu_ras_intr_triggered();
- cancel_delayed_work_sync(&adev->vcn.idle_work);
+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i)
+ cancel_delayed_work_sync(&adev->vcn.inst[i].idle_work);
/* err_event_athub will corrupt VCPU buffer, so we need to
* restore fw data and clear buffer in amdgpu_vcn_resume() */
@@ -376,46 +381,43 @@ int amdgpu_vcn_resume(struct amdgpu_device *adev)
static void amdgpu_vcn_idle_work_handler(struct work_struct *work)
{
- struct amdgpu_device *adev =
- container_of(work, struct amdgpu_device, vcn.idle_work.work);
- unsigned int fences = 0, fence[AMDGPU_MAX_VCN_INSTANCES] = {0};
- unsigned int i, j;
+ struct amdgpu_vcn_inst *vcn_inst =
+ container_of(work, struct amdgpu_vcn_inst, idle_work.work);
+ struct amdgpu_device *adev = vcn_inst->adev;
+ unsigned int inst = vcn_inst->work_inst;
+ unsigned int fence = 0;
+ unsigned int i;
int r = 0;
- for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
- if (adev->vcn.harvest_config & (1 << j))
- continue;
-
- for (i = 0; i < adev->vcn.num_enc_rings; ++i)
- fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_enc[i]);
-
- /* Only set DPG pause for VCN3 or below, VCN4 and above will be handled by FW */
- if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG &&
- !adev->vcn.using_unified_queue) {
- struct dpg_pause_state new_state;
-
- if (fence[j] ||
- unlikely(atomic_read(&adev->vcn.inst[j].dpg_enc_submission_cnt)))
- new_state.fw_based = VCN_DPG_STATE__PAUSE;
- else
- new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return;
- adev->vcn.pause_dpg_mode(adev, j, &new_state);
- }
+ for (i = 0; i < adev->vcn.num_enc_rings; ++i)
+ fence += amdgpu_fence_count_emitted(&adev->vcn.inst[inst].ring_enc[i]);
- fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_dec);
- fences += fence[j];
+ /* Only set DPG pause for VCN3 or below, VCN4 and above will be handled by FW */
+ if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG &&
+ !adev->vcn.using_unified_queue) {
+ struct dpg_pause_state new_state;
+ if (fence ||
+ unlikely(atomic_read(&adev->vcn.inst[inst].dpg_enc_submission_cnt)))
+ new_state.fw_based = VCN_DPG_STATE__PAUSE;
+ else
+ new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
+ adev->vcn.pause_dpg_mode(adev, inst, &new_state);
}
- if (!fences && !atomic_read(&adev->vcn.total_submission_cnt)) {
+ fence += amdgpu_fence_count_emitted(&adev->vcn.inst[inst].ring_dec);
+
+ if (!fence && !atomic_read(&adev->vcn.total_submission_cnt)) {
amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
AMD_PG_STATE_GATE);
r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO,
- false);
+ false);
if (r)
dev_warn(adev->dev, "(%d) failed to disable video power profile mode\n", r);
} else {
- schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
+ schedule_delayed_work(&adev->vcn.inst[inst].idle_work, VCN_IDLE_TIMEOUT);
}
}
@@ -426,7 +428,7 @@ void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
atomic_inc(&adev->vcn.total_submission_cnt);
- if (!cancel_delayed_work_sync(&adev->vcn.idle_work)) {
+ if (!cancel_delayed_work_sync(&adev->vcn.inst[ring->me].idle_work)) {
r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO,
true);
if (r)
@@ -475,7 +477,7 @@ void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring)
atomic_dec(&ring->adev->vcn.total_submission_cnt);
- schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
+ schedule_delayed_work(&ring->adev->vcn.inst[ring->me].idle_work, VCN_IDLE_TIMEOUT);
}
int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index f6717f780acd..5733dda64713 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -279,6 +279,7 @@ struct amdgpu_vcn_fw_shared {
};
struct amdgpu_vcn_inst {
+ struct amdgpu_device *adev;
struct amdgpu_bo *vcpu_bo;
void *cpu_addr;
uint64_t gpu_addr;
@@ -297,6 +298,8 @@ struct amdgpu_vcn_inst {
atomic_t dpg_enc_submission_cnt;
struct amdgpu_vcn_fw_shared fw_shared;
uint8_t aid_id;
+ struct delayed_work idle_work;
+ uint8_t work_inst;
};
struct amdgpu_vcn_ras {
@@ -305,7 +308,6 @@ struct amdgpu_vcn_ras {
struct amdgpu_vcn {
unsigned fw_version;
- struct delayed_work idle_work;
const struct firmware *fw[AMDGPU_MAX_VCN_INSTANCES]; /* VCN firmware */
unsigned num_enc_rings;
enum amd_powergating_state cur_state[AMDGPU_MAX_VCN_INSTANCES];
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c
index 33da094f1a7d..285935df3cb5 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c
@@ -604,7 +604,7 @@ static void jpeg_v1_0_set_irq_funcs(struct amdgpu_device *adev)
static void jpeg_v1_0_ring_begin_use(struct amdgpu_ring *ring)
{
struct amdgpu_device *adev = ring->adev;
- bool set_clocks = !cancel_delayed_work_sync(&adev->vcn.idle_work);
+ bool set_clocks = !cancel_delayed_work_sync(&adev->vcn.inst[0].idle_work);
int cnt = 0;
mutex_lock(&adev->vcn.vcn1_jpeg1_workaround);
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
index b7aa37b3a717..1bd1e348dab7 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
@@ -150,7 +150,7 @@ static int jpeg_v2_0_hw_fini(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- cancel_delayed_work_sync(&adev->vcn.idle_work);
+ cancel_delayed_work_sync(&adev->vcn.inst[0].idle_work);
if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS))
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
index a0cddb37a541..2f397969fe0d 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
@@ -211,7 +211,7 @@ static int jpeg_v2_5_hw_fini(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
int i;
- cancel_delayed_work_sync(&adev->vcn.idle_work);
+ cancel_delayed_work_sync(&adev->vcn.inst[0].idle_work);
for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
if (adev->jpeg.harvest_config & (1 << i))
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
index 45ffea1c759b..3b8c42516ba8 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
@@ -164,7 +164,7 @@ static int jpeg_v3_0_hw_fini(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- cancel_delayed_work_sync(&adev->vcn.idle_work);
+ cancel_delayed_work_sync(&adev->vcn.inst[0].idle_work);
if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS))
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
index 3f91d79c07f8..774cfcbaa628 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
@@ -195,7 +195,7 @@ static int jpeg_v4_0_hw_fini(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- cancel_delayed_work_sync(&adev->vcn.idle_work);
+ cancel_delayed_work_sync(&adev->vcn.inst[0].idle_work);
if (!amdgpu_sriov_vf(adev)) {
if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS))
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
index ad4030ccd917..13128bdd45a9 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
@@ -219,7 +219,7 @@ static int jpeg_v4_0_5_hw_fini(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
int i;
- cancel_delayed_work_sync(&adev->vcn.idle_work);
+ cancel_delayed_work_sync(&adev->vcn.inst[0].idle_work);
for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
if (adev->jpeg.harvest_config & (1 << i))
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
index 85fb1a5265a8..e2450f3b1eb4 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
@@ -161,7 +161,7 @@ static int jpeg_v5_0_0_hw_fini(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- cancel_delayed_work_sync(&adev->vcn.idle_work);
+ cancel_delayed_work_sync(&adev->vcn.inst[0].idle_work);
if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS))
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index bafdd6d5ff24..38497ba60292 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -149,7 +149,7 @@ static int vcn_v1_0_sw_init(struct amdgpu_ip_block *ip_block)
return r;
/* Override the work func */
- adev->vcn.idle_work.work.func = vcn_v1_0_idle_work_handler;
+ adev->vcn.inst[0].idle_work.work.func = vcn_v1_0_idle_work_handler;
amdgpu_vcn_setup_ucode(adev);
@@ -276,7 +276,7 @@ static int vcn_v1_0_hw_fini(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- cancel_delayed_work_sync(&adev->vcn.idle_work);
+ cancel_delayed_work_sync(&adev->vcn.inst[0].idle_work);
if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
(adev->vcn.cur_state[0] != AMD_PG_STATE_GATE &&
@@ -300,7 +300,7 @@ static int vcn_v1_0_suspend(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
bool idle_work_unexecuted;
- idle_work_unexecuted = cancel_delayed_work_sync(&adev->vcn.idle_work);
+ idle_work_unexecuted = cancel_delayed_work_sync(&adev->vcn.inst[0].idle_work);
if (idle_work_unexecuted) {
if (adev->pm.dpm_enabled)
amdgpu_dpm_enable_uvd(adev, false);
@@ -1829,7 +1829,7 @@ static int vcn_v1_0_set_powergating_state(void *handle,
static void vcn_v1_0_idle_work_handler(struct work_struct *work)
{
struct amdgpu_device *adev =
- container_of(work, struct amdgpu_device, vcn.idle_work.work);
+ container_of(work, struct amdgpu_device, vcn.inst[0].idle_work.work);
unsigned int fences = 0, i;
for (i = 0; i < adev->vcn.num_enc_rings; ++i)
@@ -1862,14 +1862,14 @@ static void vcn_v1_0_idle_work_handler(struct work_struct *work)
amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
AMD_PG_STATE_GATE);
} else {
- schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
+ schedule_delayed_work(&adev->vcn.inst[0].idle_work, VCN_IDLE_TIMEOUT);
}
}
static void vcn_v1_0_ring_begin_use(struct amdgpu_ring *ring)
{
struct amdgpu_device *adev = ring->adev;
- bool set_clocks = !cancel_delayed_work_sync(&adev->vcn.idle_work);
+ bool set_clocks = !cancel_delayed_work_sync(&adev->vcn.inst[0].idle_work);
mutex_lock(&adev->vcn.vcn1_jpeg1_workaround);
@@ -1921,7 +1921,7 @@ void vcn_v1_0_set_pg_for_begin_use(struct amdgpu_ring *ring, bool set_clocks)
void vcn_v1_0_ring_end_use(struct amdgpu_ring *ring)
{
- schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
+ schedule_delayed_work(&ring->adev->vcn.inst[0].idle_work, VCN_IDLE_TIMEOUT);
mutex_unlock(&ring->adev->vcn.vcn1_jpeg1_workaround);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index 72e36fbaad39..37ace062788b 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -313,7 +313,7 @@ static int vcn_v2_0_hw_fini(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- cancel_delayed_work_sync(&adev->vcn.idle_work);
+ cancel_delayed_work_sync(&adev->vcn.inst[0].idle_work);
if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
(adev->vcn.cur_state[0] != AMD_PG_STATE_GATE &&
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
index 09b342ad02cd..aa1c96571a21 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
@@ -390,7 +390,8 @@ static int vcn_v2_5_hw_fini(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
int i;
- cancel_delayed_work_sync(&adev->vcn.idle_work);
+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i)
+ cancel_delayed_work_sync(&adev->vcn.inst[i].idle_work);
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
if (adev->vcn.harvest_config & (1 << i))
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index ee9a40443d65..52c8e7767a6a 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -422,7 +422,8 @@ static int vcn_v3_0_hw_fini(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
int i;
- cancel_delayed_work_sync(&adev->vcn.idle_work);
+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i)
+ cancel_delayed_work_sync(&adev->vcn.inst[i].idle_work);
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
if (adev->vcn.harvest_config & (1 << i))
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
index aaecc680b631..9b18810f00e6 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
@@ -350,7 +350,8 @@ static int vcn_v4_0_hw_fini(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
int i;
- cancel_delayed_work_sync(&adev->vcn.idle_work);
+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i)
+ cancel_delayed_work_sync(&adev->vcn.inst[i].idle_work);
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
if (adev->vcn.harvest_config & (1 << i))
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
index 87c04c512357..fb425e27ab89 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
@@ -315,10 +315,12 @@ static int vcn_v4_0_3_hw_init(void *handle)
static int vcn_v4_0_3_hw_fini(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ int i;
- cancel_delayed_work_sync(&adev->vcn.idle_work);
+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i)
+ cancel_delayed_work_sync(&adev->vcn.inst[i].idle_work);
- for (int i = 0; i < adev->vcn.num_vcn_inst; ++i) {
+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
if (adev->vcn.cur_state[i] != AMD_PG_STATE_GATE) {
vcn_v4_0_3_set_powergating_state(adev, AMD_PG_STATE_GATE);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
index 2092360e133a..0c093d23a73f 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
@@ -300,7 +300,8 @@ static int vcn_v4_0_5_hw_fini(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
int i;
- cancel_delayed_work_sync(&adev->vcn.idle_work);
+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i)
+ cancel_delayed_work_sync(&adev->vcn.inst[i].idle_work);
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
if (adev->vcn.harvest_config & (1 << i))
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
index 045ac9c8d8be..b9eb12d2cd1b 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
@@ -264,7 +264,8 @@ static int vcn_v5_0_0_hw_fini(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
int i;
- cancel_delayed_work_sync(&adev->vcn.idle_work);
+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i)
+ cancel_delayed_work_sync(&adev->vcn.inst[i].idle_work);
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
if (adev->vcn.harvest_config & (1 << i))
--
2.34.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH 09/18] drm/amdgpu: pass ip_block in set_powergating_state
2024-10-02 4:36 [PATCH 00/18] Separating vcn power management by instance boyuan.zhang
` (7 preceding siblings ...)
2024-10-02 4:36 ` [PATCH 08/18] drm/amdgpu/vcn: separate idle work " boyuan.zhang
@ 2024-10-02 4:36 ` boyuan.zhang
2024-10-02 11:41 ` Christian König
2024-10-02 4:36 ` [PATCH 10/18] drm/amdgpu: add ip block with instance boyuan.zhang
` (8 subsequent siblings)
17 siblings, 1 reply; 29+ messages in thread
From: boyuan.zhang @ 2024-10-02 4:36 UTC (permalink / raw)
To: amd-gfx, leo.liu, christian.koenig, alexander.deucher,
sunil.khatri
Cc: Boyuan Zhang
From: Boyuan Zhang <boyuan.zhang@amd.com>
Pass ip_block instead of adev in set_powergating_state callback function.
Modify set_powergating_state ip functions for all correspoding ip blocks.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/cik.c | 2 +-
drivers/gpu/drm/amd/amdgpu/cik_ih.c | 2 +-
drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 2 +-
drivers/gpu/drm/amd/amdgpu/cz_ih.c | 2 +-
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 6 +++---
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 2 +-
drivers/gpu/drm/amd/amdgpu/ih_v6_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/ih_v6_1.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/ih_v7_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 8 ++++----
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c | 8 ++++----
drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c | 8 ++++----
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c | 8 ++++----
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 8 ++++----
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c | 8 ++++----
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c | 8 ++++----
drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 2 +-
drivers/gpu/drm/amd/amdgpu/nv.c | 2 +-
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 2 +-
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 2 +-
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 2 +-
drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/si.c | 2 +-
drivers/gpu/drm/amd/amdgpu/si_dma.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/si_ih.c | 2 +-
drivers/gpu/drm/amd/amdgpu/soc15.c | 2 +-
drivers/gpu/drm/amd/amdgpu/soc21.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/soc24.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 2 +-
drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c | 2 +-
drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 9 +++++----
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 8 ++++----
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 8 ++++----
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 8 ++++----
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 9 +++++----
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 8 ++++----
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 9 +++++----
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 9 +++++----
drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 2 +-
drivers/gpu/drm/amd/amdgpu/vega20_ih.c | 2 +-
drivers/gpu/drm/amd/amdgpu/vi.c | 2 +-
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
drivers/gpu/drm/amd/include/amd_shared.h | 2 +-
drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c | 2 +-
drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 2 +-
drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c | 2 +-
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 2 +-
82 files changed, 155 insertions(+), 151 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
index 436f24d6bd83..192c5c0926a1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
@@ -606,10 +606,10 @@ static int acp_set_clockgating_state(void *handle,
return 0;
}
-static int acp_set_powergating_state(void *handle,
+static int acp_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
bool enable = (state == AMD_PG_STATE_GATE);
amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, enable);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index b545940e512b..c074db65f196 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -724,7 +724,7 @@ void amdgpu_amdkfd_set_compute_idle(struct amdgpu_device *adev, bool idle)
/* Disable GFXOFF and PG. Temporary workaround
* to fix some compute applications issue on GFX9.
*/
- adev->ip_blocks[AMD_IP_BLOCK_TYPE_GFX].version->funcs->set_powergating_state((void *)adev, state);
+ adev->ip_blocks[AMD_IP_BLOCK_TYPE_GFX].version->funcs->set_powergating_state((void *)&adev->ip_blocks[AMD_IP_BLOCK_TYPE_GFX], state);
}
amdgpu_dpm_switch_power_profile(adev,
PP_SMC_POWER_PROFILE_COMPUTE,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 1e47655e02c6..263f25ac2d63 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2154,7 +2154,7 @@ int amdgpu_device_ip_set_powergating_state(void *dev,
if (!adev->ip_blocks[i].version->funcs->set_powergating_state)
continue;
r = adev->ip_blocks[i].version->funcs->set_powergating_state(
- (void *)adev, state);
+ (void *)&adev->ip_blocks[i], state);
if (r)
DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n",
adev->ip_blocks[i].version->funcs->name, r);
@@ -3128,7 +3128,7 @@ int amdgpu_device_set_pg_state(struct amdgpu_device *adev,
adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG &&
adev->ip_blocks[i].version->funcs->set_powergating_state) {
/* enable powergating to save power */
- r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev,
+ r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)&adev->ip_blocks[i],
state);
if (r) {
DRM_ERROR("set_powergating_state(gate) of IP block <%s> failed %d\n",
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c
index e90b5f807440..38f9a5a5d6ca 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c
@@ -171,7 +171,7 @@ static int isp_set_clockgating_state(void *handle,
return 0;
}
-static int isp_set_powergating_state(void *handle,
+static int isp_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 02fad4dad7c1..0fa2fe6e5487 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -3793,7 +3793,7 @@ static int psp_set_clockgating_state(void *handle,
return 0;
}
-static int psp_set_powergating_state(void *handle,
+static int psp_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
index af274e6b8422..bef7636228f6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
@@ -648,7 +648,7 @@ static int amdgpu_vkms_set_clockgating_state(void *handle,
return 0;
}
-static int amdgpu_vkms_set_powergating_state(void *handle,
+static int amdgpu_vkms_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c
index 1b4c60231596..d2700025a6b1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c
@@ -646,10 +646,10 @@ static int vpe_set_clockgating_state(void *handle,
return 0;
}
-static int vpe_set_powergating_state(void *handle,
+static int vpe_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
struct amdgpu_vpe *vpe = &adev->vpe;
if (!adev->pm.dpm_enabled)
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index b39944e3ac68..3c62f0b55897 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -2189,7 +2189,7 @@ static int cik_common_set_clockgating_state(void *handle,
return 0;
}
-static int cik_common_set_powergating_state(void *handle,
+static int cik_common_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
index 612330f40447..22ba98087a66 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
@@ -414,7 +414,7 @@ static int cik_ih_set_clockgating_state(void *handle,
return 0;
}
-static int cik_ih_set_powergating_state(void *handle,
+static int cik_ih_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index 8706855d681b..ae91bbd83eb0 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -1208,7 +1208,7 @@ static int cik_sdma_set_clockgating_state(void *handle,
return 0;
}
-static int cik_sdma_set_powergating_state(void *handle,
+static int cik_sdma_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
index 12a55f1e0e1f..155429900d28 100644
--- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
@@ -411,7 +411,7 @@ static int cz_ih_set_clockgating_state(void *handle,
return 0;
}
-static int cz_ih_set_powergating_state(void *handle,
+static int cz_ih_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
// TODO
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index 6f81621649d6..4b8763bfa5f5 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -3313,7 +3313,7 @@ static int dce_v10_0_set_clockgating_state(void *handle,
return 0;
}
-static int dce_v10_0_set_powergating_state(void *handle,
+static int dce_v10_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index b1afe4b837a7..55b66882c4dd 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -3445,7 +3445,7 @@ static int dce_v11_0_set_clockgating_state(void *handle,
return 0;
}
-static int dce_v11_0_set_powergating_state(void *handle,
+static int dce_v11_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
index a6bbeb3bde3b..efcfdceba72c 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
@@ -3135,7 +3135,7 @@ static int dce_v6_0_set_clockgating_state(void *handle,
return 0;
}
-static int dce_v6_0_set_powergating_state(void *handle,
+static int dce_v6_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
index 0b57e22a7c95..38d2ac9aac8d 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
@@ -3223,7 +3223,7 @@ static int dce_v8_0_set_clockgating_state(void *handle,
return 0;
}
-static int dce_v8_0_set_powergating_state(void *handle,
+static int dce_v8_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index c544ea2aea6e..7c4b8ff7ae2e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -3673,7 +3673,7 @@ static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev,
unsigned int vmid);
-static int gfx_v10_0_set_powergating_state(void *handle,
+static int gfx_v10_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state);
static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
{
@@ -8319,10 +8319,10 @@ static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = {
.is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range,
};
-static int gfx_v10_0_set_powergating_state(void *handle,
+static int gfx_v10_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
bool enable = (state == AMD_PG_STATE_GATE);
if (amdgpu_sriov_vf(adev))
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index a0f80cc993cf..a7d5343dba2a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -5402,10 +5402,10 @@ static void gfx_v11_cntl_pg(struct amdgpu_device *adev, bool enable)
amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
}
-static int gfx_v11_0_set_powergating_state(void *handle,
+static int gfx_v11_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
bool enable = (state == AMD_PG_STATE_GATE);
if (amdgpu_sriov_vf(adev))
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
index 63e1a2803503..0b88f41523d5 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
@@ -3846,10 +3846,10 @@ static void gfx_v12_cntl_pg(struct amdgpu_device *adev, bool enable)
}
#endif
-static int gfx_v12_0_set_powergating_state(void *handle,
+static int gfx_v12_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
bool enable = (state == AMD_PG_STATE_GATE);
if (amdgpu_sriov_vf(adev))
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index 60579b3029b4..e644ec23252f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -3404,11 +3404,11 @@ static int gfx_v6_0_set_clockgating_state(void *handle,
return 0;
}
-static int gfx_v6_0_set_powergating_state(void *handle,
+static int gfx_v6_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
bool gate = false;
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
if (state == AMD_PG_STATE_GATE)
gate = true;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 990e7de8da25..4e1be0057e6f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -4873,11 +4873,11 @@ static int gfx_v7_0_set_clockgating_state(void *handle,
return 0;
}
-static int gfx_v7_0_set_powergating_state(void *handle,
+static int gfx_v7_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
bool gate = false;
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
if (state == AMD_PG_STATE_GATE)
gate = true;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 6864219987e9..d6a1cc898209 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -5359,10 +5359,10 @@ static void cz_update_gfx_cg_power_gating(struct amdgpu_device *adev,
}
}
-static int gfx_v8_0_set_powergating_state(void *handle,
+static int gfx_v8_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
bool enable = (state == AMD_PG_STATE_GATE);
if (amdgpu_sriov_vf(adev))
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 99334afb7aae..5d3e7a07a81d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -5214,10 +5214,10 @@ static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = {
.is_rlcg_access_range = gfx_v9_0_is_rlcg_access_range,
};
-static int gfx_v9_0_set_powergating_state(void *handle,
+static int gfx_v9_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
bool enable = (state == AMD_PG_STATE_GATE);
switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index 81bd4ca4fba5..b4d101b642b6 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
@@ -2760,7 +2760,7 @@ static const struct amdgpu_rlc_funcs gfx_v9_4_3_rlc_funcs = {
.is_rlcg_access_range = gfx_v9_4_3_is_rlcg_access_range,
};
-static int gfx_v9_4_3_set_powergating_state(void *handle,
+static int gfx_v9_4_3_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index 8e51c7e4e8c8..d7af95de9703 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -1136,7 +1136,7 @@ static void gmc_v10_0_get_clockgating_state(void *handle, u64 *flags)
athub_v2_0_get_clockgating(adev, flags);
}
-static int gmc_v10_0_set_powergating_state(void *handle,
+static int gmc_v10_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
index 2fc69cdf8843..53841d7287b7 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
@@ -1023,7 +1023,7 @@ static void gmc_v11_0_get_clockgating_state(void *handle, u64 *flags)
athub_v3_0_get_clockgating(adev, flags);
}
-static int gmc_v11_0_set_powergating_state(void *handle,
+static int gmc_v11_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
index 3cbb5824a378..ceae0cbc7919 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
@@ -1007,7 +1007,7 @@ static void gmc_v12_0_get_clockgating_state(void *handle, u64 *flags)
athub_v4_1_0_get_clockgating(adev, flags);
}
-static int gmc_v12_0_set_powergating_state(void *handle,
+static int gmc_v12_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index 82a097d32f28..1766f379fcb0 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -1088,7 +1088,7 @@ static int gmc_v6_0_set_clockgating_state(void *handle,
return 0;
}
-static int gmc_v6_0_set_powergating_state(void *handle,
+static int gmc_v6_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index ad9bad951cc6..9269bbf7b698 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -1330,7 +1330,7 @@ static int gmc_v7_0_set_clockgating_state(void *handle,
return 0;
}
-static int gmc_v7_0_set_powergating_state(void *handle,
+static int gmc_v7_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 47ba4480b757..795cd57438de 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -1672,7 +1672,7 @@ static int gmc_v8_0_set_clockgating_state(void *handle,
return 0;
}
-static int gmc_v8_0_set_powergating_state(void *handle,
+static int gmc_v8_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 1d0eb31d7b72..c6aa236300a1 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -2488,7 +2488,7 @@ static void gmc_v9_0_get_clockgating_state(void *handle, u64 *flags)
athub_v1_0_get_clockgating(adev, flags);
}
-static int gmc_v9_0_set_powergating_state(void *handle,
+static int gmc_v9_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
index 6210fa17eeca..6d0ff78d99c6 100644
--- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
@@ -404,7 +404,7 @@ static int iceland_ih_set_clockgating_state(void *handle,
return 0;
}
-static int iceland_ih_set_powergating_state(void *handle,
+static int iceland_ih_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
index 80c021598b78..a6387a151137 100644
--- a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
@@ -762,10 +762,10 @@ static void ih_v6_0_update_ih_mem_power_gating(struct amdgpu_device *adev,
WREG32_SOC15(OSSSYS, 0, regIH_MEM_POWER_CTRL, ih_mem_pwr_cntl);
}
-static int ih_v6_0_set_powergating_state(void *handle,
+static int ih_v6_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
bool enable = (state == AMD_PG_STATE_GATE);
if (adev->pg_flags & AMD_PG_SUPPORT_IH_SRAM_PG)
diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
index be700137d5a7..09d5e28ce112 100644
--- a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
@@ -743,10 +743,10 @@ static void ih_v6_1_update_ih_mem_power_gating(struct amdgpu_device *adev,
WREG32_SOC15(OSSSYS, 0, regIH_MEM_POWER_CTRL, ih_mem_pwr_cntl);
}
-static int ih_v6_1_set_powergating_state(void *handle,
+static int ih_v6_1_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
bool enable = (state == AMD_PG_STATE_GATE);
if (adev->pg_flags & AMD_PG_SUPPORT_IH_SRAM_PG)
diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
index a86d12e3ab24..2f34662db179 100644
--- a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
@@ -733,10 +733,10 @@ static void ih_v7_0_update_ih_mem_power_gating(struct amdgpu_device *adev,
WREG32_SOC15(OSSSYS, 0, regIH_MEM_POWER_CTRL, ih_mem_pwr_cntl);
}
-static int ih_v7_0_set_powergating_state(void *handle,
+static int ih_v7_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
bool enable = (state == AMD_PG_STATE_GATE);
if (adev->pg_flags & AMD_PG_SUPPORT_IH_SRAM_PG)
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
index 1bd1e348dab7..387ed4a13bed 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
@@ -35,7 +35,7 @@
static void jpeg_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev);
static void jpeg_v2_0_set_irq_funcs(struct amdgpu_device *adev);
-static int jpeg_v2_0_set_powergating_state(void *handle,
+static int jpeg_v2_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state);
/**
@@ -154,7 +154,7 @@ static int jpeg_v2_0_hw_fini(void *handle)
if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS))
- jpeg_v2_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
+ jpeg_v2_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
return 0;
}
@@ -694,10 +694,10 @@ static int jpeg_v2_0_set_clockgating_state(void *handle,
return 0;
}
-static int jpeg_v2_0_set_powergating_state(void *handle,
+static int jpeg_v2_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
int ret;
if (state == adev->jpeg.cur_state)
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
index 2f397969fe0d..66d7c7c5581f 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
@@ -38,7 +38,7 @@
static void jpeg_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev);
static void jpeg_v2_5_set_irq_funcs(struct amdgpu_device *adev);
-static int jpeg_v2_5_set_powergating_state(void *handle,
+static int jpeg_v2_5_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state);
static void jpeg_v2_5_set_ras_funcs(struct amdgpu_device *adev);
@@ -219,7 +219,7 @@ static int jpeg_v2_5_hw_fini(void *handle)
if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
RREG32_SOC15(JPEG, i, mmUVD_JRBC_STATUS))
- jpeg_v2_5_set_powergating_state(adev, AMD_PG_STATE_GATE);
+ jpeg_v2_5_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG))
amdgpu_irq_put(adev, &adev->jpeg.inst[i].ras_poison_irq, 0);
@@ -543,10 +543,10 @@ static int jpeg_v2_5_set_clockgating_state(void *handle,
return 0;
}
-static int jpeg_v2_5_set_powergating_state(void *handle,
+static int jpeg_v2_5_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
int ret;
if (state == adev->jpeg.cur_state)
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
index 3b8c42516ba8..52a52b39d567 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
@@ -36,7 +36,7 @@
static void jpeg_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev);
static void jpeg_v3_0_set_irq_funcs(struct amdgpu_device *adev);
-static int jpeg_v3_0_set_powergating_state(void *handle,
+static int jpeg_v3_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state);
/**
@@ -168,7 +168,7 @@ static int jpeg_v3_0_hw_fini(void *handle)
if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS))
- jpeg_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
+ jpeg_v3_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
return 0;
}
@@ -485,10 +485,10 @@ static int jpeg_v3_0_set_clockgating_state(void *handle,
return 0;
}
-static int jpeg_v3_0_set_powergating_state(void *handle,
+static int jpeg_v3_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
int ret;
if(state == adev->jpeg.cur_state)
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
index 774cfcbaa628..65d050bdffc9 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
@@ -39,7 +39,7 @@
static int jpeg_v4_0_start_sriov(struct amdgpu_device *adev);
static void jpeg_v4_0_set_dec_ring_funcs(struct amdgpu_device *adev);
static void jpeg_v4_0_set_irq_funcs(struct amdgpu_device *adev);
-static int jpeg_v4_0_set_powergating_state(void *handle,
+static int jpeg_v4_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state);
static void jpeg_v4_0_set_ras_funcs(struct amdgpu_device *adev);
@@ -199,7 +199,7 @@ static int jpeg_v4_0_hw_fini(void *handle)
if (!amdgpu_sriov_vf(adev)) {
if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS))
- jpeg_v4_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
+ jpeg_v4_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
}
if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG))
amdgpu_irq_put(adev, &adev->jpeg.inst->ras_poison_irq, 0);
@@ -647,10 +647,10 @@ static int jpeg_v4_0_set_clockgating_state(void *handle,
return 0;
}
-static int jpeg_v4_0_set_powergating_state(void *handle,
+static int jpeg_v4_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
int ret;
if (amdgpu_sriov_vf(adev)) {
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
index 74b3700052ad..a1b933be8217 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
@@ -43,7 +43,7 @@ enum jpeg_engin_status {
static void jpeg_v4_0_3_set_dec_ring_funcs(struct amdgpu_device *adev);
static void jpeg_v4_0_3_set_irq_funcs(struct amdgpu_device *adev);
-static int jpeg_v4_0_3_set_powergating_state(void *handle,
+static int jpeg_v4_0_3_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state);
static void jpeg_v4_0_3_set_ras_funcs(struct amdgpu_device *adev);
static void jpeg_v4_0_3_dec_ring_set_wptr(struct amdgpu_ring *ring);
@@ -371,7 +371,7 @@ static int jpeg_v4_0_3_hw_fini(void *handle)
if (!amdgpu_sriov_vf(adev)) {
if (adev->jpeg.cur_state != AMD_PG_STATE_GATE)
- ret = jpeg_v4_0_3_set_powergating_state(adev, AMD_PG_STATE_GATE);
+ ret = jpeg_v4_0_3_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
}
return ret;
@@ -962,10 +962,10 @@ static int jpeg_v4_0_3_set_clockgating_state(void *handle,
return 0;
}
-static int jpeg_v4_0_3_set_powergating_state(void *handle,
+static int jpeg_v4_0_3_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
int ret;
if (amdgpu_sriov_vf(adev)) {
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
index 13128bdd45a9..399035a92795 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
@@ -48,7 +48,7 @@
static void jpeg_v4_0_5_set_dec_ring_funcs(struct amdgpu_device *adev);
static void jpeg_v4_0_5_set_irq_funcs(struct amdgpu_device *adev);
-static int jpeg_v4_0_5_set_powergating_state(void *handle,
+static int jpeg_v4_0_5_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state);
static void jpeg_v4_0_5_dec_ring_set_wptr(struct amdgpu_ring *ring);
@@ -228,7 +228,7 @@ static int jpeg_v4_0_5_hw_fini(void *handle)
if (!amdgpu_sriov_vf(adev)) {
if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
RREG32_SOC15(JPEG, i, regUVD_JRBC_STATUS))
- jpeg_v4_0_5_set_powergating_state(adev, AMD_PG_STATE_GATE);
+ jpeg_v4_0_5_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
}
}
return 0;
@@ -678,10 +678,10 @@ static int jpeg_v4_0_5_set_clockgating_state(void *handle,
return 0;
}
-static int jpeg_v4_0_5_set_powergating_state(void *handle,
+static int jpeg_v4_0_5_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
int ret;
if (amdgpu_sriov_vf(adev)) {
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
index e2450f3b1eb4..08afad812728 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
@@ -36,7 +36,7 @@
static void jpeg_v5_0_0_set_dec_ring_funcs(struct amdgpu_device *adev);
static void jpeg_v5_0_0_set_irq_funcs(struct amdgpu_device *adev);
-static int jpeg_v5_0_0_set_powergating_state(void *handle,
+static int jpeg_v5_0_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state);
/**
@@ -165,7 +165,7 @@ static int jpeg_v5_0_0_hw_fini(void *handle)
if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS))
- jpeg_v5_0_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
+ jpeg_v5_0_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
return 0;
}
@@ -572,10 +572,10 @@ static int jpeg_v5_0_0_set_clockgating_state(void *handle,
return 0;
}
-static int jpeg_v5_0_0_set_powergating_state(void *handle,
+static int jpeg_v5_0_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
int ret;
if (state == adev->jpeg.cur_state)
diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
index 85361dcb4b4c..02106ae3ca9a 100644
--- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
@@ -683,7 +683,7 @@ static int navi10_ih_set_clockgating_state(void *handle,
return 0;
}
-static int navi10_ih_set_powergating_state(void *handle,
+static int navi10_ih_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 7fdd5739b608..75cb8556c8bc 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -1089,7 +1089,7 @@ static int nv_common_set_clockgating_state(void *handle,
return 0;
}
-static int nv_common_set_powergating_state(void *handle,
+static int nv_common_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
/* TODO */
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
index a77977478ebe..895230ed4db4 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
@@ -1093,7 +1093,7 @@ static int sdma_v2_4_set_clockgating_state(void *handle,
return 0;
}
-static int sdma_v2_4_set_powergating_state(void *handle,
+static int sdma_v2_4_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 18bc1463238f..6a5edcafd3ec 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -1510,7 +1510,7 @@ static int sdma_v3_0_set_clockgating_state(void *handle,
return 0;
}
-static int sdma_v3_0_set_powergating_state(void *handle,
+static int sdma_v3_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 10887eeb50af..6b2783e0d125 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -2312,10 +2312,10 @@ static int sdma_v4_0_set_clockgating_state(void *handle,
return 0;
}
-static int sdma_v4_0_set_powergating_state(void *handle,
+static int sdma_v4_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) {
case IP_VERSION(4, 1, 0):
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
index a8c5e30c83c8..cdb0ad4ee574 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
@@ -1832,7 +1832,7 @@ static int sdma_v4_4_2_set_clockgating_state(void *handle,
return 0;
}
-static int sdma_v4_4_2_set_powergating_state(void *handle,
+static int sdma_v4_4_2_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
index c67ccb541127..24604fd63dd0 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
@@ -1863,7 +1863,7 @@ static int sdma_v5_0_set_clockgating_state(void *handle,
return 0;
}
-static int sdma_v5_0_set_powergating_state(void *handle,
+static int sdma_v5_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
index b136621e5549..ab687e6ed36a 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
@@ -1822,7 +1822,7 @@ static int sdma_v5_2_set_clockgating_state(void *handle,
return 0;
}
-static int sdma_v5_2_set_powergating_state(void *handle,
+static int sdma_v5_2_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
index f18e3a40ceeb..438be23cdcae 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
@@ -1593,7 +1593,7 @@ static int sdma_v6_0_set_clockgating_state(void *handle,
return 0;
}
-static int sdma_v6_0_set_powergating_state(void *handle,
+static int sdma_v6_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
index 670529e16289..25a6cc68d008 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
@@ -1528,7 +1528,7 @@ static int sdma_v7_0_set_clockgating_state(void *handle,
return 0;
}
-static int sdma_v7_0_set_powergating_state(void *handle,
+static int sdma_v7_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index 096cf2deeb40..603b48533c0e 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -2685,7 +2685,7 @@ static int si_common_set_clockgating_state(void *handle,
return 0;
}
-static int si_common_set_powergating_state(void *handle,
+static int si_common_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c
index 93f80ab50626..b75c7a4fb727 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dma.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c
@@ -677,12 +677,12 @@ static int si_dma_set_clockgating_state(void *handle,
return 0;
}
-static int si_dma_set_powergating_state(void *handle,
+static int si_dma_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
u32 tmp;
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
WREG32(DMA_PGFSM_WRITE, 0x00002000);
WREG32(DMA_PGFSM_CONFIG, 0x100010ff);
diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c b/drivers/gpu/drm/amd/amdgpu/si_ih.c
index 089921417ec5..854ae444d608 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c
@@ -275,7 +275,7 @@ static int si_ih_set_clockgating_state(void *handle,
return 0;
}
-static int si_ih_set_powergating_state(void *handle,
+static int si_ih_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 2f9f7e3fa833..8e5e21835235 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -1483,7 +1483,7 @@ static void soc15_common_get_clockgating_state(void *handle, u64 *flags)
adev->df.funcs->get_clockgating_state(adev, flags);
}
-static int soc15_common_set_powergating_state(void *handle,
+static int soc15_common_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
/* todo */
diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c
index 5946911a4191..80655a80a666 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc21.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
@@ -970,10 +970,10 @@ static int soc21_common_set_clockgating_state(void *handle,
return 0;
}
-static int soc21_common_set_powergating_state(void *handle,
+static int soc21_common_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) {
case IP_VERSION(6, 0, 0):
diff --git a/drivers/gpu/drm/amd/amdgpu/soc24.c b/drivers/gpu/drm/amd/amdgpu/soc24.c
index 64d2f8ce548d..b6d71c7eafed 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc24.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc24.c
@@ -561,10 +561,10 @@ static int soc24_common_set_clockgating_state(void *handle,
return 0;
}
-static int soc24_common_set_powergating_state(void *handle,
+static int soc24_common_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) {
case IP_VERSION(7, 0, 0):
diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
index d76c528d08f1..21211c4de20c 100644
--- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
@@ -462,7 +462,7 @@ static int tonga_ih_set_clockgating_state(void *handle,
return 0;
}
-static int tonga_ih_set_powergating_state(void *handle,
+static int tonga_ih_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
index 0fd864247a48..8ef76e1f77af 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
@@ -797,7 +797,7 @@ static int uvd_v3_1_set_clockgating_state(void *handle,
return 0;
}
-static int uvd_v3_1_set_powergating_state(void *handle,
+static int uvd_v3_1_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
index 853af18fcc43..581f503bfd69 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
@@ -715,7 +715,7 @@ static int uvd_v4_2_set_clockgating_state(void *handle,
return 0;
}
-static int uvd_v4_2_set_powergating_state(void *handle,
+static int uvd_v4_2_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
/* This doesn't actually powergate the UVD block.
@@ -725,7 +725,7 @@ static int uvd_v4_2_set_powergating_state(void *handle,
* revisit this when there is a cleaner line between
* the smc and the hw blocks
*/
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
if (state == AMD_PG_STATE_GATE) {
uvd_v4_2_stop(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
index 7b6128660294..9ba5c64bb776 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
@@ -813,7 +813,7 @@ static int uvd_v5_0_set_clockgating_state(void *handle,
return 0;
}
-static int uvd_v5_0_set_powergating_state(void *handle,
+static int uvd_v5_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
/* This doesn't actually powergate the UVD block.
@@ -823,7 +823,7 @@ static int uvd_v5_0_set_powergating_state(void *handle,
* revisit this when there is a cleaner line between
* the smc and the hw blocks
*/
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
int ret = 0;
if (state == AMD_PG_STATE_GATE) {
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index 0c334d90e4f3..e6c3f9237321 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -1472,7 +1472,7 @@ static int uvd_v6_0_set_clockgating_state(void *handle,
return 0;
}
-static int uvd_v6_0_set_powergating_state(void *handle,
+static int uvd_v6_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
/* This doesn't actually powergate the UVD block.
@@ -1482,7 +1482,7 @@ static int uvd_v6_0_set_powergating_state(void *handle,
* revisit this when there is a cleaner line between
* the smc and the hw blocks
*/
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
int ret = 0;
WREG32(mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
index 71ca9966711e..bf10e23272a0 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
@@ -593,7 +593,7 @@ static int vce_v2_0_set_clockgating_state(void *handle,
return 0;
}
-static int vce_v2_0_set_powergating_state(void *handle,
+static int vce_v2_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
/* This doesn't actually powergate the VCE block.
@@ -603,7 +603,7 @@ static int vce_v2_0_set_powergating_state(void *handle,
* revisit this when there is a cleaner line between
* the smc and the hw blocks
*/
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
if (state == AMD_PG_STATE_GATE)
return vce_v2_0_stop(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
index 92ffd3fa5b00..079139c23bfc 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
@@ -802,7 +802,7 @@ static int vce_v3_0_set_clockgating_state(void *handle,
return 0;
}
-static int vce_v3_0_set_powergating_state(void *handle,
+static int vce_v3_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
/* This doesn't actually powergate the VCE block.
@@ -812,7 +812,7 @@ static int vce_v3_0_set_powergating_state(void *handle,
* revisit this when there is a cleaner line between
* the smc and the hw blocks
*/
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
int ret = 0;
if (state == AMD_PG_STATE_GATE) {
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
index b17aabaf220a..b046e2430b8e 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
@@ -958,7 +958,7 @@ static int vce_v4_0_set_clockgating_state(void *handle,
}
#endif
-static int vce_v4_0_set_powergating_state(void *handle,
+static int vce_v4_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
/* This doesn't actually powergate the VCE block.
@@ -968,7 +968,7 @@ static int vce_v4_0_set_powergating_state(void *handle,
* revisit this when there is a cleaner line between
* the smc and the hw blocks
*/
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
if (state == AMD_PG_STATE_GATE)
return vce_v4_0_stop(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 38497ba60292..734f7cf259b1 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -85,7 +85,8 @@ static int vcn_v1_0_stop(struct amdgpu_device *adev);
static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev);
static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev);
static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev);
-static int vcn_v1_0_set_powergating_state(void *handle, enum amd_powergating_state state);
+static int vcn_v1_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
+ enum amd_powergating_state state);
static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev,
int inst_idx, struct dpg_pause_state *new_state);
@@ -281,7 +282,7 @@ static int vcn_v1_0_hw_fini(void *handle)
if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
(adev->vcn.cur_state[0] != AMD_PG_STATE_GATE &&
RREG32_SOC15(VCN, 0, mmUVD_STATUS))) {
- vcn_v1_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
+ vcn_v1_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
}
return 0;
@@ -1800,7 +1801,7 @@ static void vcn_v1_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t coun
}
}
-static int vcn_v1_0_set_powergating_state(void *handle,
+static int vcn_v1_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
/* This doesn't actually powergate the VCN block.
@@ -1811,7 +1812,7 @@ static int vcn_v1_0_set_powergating_state(void *handle,
* the smc and the hw blocks
*/
int ret;
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
if (state == adev->vcn.cur_state[0])
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index 37ace062788b..df4b85e1a4d7 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -92,7 +92,7 @@ static const struct amdgpu_hwip_reg_entry vcn_reg_list_2_0[] = {
static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev);
static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev);
static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev);
-static int vcn_v2_0_set_powergating_state(void *handle,
+static int vcn_v2_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state);
static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev,
int inst_idx, struct dpg_pause_state *new_state);
@@ -318,7 +318,7 @@ static int vcn_v2_0_hw_fini(void *handle)
if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
(adev->vcn.cur_state[0] != AMD_PG_STATE_GATE &&
RREG32_SOC15(VCN, 0, mmUVD_STATUS)))
- vcn_v2_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
+ vcn_v2_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
return 0;
}
@@ -1798,7 +1798,7 @@ int vcn_v2_0_dec_ring_test_ring(struct amdgpu_ring *ring)
}
-static int vcn_v2_0_set_powergating_state(void *handle,
+static int vcn_v2_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
/* This doesn't actually powergate the VCN block.
@@ -1809,7 +1809,7 @@ static int vcn_v2_0_set_powergating_state(void *handle,
* the smc and the hw blocks
*/
int ret;
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
if (amdgpu_sriov_vf(adev)) {
adev->vcn.cur_state[0] = AMD_PG_STATE_UNGATE;
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
index aa1c96571a21..c69cd7f62f09 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
@@ -95,7 +95,7 @@ static const struct amdgpu_hwip_reg_entry vcn_reg_list_2_5[] = {
static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev);
static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev);
static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev);
-static int vcn_v2_5_set_powergating_state(void *handle,
+static int vcn_v2_5_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state);
static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev,
int inst_idx, struct dpg_pause_state *new_state);
@@ -400,7 +400,7 @@ static int vcn_v2_5_hw_fini(void *handle)
if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
(adev->vcn.cur_state[i] != AMD_PG_STATE_GATE &&
RREG32_SOC15(VCN, i, mmUVD_STATUS))) {
- vcn_v2_5_set_powergating_state(adev, AMD_PG_STATE_GATE);
+ vcn_v2_5_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
}
if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN))
@@ -1825,10 +1825,10 @@ static int vcn_v2_5_set_clockgating_state(void *handle,
return 0;
}
-static int vcn_v2_5_set_powergating_state(void *handle,
+static int vcn_v2_5_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
int ret;
if (amdgpu_sriov_vf(adev))
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index 52c8e7767a6a..65d648429825 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -105,7 +105,7 @@ static int vcn_v3_0_start_sriov(struct amdgpu_device *adev);
static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev);
static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev);
static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev);
-static int vcn_v3_0_set_powergating_state(void *handle,
+static int vcn_v3_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state);
static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev,
int inst_idx, struct dpg_pause_state *new_state);
@@ -433,7 +433,7 @@ static int vcn_v3_0_hw_fini(void *handle)
if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
(adev->vcn.cur_state[i] != AMD_PG_STATE_GATE &&
RREG32_SOC15(VCN, i, mmUVD_STATUS))) {
- vcn_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
+ vcn_v3_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
}
}
}
@@ -2158,10 +2158,10 @@ static int vcn_v3_0_set_clockgating_state(void *handle,
return 0;
}
-static int vcn_v3_0_set_powergating_state(void *handle,
+static int vcn_v3_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
int ret;
for (int i = 0; i < adev->vcn.num_vcn_inst; ++i) {
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
index 9b18810f00e6..50198b72e579 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
@@ -96,7 +96,7 @@ static int amdgpu_ih_clientid_vcns[] = {
static int vcn_v4_0_start_sriov(struct amdgpu_device *adev);
static void vcn_v4_0_set_unified_ring_funcs(struct amdgpu_device *adev);
static void vcn_v4_0_set_irq_funcs(struct amdgpu_device *adev);
-static int vcn_v4_0_set_powergating_state(void *handle,
+static int vcn_v4_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state);
static int vcn_v4_0_pause_dpg_mode(struct amdgpu_device *adev,
int inst_idx, struct dpg_pause_state *new_state);
@@ -361,7 +361,7 @@ static int vcn_v4_0_hw_fini(void *handle)
if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
(adev->vcn.cur_state[i] != AMD_PG_STATE_GATE &&
RREG32_SOC15(VCN, i, regUVD_STATUS))) {
- vcn_v4_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
+ vcn_v4_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
}
}
if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN))
@@ -2037,9 +2037,10 @@ static int vcn_v4_0_set_clockgating_state(void *handle, enum amd_clockgating_sta
*
* Set VCN block powergating state
*/
-static int vcn_v4_0_set_powergating_state(void *handle, enum amd_powergating_state state)
+static int vcn_v4_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
+ enum amd_powergating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
int ret;
for (int i = 0; i < adev->vcn.num_vcn_inst; ++i) {
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
index fb425e27ab89..84939e92cd3a 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
@@ -87,7 +87,7 @@ static const struct amdgpu_hwip_reg_entry vcn_reg_list_4_0_3[] = {
static int vcn_v4_0_3_start_sriov(struct amdgpu_device *adev);
static void vcn_v4_0_3_set_unified_ring_funcs(struct amdgpu_device *adev);
static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev);
-static int vcn_v4_0_3_set_powergating_state(void *handle,
+static int vcn_v4_0_3_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state);
static int vcn_v4_0_3_pause_dpg_mode(struct amdgpu_device *adev,
int inst_idx, struct dpg_pause_state *new_state);
@@ -322,7 +322,7 @@ static int vcn_v4_0_3_hw_fini(void *handle)
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
if (adev->vcn.cur_state[i] != AMD_PG_STATE_GATE) {
- vcn_v4_0_3_set_powergating_state(adev, AMD_PG_STATE_GATE);
+ vcn_v4_0_3_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
}
}
@@ -1626,10 +1626,10 @@ static int vcn_v4_0_3_set_clockgating_state(void *handle,
*
* Set VCN block powergating state
*/
-static int vcn_v4_0_3_set_powergating_state(void *handle,
+static int vcn_v4_0_3_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
int ret;
for (int i = 0; i < adev->vcn.num_vcn_inst; ++i) {
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
index 0c093d23a73f..a3bb42893803 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
@@ -95,7 +95,7 @@ static int amdgpu_ih_clientid_vcns[] = {
static void vcn_v4_0_5_set_unified_ring_funcs(struct amdgpu_device *adev);
static void vcn_v4_0_5_set_irq_funcs(struct amdgpu_device *adev);
-static int vcn_v4_0_5_set_powergating_state(void *handle,
+static int vcn_v4_0_5_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state);
static int vcn_v4_0_5_pause_dpg_mode(struct amdgpu_device *adev,
int inst_idx, struct dpg_pause_state *new_state);
@@ -311,7 +311,7 @@ static int vcn_v4_0_5_hw_fini(void *handle)
if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
(adev->vcn.cur_state[i] != AMD_PG_STATE_GATE &&
RREG32_SOC15(VCN, i, regUVD_STATUS))) {
- vcn_v4_0_5_set_powergating_state(adev, AMD_PG_STATE_GATE);
+ vcn_v4_0_5_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
}
}
}
@@ -1531,9 +1531,10 @@ static int vcn_v4_0_5_set_clockgating_state(void *handle, enum amd_clockgating_s
*
* Set VCN block powergating state
*/
-static int vcn_v4_0_5_set_powergating_state(void *handle, enum amd_powergating_state state)
+static int vcn_v4_0_5_set_powergating_state(struct amdgpu_ip_block *ip_block,
+ enum amd_powergating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
int ret;
for (int i = 0; i < adev->vcn.num_vcn_inst; ++i) {
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
index b9eb12d2cd1b..65791fe2090b 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
@@ -78,7 +78,7 @@ static int amdgpu_ih_clientid_vcns[] = {
static void vcn_v5_0_0_set_unified_ring_funcs(struct amdgpu_device *adev);
static void vcn_v5_0_0_set_irq_funcs(struct amdgpu_device *adev);
-static int vcn_v5_0_0_set_powergating_state(void *handle,
+static int vcn_v5_0_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state);
static int vcn_v5_0_0_pause_dpg_mode(struct amdgpu_device *adev,
int inst_idx, struct dpg_pause_state *new_state);
@@ -275,7 +275,7 @@ static int vcn_v5_0_0_hw_fini(void *handle)
if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
(adev->vcn.cur_state[i] != AMD_PG_STATE_GATE &&
RREG32_SOC15(VCN, i, regUVD_STATUS))) {
- vcn_v5_0_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
+ vcn_v5_0_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
}
}
}
@@ -1258,9 +1258,10 @@ static int vcn_v5_0_0_set_clockgating_state(void *handle, enum amd_clockgating_s
*
* Set VCN block powergating state
*/
-static int vcn_v5_0_0_set_powergating_state(void *handle, enum amd_powergating_state state)
+static int vcn_v5_0_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
+ enum amd_powergating_state state)
{
- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ struct amdgpu_device *adev = ip_block->adev;
int ret;
for (int i = 0; i < adev->vcn.num_vcn_inst; ++i) {
diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
index 2d80aafcdbc6..630567f8e930 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
@@ -624,7 +624,7 @@ static int vega10_ih_set_clockgating_state(void *handle,
}
-static int vega10_ih_set_powergating_state(void *handle,
+static int vega10_ih_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
index c2461211aefb..a083ae3e28ac 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
@@ -687,7 +687,7 @@ static int vega20_ih_set_clockgating_state(void *handle,
}
-static int vega20_ih_set_powergating_state(void *handle,
+static int vega20_ih_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index e832dd50a628..87942af88eec 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -2007,7 +2007,7 @@ static int vi_common_set_clockgating_state(void *handle,
return 0;
}
-static int vi_common_set_powergating_state(void *handle,
+static int vi_common_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 87429766c70f..3aab1b9e07ac 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -961,7 +961,7 @@ static int dm_set_clockgating_state(void *handle,
return 0;
}
-static int dm_set_powergating_state(void *handle,
+static int dm_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
index 6601d3e0f5dd..8e10ffa3d34a 100644
--- a/drivers/gpu/drm/amd/include/amd_shared.h
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -398,7 +398,7 @@ struct amd_ip_funcs {
int (*post_soft_reset)(struct amdgpu_ip_block *ip_block);
int (*set_clockgating_state)(void *handle,
enum amd_clockgating_state state);
- int (*set_powergating_state)(void *handle,
+ int (*set_powergating_state)(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state);
void (*get_clockgating_state)(void *handle, u64 *flags);
void (*dump_ip_state)(struct amdgpu_ip_block *ip_block);
diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
index 92c7e45c64b2..358d066fac56 100644
--- a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
+++ b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
@@ -3194,7 +3194,7 @@ static int kv_dpm_set_clockgating_state(void *handle,
return 0;
}
-static int kv_dpm_set_powergating_state(void *handle,
+static int kv_dpm_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
index 157777db75c7..8e2d243d055d 100644
--- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
+++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
@@ -7860,7 +7860,7 @@ static int si_dpm_set_clockgating_state(void *handle,
return 0;
}
-static int si_dpm_set_powergating_state(void *handle,
+static int si_dpm_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
index 334f03c04257..750a7c0fb898 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
@@ -255,7 +255,7 @@ static int pp_sw_reset(struct amdgpu_ip_block *ip_block)
return 0;
}
-static int pp_set_powergating_state(void *handle,
+static int pp_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 86001682e13e..5b3d0cf7bb99 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -2263,7 +2263,7 @@ static int smu_set_clockgating_state(void *handle,
return 0;
}
-static int smu_set_powergating_state(void *handle,
+static int smu_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
return 0;
--
2.34.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH 09/18] drm/amdgpu: pass ip_block in set_powergating_state
2024-10-02 4:36 ` [PATCH 09/18] drm/amdgpu: pass ip_block in set_powergating_state boyuan.zhang
@ 2024-10-02 11:41 ` Christian König
2024-10-04 19:34 ` Boyuan Zhang
0 siblings, 1 reply; 29+ messages in thread
From: Christian König @ 2024-10-02 11:41 UTC (permalink / raw)
To: boyuan.zhang, amd-gfx, leo.liu, alexander.deucher, sunil.khatri
Am 02.10.24 um 06:36 schrieb boyuan.zhang@amd.com:
> From: Boyuan Zhang <boyuan.zhang@amd.com>
>
> Pass ip_block instead of adev in set_powergating_state callback function.
> Modify set_powergating_state ip functions for all correspoding ip blocks.
>
> Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/cik.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/cik_ih.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/cz_ih.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 6 +++---
> drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/ih_v6_0.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/ih_v6_1.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/ih_v7_0.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 8 ++++----
> drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c | 8 ++++----
> drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c | 8 ++++----
> drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c | 8 ++++----
> drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 8 ++++----
> drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c | 8 ++++----
> drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c | 8 ++++----
> drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/nv.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/si.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/si_dma.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/si_ih.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/soc15.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/soc21.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/soc24.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 9 +++++----
> drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 8 ++++----
> drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 8 ++++----
> drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 8 ++++----
> drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 9 +++++----
> drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 8 ++++----
> drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 9 +++++----
> drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 9 +++++----
> drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/vega20_ih.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/vi.c | 2 +-
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
> drivers/gpu/drm/amd/include/amd_shared.h | 2 +-
> drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c | 2 +-
> drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 2 +-
> drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c | 2 +-
> drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 2 +-
> 82 files changed, 155 insertions(+), 151 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
> index 436f24d6bd83..192c5c0926a1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
> @@ -606,10 +606,10 @@ static int acp_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int acp_set_powergating_state(void *handle,
> +static int acp_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> bool enable = (state == AMD_PG_STATE_GATE);
>
> amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, enable);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> index b545940e512b..c074db65f196 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
> @@ -724,7 +724,7 @@ void amdgpu_amdkfd_set_compute_idle(struct amdgpu_device *adev, bool idle)
> /* Disable GFXOFF and PG. Temporary workaround
> * to fix some compute applications issue on GFX9.
> */
> - adev->ip_blocks[AMD_IP_BLOCK_TYPE_GFX].version->funcs->set_powergating_state((void *)adev, state);
> + adev->ip_blocks[AMD_IP_BLOCK_TYPE_GFX].version->funcs->set_powergating_state((void *)&adev->ip_blocks[AMD_IP_BLOCK_TYPE_GFX], state);
That's completely wrong the ip_blocks can't be indexed by
AMD_IP_BLOCK_TYPE_.
We missed this during Sunil's review as well.
Regards,
Christian.
> }
> amdgpu_dpm_switch_power_profile(adev,
> PP_SMC_POWER_PROFILE_COMPUTE,
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 1e47655e02c6..263f25ac2d63 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -2154,7 +2154,7 @@ int amdgpu_device_ip_set_powergating_state(void *dev,
> if (!adev->ip_blocks[i].version->funcs->set_powergating_state)
> continue;
> r = adev->ip_blocks[i].version->funcs->set_powergating_state(
> - (void *)adev, state);
> + (void *)&adev->ip_blocks[i], state);
> if (r)
> DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n",
> adev->ip_blocks[i].version->funcs->name, r);
> @@ -3128,7 +3128,7 @@ int amdgpu_device_set_pg_state(struct amdgpu_device *adev,
> adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG &&
> adev->ip_blocks[i].version->funcs->set_powergating_state) {
> /* enable powergating to save power */
> - r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev,
> + r = adev->ip_blocks[i].version->funcs->set_powergating_state((void *)&adev->ip_blocks[i],
> state);
> if (r) {
> DRM_ERROR("set_powergating_state(gate) of IP block <%s> failed %d\n",
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c
> index e90b5f807440..38f9a5a5d6ca 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c
> @@ -171,7 +171,7 @@ static int isp_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int isp_set_powergating_state(void *handle,
> +static int isp_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> index 02fad4dad7c1..0fa2fe6e5487 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> @@ -3793,7 +3793,7 @@ static int psp_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int psp_set_powergating_state(void *handle,
> +static int psp_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
> index af274e6b8422..bef7636228f6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
> @@ -648,7 +648,7 @@ static int amdgpu_vkms_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int amdgpu_vkms_set_powergating_state(void *handle,
> +static int amdgpu_vkms_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c
> index 1b4c60231596..d2700025a6b1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c
> @@ -646,10 +646,10 @@ static int vpe_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int vpe_set_powergating_state(void *handle,
> +static int vpe_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> struct amdgpu_vpe *vpe = &adev->vpe;
>
> if (!adev->pm.dpm_enabled)
> diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
> index b39944e3ac68..3c62f0b55897 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cik.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cik.c
> @@ -2189,7 +2189,7 @@ static int cik_common_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int cik_common_set_powergating_state(void *handle,
> +static int cik_common_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> index 612330f40447..22ba98087a66 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
> @@ -414,7 +414,7 @@ static int cik_ih_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int cik_ih_set_powergating_state(void *handle,
> +static int cik_ih_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
> index 8706855d681b..ae91bbd83eb0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
> @@ -1208,7 +1208,7 @@ static int cik_sdma_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int cik_sdma_set_powergating_state(void *handle,
> +static int cik_sdma_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> index 12a55f1e0e1f..155429900d28 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
> @@ -411,7 +411,7 @@ static int cz_ih_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int cz_ih_set_powergating_state(void *handle,
> +static int cz_ih_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> // TODO
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> index 6f81621649d6..4b8763bfa5f5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> @@ -3313,7 +3313,7 @@ static int dce_v10_0_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int dce_v10_0_set_powergating_state(void *handle,
> +static int dce_v10_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> index b1afe4b837a7..55b66882c4dd 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> @@ -3445,7 +3445,7 @@ static int dce_v11_0_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int dce_v11_0_set_powergating_state(void *handle,
> +static int dce_v11_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> index a6bbeb3bde3b..efcfdceba72c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
> @@ -3135,7 +3135,7 @@ static int dce_v6_0_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int dce_v6_0_set_powergating_state(void *handle,
> +static int dce_v6_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
> index 0b57e22a7c95..38d2ac9aac8d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
> @@ -3223,7 +3223,7 @@ static int dce_v8_0_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int dce_v8_0_set_powergating_state(void *handle,
> +static int dce_v8_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index c544ea2aea6e..7c4b8ff7ae2e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -3673,7 +3673,7 @@ static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
> static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev,
> unsigned int vmid);
>
> -static int gfx_v10_0_set_powergating_state(void *handle,
> +static int gfx_v10_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state);
> static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
> {
> @@ -8319,10 +8319,10 @@ static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = {
> .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range,
> };
>
> -static int gfx_v10_0_set_powergating_state(void *handle,
> +static int gfx_v10_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> bool enable = (state == AMD_PG_STATE_GATE);
>
> if (amdgpu_sriov_vf(adev))
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> index a0f80cc993cf..a7d5343dba2a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> @@ -5402,10 +5402,10 @@ static void gfx_v11_cntl_pg(struct amdgpu_device *adev, bool enable)
> amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
> }
>
> -static int gfx_v11_0_set_powergating_state(void *handle,
> +static int gfx_v11_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> bool enable = (state == AMD_PG_STATE_GATE);
>
> if (amdgpu_sriov_vf(adev))
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
> index 63e1a2803503..0b88f41523d5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
> @@ -3846,10 +3846,10 @@ static void gfx_v12_cntl_pg(struct amdgpu_device *adev, bool enable)
> }
> #endif
>
> -static int gfx_v12_0_set_powergating_state(void *handle,
> +static int gfx_v12_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> bool enable = (state == AMD_PG_STATE_GATE);
>
> if (amdgpu_sriov_vf(adev))
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> index 60579b3029b4..e644ec23252f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> @@ -3404,11 +3404,11 @@ static int gfx_v6_0_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int gfx_v6_0_set_powergating_state(void *handle,
> +static int gfx_v6_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> bool gate = false;
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> if (state == AMD_PG_STATE_GATE)
> gate = true;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> index 990e7de8da25..4e1be0057e6f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> @@ -4873,11 +4873,11 @@ static int gfx_v7_0_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int gfx_v7_0_set_powergating_state(void *handle,
> +static int gfx_v7_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> bool gate = false;
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> if (state == AMD_PG_STATE_GATE)
> gate = true;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index 6864219987e9..d6a1cc898209 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -5359,10 +5359,10 @@ static void cz_update_gfx_cg_power_gating(struct amdgpu_device *adev,
> }
> }
>
> -static int gfx_v8_0_set_powergating_state(void *handle,
> +static int gfx_v8_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> bool enable = (state == AMD_PG_STATE_GATE);
>
> if (amdgpu_sriov_vf(adev))
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 99334afb7aae..5d3e7a07a81d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -5214,10 +5214,10 @@ static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = {
> .is_rlcg_access_range = gfx_v9_0_is_rlcg_access_range,
> };
>
> -static int gfx_v9_0_set_powergating_state(void *handle,
> +static int gfx_v9_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> bool enable = (state == AMD_PG_STATE_GATE);
>
> switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
> index 81bd4ca4fba5..b4d101b642b6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
> @@ -2760,7 +2760,7 @@ static const struct amdgpu_rlc_funcs gfx_v9_4_3_rlc_funcs = {
> .is_rlcg_access_range = gfx_v9_4_3_is_rlcg_access_range,
> };
>
> -static int gfx_v9_4_3_set_powergating_state(void *handle,
> +static int gfx_v9_4_3_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> index 8e51c7e4e8c8..d7af95de9703 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> @@ -1136,7 +1136,7 @@ static void gmc_v10_0_get_clockgating_state(void *handle, u64 *flags)
> athub_v2_0_get_clockgating(adev, flags);
> }
>
> -static int gmc_v10_0_set_powergating_state(void *handle,
> +static int gmc_v10_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
> index 2fc69cdf8843..53841d7287b7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
> @@ -1023,7 +1023,7 @@ static void gmc_v11_0_get_clockgating_state(void *handle, u64 *flags)
> athub_v3_0_get_clockgating(adev, flags);
> }
>
> -static int gmc_v11_0_set_powergating_state(void *handle,
> +static int gmc_v11_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
> index 3cbb5824a378..ceae0cbc7919 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
> @@ -1007,7 +1007,7 @@ static void gmc_v12_0_get_clockgating_state(void *handle, u64 *flags)
> athub_v4_1_0_get_clockgating(adev, flags);
> }
>
> -static int gmc_v12_0_set_powergating_state(void *handle,
> +static int gmc_v12_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> index 82a097d32f28..1766f379fcb0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> @@ -1088,7 +1088,7 @@ static int gmc_v6_0_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int gmc_v6_0_set_powergating_state(void *handle,
> +static int gmc_v6_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> index ad9bad951cc6..9269bbf7b698 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> @@ -1330,7 +1330,7 @@ static int gmc_v7_0_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int gmc_v7_0_set_powergating_state(void *handle,
> +static int gmc_v7_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> index 47ba4480b757..795cd57438de 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> @@ -1672,7 +1672,7 @@ static int gmc_v8_0_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int gmc_v8_0_set_powergating_state(void *handle,
> +static int gmc_v8_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index 1d0eb31d7b72..c6aa236300a1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -2488,7 +2488,7 @@ static void gmc_v9_0_get_clockgating_state(void *handle, u64 *flags)
> athub_v1_0_get_clockgating(adev, flags);
> }
>
> -static int gmc_v9_0_set_powergating_state(void *handle,
> +static int gmc_v9_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> index 6210fa17eeca..6d0ff78d99c6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
> @@ -404,7 +404,7 @@ static int iceland_ih_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int iceland_ih_set_powergating_state(void *handle,
> +static int iceland_ih_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
> index 80c021598b78..a6387a151137 100644
> --- a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
> @@ -762,10 +762,10 @@ static void ih_v6_0_update_ih_mem_power_gating(struct amdgpu_device *adev,
> WREG32_SOC15(OSSSYS, 0, regIH_MEM_POWER_CTRL, ih_mem_pwr_cntl);
> }
>
> -static int ih_v6_0_set_powergating_state(void *handle,
> +static int ih_v6_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> bool enable = (state == AMD_PG_STATE_GATE);
>
> if (adev->pg_flags & AMD_PG_SUPPORT_IH_SRAM_PG)
> diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
> index be700137d5a7..09d5e28ce112 100644
> --- a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
> +++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
> @@ -743,10 +743,10 @@ static void ih_v6_1_update_ih_mem_power_gating(struct amdgpu_device *adev,
> WREG32_SOC15(OSSSYS, 0, regIH_MEM_POWER_CTRL, ih_mem_pwr_cntl);
> }
>
> -static int ih_v6_1_set_powergating_state(void *handle,
> +static int ih_v6_1_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> bool enable = (state == AMD_PG_STATE_GATE);
>
> if (adev->pg_flags & AMD_PG_SUPPORT_IH_SRAM_PG)
> diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
> index a86d12e3ab24..2f34662db179 100644
> --- a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
> @@ -733,10 +733,10 @@ static void ih_v7_0_update_ih_mem_power_gating(struct amdgpu_device *adev,
> WREG32_SOC15(OSSSYS, 0, regIH_MEM_POWER_CTRL, ih_mem_pwr_cntl);
> }
>
> -static int ih_v7_0_set_powergating_state(void *handle,
> +static int ih_v7_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> bool enable = (state == AMD_PG_STATE_GATE);
>
> if (adev->pg_flags & AMD_PG_SUPPORT_IH_SRAM_PG)
> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
> index 1bd1e348dab7..387ed4a13bed 100644
> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
> @@ -35,7 +35,7 @@
>
> static void jpeg_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev);
> static void jpeg_v2_0_set_irq_funcs(struct amdgpu_device *adev);
> -static int jpeg_v2_0_set_powergating_state(void *handle,
> +static int jpeg_v2_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state);
>
> /**
> @@ -154,7 +154,7 @@ static int jpeg_v2_0_hw_fini(void *handle)
>
> if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
> RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS))
> - jpeg_v2_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
> + jpeg_v2_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
>
> return 0;
> }
> @@ -694,10 +694,10 @@ static int jpeg_v2_0_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int jpeg_v2_0_set_powergating_state(void *handle,
> +static int jpeg_v2_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> int ret;
>
> if (state == adev->jpeg.cur_state)
> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
> index 2f397969fe0d..66d7c7c5581f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
> @@ -38,7 +38,7 @@
>
> static void jpeg_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev);
> static void jpeg_v2_5_set_irq_funcs(struct amdgpu_device *adev);
> -static int jpeg_v2_5_set_powergating_state(void *handle,
> +static int jpeg_v2_5_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state);
> static void jpeg_v2_5_set_ras_funcs(struct amdgpu_device *adev);
>
> @@ -219,7 +219,7 @@ static int jpeg_v2_5_hw_fini(void *handle)
>
> if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
> RREG32_SOC15(JPEG, i, mmUVD_JRBC_STATUS))
> - jpeg_v2_5_set_powergating_state(adev, AMD_PG_STATE_GATE);
> + jpeg_v2_5_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
>
> if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG))
> amdgpu_irq_put(adev, &adev->jpeg.inst[i].ras_poison_irq, 0);
> @@ -543,10 +543,10 @@ static int jpeg_v2_5_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int jpeg_v2_5_set_powergating_state(void *handle,
> +static int jpeg_v2_5_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> int ret;
>
> if (state == adev->jpeg.cur_state)
> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
> index 3b8c42516ba8..52a52b39d567 100644
> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
> @@ -36,7 +36,7 @@
>
> static void jpeg_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev);
> static void jpeg_v3_0_set_irq_funcs(struct amdgpu_device *adev);
> -static int jpeg_v3_0_set_powergating_state(void *handle,
> +static int jpeg_v3_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state);
>
> /**
> @@ -168,7 +168,7 @@ static int jpeg_v3_0_hw_fini(void *handle)
>
> if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
> RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS))
> - jpeg_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
> + jpeg_v3_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
>
> return 0;
> }
> @@ -485,10 +485,10 @@ static int jpeg_v3_0_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int jpeg_v3_0_set_powergating_state(void *handle,
> +static int jpeg_v3_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> int ret;
>
> if(state == adev->jpeg.cur_state)
> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
> index 774cfcbaa628..65d050bdffc9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
> @@ -39,7 +39,7 @@
> static int jpeg_v4_0_start_sriov(struct amdgpu_device *adev);
> static void jpeg_v4_0_set_dec_ring_funcs(struct amdgpu_device *adev);
> static void jpeg_v4_0_set_irq_funcs(struct amdgpu_device *adev);
> -static int jpeg_v4_0_set_powergating_state(void *handle,
> +static int jpeg_v4_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state);
> static void jpeg_v4_0_set_ras_funcs(struct amdgpu_device *adev);
>
> @@ -199,7 +199,7 @@ static int jpeg_v4_0_hw_fini(void *handle)
> if (!amdgpu_sriov_vf(adev)) {
> if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
> RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS))
> - jpeg_v4_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
> + jpeg_v4_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
> }
> if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG))
> amdgpu_irq_put(adev, &adev->jpeg.inst->ras_poison_irq, 0);
> @@ -647,10 +647,10 @@ static int jpeg_v4_0_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int jpeg_v4_0_set_powergating_state(void *handle,
> +static int jpeg_v4_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> int ret;
>
> if (amdgpu_sriov_vf(adev)) {
> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
> index 74b3700052ad..a1b933be8217 100644
> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
> @@ -43,7 +43,7 @@ enum jpeg_engin_status {
>
> static void jpeg_v4_0_3_set_dec_ring_funcs(struct amdgpu_device *adev);
> static void jpeg_v4_0_3_set_irq_funcs(struct amdgpu_device *adev);
> -static int jpeg_v4_0_3_set_powergating_state(void *handle,
> +static int jpeg_v4_0_3_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state);
> static void jpeg_v4_0_3_set_ras_funcs(struct amdgpu_device *adev);
> static void jpeg_v4_0_3_dec_ring_set_wptr(struct amdgpu_ring *ring);
> @@ -371,7 +371,7 @@ static int jpeg_v4_0_3_hw_fini(void *handle)
>
> if (!amdgpu_sriov_vf(adev)) {
> if (adev->jpeg.cur_state != AMD_PG_STATE_GATE)
> - ret = jpeg_v4_0_3_set_powergating_state(adev, AMD_PG_STATE_GATE);
> + ret = jpeg_v4_0_3_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
> }
>
> return ret;
> @@ -962,10 +962,10 @@ static int jpeg_v4_0_3_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int jpeg_v4_0_3_set_powergating_state(void *handle,
> +static int jpeg_v4_0_3_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> int ret;
>
> if (amdgpu_sriov_vf(adev)) {
> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
> index 13128bdd45a9..399035a92795 100644
> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
> @@ -48,7 +48,7 @@
>
> static void jpeg_v4_0_5_set_dec_ring_funcs(struct amdgpu_device *adev);
> static void jpeg_v4_0_5_set_irq_funcs(struct amdgpu_device *adev);
> -static int jpeg_v4_0_5_set_powergating_state(void *handle,
> +static int jpeg_v4_0_5_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state);
>
> static void jpeg_v4_0_5_dec_ring_set_wptr(struct amdgpu_ring *ring);
> @@ -228,7 +228,7 @@ static int jpeg_v4_0_5_hw_fini(void *handle)
> if (!amdgpu_sriov_vf(adev)) {
> if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
> RREG32_SOC15(JPEG, i, regUVD_JRBC_STATUS))
> - jpeg_v4_0_5_set_powergating_state(adev, AMD_PG_STATE_GATE);
> + jpeg_v4_0_5_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
> }
> }
> return 0;
> @@ -678,10 +678,10 @@ static int jpeg_v4_0_5_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int jpeg_v4_0_5_set_powergating_state(void *handle,
> +static int jpeg_v4_0_5_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> int ret;
>
> if (amdgpu_sriov_vf(adev)) {
> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
> index e2450f3b1eb4..08afad812728 100644
> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
> @@ -36,7 +36,7 @@
>
> static void jpeg_v5_0_0_set_dec_ring_funcs(struct amdgpu_device *adev);
> static void jpeg_v5_0_0_set_irq_funcs(struct amdgpu_device *adev);
> -static int jpeg_v5_0_0_set_powergating_state(void *handle,
> +static int jpeg_v5_0_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state);
>
> /**
> @@ -165,7 +165,7 @@ static int jpeg_v5_0_0_hw_fini(void *handle)
>
> if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
> RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS))
> - jpeg_v5_0_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
> + jpeg_v5_0_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
>
> return 0;
> }
> @@ -572,10 +572,10 @@ static int jpeg_v5_0_0_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int jpeg_v5_0_0_set_powergating_state(void *handle,
> +static int jpeg_v5_0_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> int ret;
>
> if (state == adev->jpeg.cur_state)
> diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> index 85361dcb4b4c..02106ae3ca9a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> @@ -683,7 +683,7 @@ static int navi10_ih_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int navi10_ih_set_powergating_state(void *handle,
> +static int navi10_ih_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
> index 7fdd5739b608..75cb8556c8bc 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nv.c
> @@ -1089,7 +1089,7 @@ static int nv_common_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int nv_common_set_powergating_state(void *handle,
> +static int nv_common_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> /* TODO */
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
> index a77977478ebe..895230ed4db4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
> @@ -1093,7 +1093,7 @@ static int sdma_v2_4_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int sdma_v2_4_set_powergating_state(void *handle,
> +static int sdma_v2_4_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> index 18bc1463238f..6a5edcafd3ec 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> @@ -1510,7 +1510,7 @@ static int sdma_v3_0_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int sdma_v3_0_set_powergating_state(void *handle,
> +static int sdma_v3_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> index 10887eeb50af..6b2783e0d125 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> @@ -2312,10 +2312,10 @@ static int sdma_v4_0_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int sdma_v4_0_set_powergating_state(void *handle,
> +static int sdma_v4_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) {
> case IP_VERSION(4, 1, 0):
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
> index a8c5e30c83c8..cdb0ad4ee574 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
> @@ -1832,7 +1832,7 @@ static int sdma_v4_4_2_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int sdma_v4_4_2_set_powergating_state(void *handle,
> +static int sdma_v4_4_2_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> index c67ccb541127..24604fd63dd0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> @@ -1863,7 +1863,7 @@ static int sdma_v5_0_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int sdma_v5_0_set_powergating_state(void *handle,
> +static int sdma_v5_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> index b136621e5549..ab687e6ed36a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> @@ -1822,7 +1822,7 @@ static int sdma_v5_2_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int sdma_v5_2_set_powergating_state(void *handle,
> +static int sdma_v5_2_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
> index f18e3a40ceeb..438be23cdcae 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
> @@ -1593,7 +1593,7 @@ static int sdma_v6_0_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int sdma_v6_0_set_powergating_state(void *handle,
> +static int sdma_v6_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
> index 670529e16289..25a6cc68d008 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
> @@ -1528,7 +1528,7 @@ static int sdma_v7_0_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int sdma_v7_0_set_powergating_state(void *handle,
> +static int sdma_v7_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
> index 096cf2deeb40..603b48533c0e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/si.c
> +++ b/drivers/gpu/drm/amd/amdgpu/si.c
> @@ -2685,7 +2685,7 @@ static int si_common_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int si_common_set_powergating_state(void *handle,
> +static int si_common_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c
> index 93f80ab50626..b75c7a4fb727 100644
> --- a/drivers/gpu/drm/amd/amdgpu/si_dma.c
> +++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c
> @@ -677,12 +677,12 @@ static int si_dma_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int si_dma_set_powergating_state(void *handle,
> +static int si_dma_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> u32 tmp;
>
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> WREG32(DMA_PGFSM_WRITE, 0x00002000);
> WREG32(DMA_PGFSM_CONFIG, 0x100010ff);
> diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c b/drivers/gpu/drm/amd/amdgpu/si_ih.c
> index 089921417ec5..854ae444d608 100644
> --- a/drivers/gpu/drm/amd/amdgpu/si_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c
> @@ -275,7 +275,7 @@ static int si_ih_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int si_ih_set_powergating_state(void *handle,
> +static int si_ih_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
> index 2f9f7e3fa833..8e5e21835235 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> @@ -1483,7 +1483,7 @@ static void soc15_common_get_clockgating_state(void *handle, u64 *flags)
> adev->df.funcs->get_clockgating_state(adev, flags);
> }
>
> -static int soc15_common_set_powergating_state(void *handle,
> +static int soc15_common_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> /* todo */
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c
> index 5946911a4191..80655a80a666 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc21.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
> @@ -970,10 +970,10 @@ static int soc21_common_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int soc21_common_set_powergating_state(void *handle,
> +static int soc21_common_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) {
> case IP_VERSION(6, 0, 0):
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc24.c b/drivers/gpu/drm/amd/amdgpu/soc24.c
> index 64d2f8ce548d..b6d71c7eafed 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc24.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc24.c
> @@ -561,10 +561,10 @@ static int soc24_common_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int soc24_common_set_powergating_state(void *handle,
> +static int soc24_common_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) {
> case IP_VERSION(7, 0, 0):
> diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> index d76c528d08f1..21211c4de20c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
> @@ -462,7 +462,7 @@ static int tonga_ih_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int tonga_ih_set_powergating_state(void *handle,
> +static int tonga_ih_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
> index 0fd864247a48..8ef76e1f77af 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
> @@ -797,7 +797,7 @@ static int uvd_v3_1_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int uvd_v3_1_set_powergating_state(void *handle,
> +static int uvd_v3_1_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
> index 853af18fcc43..581f503bfd69 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
> @@ -715,7 +715,7 @@ static int uvd_v4_2_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int uvd_v4_2_set_powergating_state(void *handle,
> +static int uvd_v4_2_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> /* This doesn't actually powergate the UVD block.
> @@ -725,7 +725,7 @@ static int uvd_v4_2_set_powergating_state(void *handle,
> * revisit this when there is a cleaner line between
> * the smc and the hw blocks
> */
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> if (state == AMD_PG_STATE_GATE) {
> uvd_v4_2_stop(adev);
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
> index 7b6128660294..9ba5c64bb776 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
> @@ -813,7 +813,7 @@ static int uvd_v5_0_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int uvd_v5_0_set_powergating_state(void *handle,
> +static int uvd_v5_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> /* This doesn't actually powergate the UVD block.
> @@ -823,7 +823,7 @@ static int uvd_v5_0_set_powergating_state(void *handle,
> * revisit this when there is a cleaner line between
> * the smc and the hw blocks
> */
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> int ret = 0;
>
> if (state == AMD_PG_STATE_GATE) {
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> index 0c334d90e4f3..e6c3f9237321 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> @@ -1472,7 +1472,7 @@ static int uvd_v6_0_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int uvd_v6_0_set_powergating_state(void *handle,
> +static int uvd_v6_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> /* This doesn't actually powergate the UVD block.
> @@ -1482,7 +1482,7 @@ static int uvd_v6_0_set_powergating_state(void *handle,
> * revisit this when there is a cleaner line between
> * the smc and the hw blocks
> */
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> int ret = 0;
>
> WREG32(mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);
> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
> index 71ca9966711e..bf10e23272a0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
> @@ -593,7 +593,7 @@ static int vce_v2_0_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int vce_v2_0_set_powergating_state(void *handle,
> +static int vce_v2_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> /* This doesn't actually powergate the VCE block.
> @@ -603,7 +603,7 @@ static int vce_v2_0_set_powergating_state(void *handle,
> * revisit this when there is a cleaner line between
> * the smc and the hw blocks
> */
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> if (state == AMD_PG_STATE_GATE)
> return vce_v2_0_stop(adev);
> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> index 92ffd3fa5b00..079139c23bfc 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> @@ -802,7 +802,7 @@ static int vce_v3_0_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int vce_v3_0_set_powergating_state(void *handle,
> +static int vce_v3_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> /* This doesn't actually powergate the VCE block.
> @@ -812,7 +812,7 @@ static int vce_v3_0_set_powergating_state(void *handle,
> * revisit this when there is a cleaner line between
> * the smc and the hw blocks
> */
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> int ret = 0;
>
> if (state == AMD_PG_STATE_GATE) {
> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
> index b17aabaf220a..b046e2430b8e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
> @@ -958,7 +958,7 @@ static int vce_v4_0_set_clockgating_state(void *handle,
> }
> #endif
>
> -static int vce_v4_0_set_powergating_state(void *handle,
> +static int vce_v4_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> /* This doesn't actually powergate the VCE block.
> @@ -968,7 +968,7 @@ static int vce_v4_0_set_powergating_state(void *handle,
> * revisit this when there is a cleaner line between
> * the smc and the hw blocks
> */
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> if (state == AMD_PG_STATE_GATE)
> return vce_v4_0_stop(adev);
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> index 38497ba60292..734f7cf259b1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> @@ -85,7 +85,8 @@ static int vcn_v1_0_stop(struct amdgpu_device *adev);
> static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev);
> static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev);
> static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev);
> -static int vcn_v1_0_set_powergating_state(void *handle, enum amd_powergating_state state);
> +static int vcn_v1_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> + enum amd_powergating_state state);
> static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev,
> int inst_idx, struct dpg_pause_state *new_state);
>
> @@ -281,7 +282,7 @@ static int vcn_v1_0_hw_fini(void *handle)
> if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
> (adev->vcn.cur_state[0] != AMD_PG_STATE_GATE &&
> RREG32_SOC15(VCN, 0, mmUVD_STATUS))) {
> - vcn_v1_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
> + vcn_v1_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
> }
>
> return 0;
> @@ -1800,7 +1801,7 @@ static void vcn_v1_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t coun
> }
> }
>
> -static int vcn_v1_0_set_powergating_state(void *handle,
> +static int vcn_v1_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> /* This doesn't actually powergate the VCN block.
> @@ -1811,7 +1812,7 @@ static int vcn_v1_0_set_powergating_state(void *handle,
> * the smc and the hw blocks
> */
> int ret;
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> if (state == adev->vcn.cur_state[0])
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> index 37ace062788b..df4b85e1a4d7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> @@ -92,7 +92,7 @@ static const struct amdgpu_hwip_reg_entry vcn_reg_list_2_0[] = {
> static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev);
> static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev);
> static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev);
> -static int vcn_v2_0_set_powergating_state(void *handle,
> +static int vcn_v2_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state);
> static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev,
> int inst_idx, struct dpg_pause_state *new_state);
> @@ -318,7 +318,7 @@ static int vcn_v2_0_hw_fini(void *handle)
> if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
> (adev->vcn.cur_state[0] != AMD_PG_STATE_GATE &&
> RREG32_SOC15(VCN, 0, mmUVD_STATUS)))
> - vcn_v2_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
> + vcn_v2_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
>
> return 0;
> }
> @@ -1798,7 +1798,7 @@ int vcn_v2_0_dec_ring_test_ring(struct amdgpu_ring *ring)
> }
>
>
> -static int vcn_v2_0_set_powergating_state(void *handle,
> +static int vcn_v2_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> /* This doesn't actually powergate the VCN block.
> @@ -1809,7 +1809,7 @@ static int vcn_v2_0_set_powergating_state(void *handle,
> * the smc and the hw blocks
> */
> int ret;
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
>
> if (amdgpu_sriov_vf(adev)) {
> adev->vcn.cur_state[0] = AMD_PG_STATE_UNGATE;
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> index aa1c96571a21..c69cd7f62f09 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> @@ -95,7 +95,7 @@ static const struct amdgpu_hwip_reg_entry vcn_reg_list_2_5[] = {
> static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev);
> static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev);
> static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev);
> -static int vcn_v2_5_set_powergating_state(void *handle,
> +static int vcn_v2_5_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state);
> static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev,
> int inst_idx, struct dpg_pause_state *new_state);
> @@ -400,7 +400,7 @@ static int vcn_v2_5_hw_fini(void *handle)
> if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
> (adev->vcn.cur_state[i] != AMD_PG_STATE_GATE &&
> RREG32_SOC15(VCN, i, mmUVD_STATUS))) {
> - vcn_v2_5_set_powergating_state(adev, AMD_PG_STATE_GATE);
> + vcn_v2_5_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
> }
>
> if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN))
> @@ -1825,10 +1825,10 @@ static int vcn_v2_5_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int vcn_v2_5_set_powergating_state(void *handle,
> +static int vcn_v2_5_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> int ret;
>
> if (amdgpu_sriov_vf(adev))
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> index 52c8e7767a6a..65d648429825 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> @@ -105,7 +105,7 @@ static int vcn_v3_0_start_sriov(struct amdgpu_device *adev);
> static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev);
> static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev);
> static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev);
> -static int vcn_v3_0_set_powergating_state(void *handle,
> +static int vcn_v3_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state);
> static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev,
> int inst_idx, struct dpg_pause_state *new_state);
> @@ -433,7 +433,7 @@ static int vcn_v3_0_hw_fini(void *handle)
> if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
> (adev->vcn.cur_state[i] != AMD_PG_STATE_GATE &&
> RREG32_SOC15(VCN, i, mmUVD_STATUS))) {
> - vcn_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
> + vcn_v3_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
> }
> }
> }
> @@ -2158,10 +2158,10 @@ static int vcn_v3_0_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int vcn_v3_0_set_powergating_state(void *handle,
> +static int vcn_v3_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> int ret;
>
> for (int i = 0; i < adev->vcn.num_vcn_inst; ++i) {
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
> index 9b18810f00e6..50198b72e579 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
> @@ -96,7 +96,7 @@ static int amdgpu_ih_clientid_vcns[] = {
> static int vcn_v4_0_start_sriov(struct amdgpu_device *adev);
> static void vcn_v4_0_set_unified_ring_funcs(struct amdgpu_device *adev);
> static void vcn_v4_0_set_irq_funcs(struct amdgpu_device *adev);
> -static int vcn_v4_0_set_powergating_state(void *handle,
> +static int vcn_v4_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state);
> static int vcn_v4_0_pause_dpg_mode(struct amdgpu_device *adev,
> int inst_idx, struct dpg_pause_state *new_state);
> @@ -361,7 +361,7 @@ static int vcn_v4_0_hw_fini(void *handle)
> if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
> (adev->vcn.cur_state[i] != AMD_PG_STATE_GATE &&
> RREG32_SOC15(VCN, i, regUVD_STATUS))) {
> - vcn_v4_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
> + vcn_v4_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
> }
> }
> if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN))
> @@ -2037,9 +2037,10 @@ static int vcn_v4_0_set_clockgating_state(void *handle, enum amd_clockgating_sta
> *
> * Set VCN block powergating state
> */
> -static int vcn_v4_0_set_powergating_state(void *handle, enum amd_powergating_state state)
> +static int vcn_v4_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> + enum amd_powergating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> int ret;
>
> for (int i = 0; i < adev->vcn.num_vcn_inst; ++i) {
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> index fb425e27ab89..84939e92cd3a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> @@ -87,7 +87,7 @@ static const struct amdgpu_hwip_reg_entry vcn_reg_list_4_0_3[] = {
> static int vcn_v4_0_3_start_sriov(struct amdgpu_device *adev);
> static void vcn_v4_0_3_set_unified_ring_funcs(struct amdgpu_device *adev);
> static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev);
> -static int vcn_v4_0_3_set_powergating_state(void *handle,
> +static int vcn_v4_0_3_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state);
> static int vcn_v4_0_3_pause_dpg_mode(struct amdgpu_device *adev,
> int inst_idx, struct dpg_pause_state *new_state);
> @@ -322,7 +322,7 @@ static int vcn_v4_0_3_hw_fini(void *handle)
>
> for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
> if (adev->vcn.cur_state[i] != AMD_PG_STATE_GATE) {
> - vcn_v4_0_3_set_powergating_state(adev, AMD_PG_STATE_GATE);
> + vcn_v4_0_3_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
> }
> }
>
> @@ -1626,10 +1626,10 @@ static int vcn_v4_0_3_set_clockgating_state(void *handle,
> *
> * Set VCN block powergating state
> */
> -static int vcn_v4_0_3_set_powergating_state(void *handle,
> +static int vcn_v4_0_3_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> int ret;
>
> for (int i = 0; i < adev->vcn.num_vcn_inst; ++i) {
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
> index 0c093d23a73f..a3bb42893803 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
> @@ -95,7 +95,7 @@ static int amdgpu_ih_clientid_vcns[] = {
>
> static void vcn_v4_0_5_set_unified_ring_funcs(struct amdgpu_device *adev);
> static void vcn_v4_0_5_set_irq_funcs(struct amdgpu_device *adev);
> -static int vcn_v4_0_5_set_powergating_state(void *handle,
> +static int vcn_v4_0_5_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state);
> static int vcn_v4_0_5_pause_dpg_mode(struct amdgpu_device *adev,
> int inst_idx, struct dpg_pause_state *new_state);
> @@ -311,7 +311,7 @@ static int vcn_v4_0_5_hw_fini(void *handle)
> if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
> (adev->vcn.cur_state[i] != AMD_PG_STATE_GATE &&
> RREG32_SOC15(VCN, i, regUVD_STATUS))) {
> - vcn_v4_0_5_set_powergating_state(adev, AMD_PG_STATE_GATE);
> + vcn_v4_0_5_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
> }
> }
> }
> @@ -1531,9 +1531,10 @@ static int vcn_v4_0_5_set_clockgating_state(void *handle, enum amd_clockgating_s
> *
> * Set VCN block powergating state
> */
> -static int vcn_v4_0_5_set_powergating_state(void *handle, enum amd_powergating_state state)
> +static int vcn_v4_0_5_set_powergating_state(struct amdgpu_ip_block *ip_block,
> + enum amd_powergating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> int ret;
>
> for (int i = 0; i < adev->vcn.num_vcn_inst; ++i) {
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
> index b9eb12d2cd1b..65791fe2090b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
> @@ -78,7 +78,7 @@ static int amdgpu_ih_clientid_vcns[] = {
>
> static void vcn_v5_0_0_set_unified_ring_funcs(struct amdgpu_device *adev);
> static void vcn_v5_0_0_set_irq_funcs(struct amdgpu_device *adev);
> -static int vcn_v5_0_0_set_powergating_state(void *handle,
> +static int vcn_v5_0_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state);
> static int vcn_v5_0_0_pause_dpg_mode(struct amdgpu_device *adev,
> int inst_idx, struct dpg_pause_state *new_state);
> @@ -275,7 +275,7 @@ static int vcn_v5_0_0_hw_fini(void *handle)
> if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
> (adev->vcn.cur_state[i] != AMD_PG_STATE_GATE &&
> RREG32_SOC15(VCN, i, regUVD_STATUS))) {
> - vcn_v5_0_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
> + vcn_v5_0_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
> }
> }
> }
> @@ -1258,9 +1258,10 @@ static int vcn_v5_0_0_set_clockgating_state(void *handle, enum amd_clockgating_s
> *
> * Set VCN block powergating state
> */
> -static int vcn_v5_0_0_set_powergating_state(void *handle, enum amd_powergating_state state)
> +static int vcn_v5_0_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
> + enum amd_powergating_state state)
> {
> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> + struct amdgpu_device *adev = ip_block->adev;
> int ret;
>
> for (int i = 0; i < adev->vcn.num_vcn_inst; ++i) {
> diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> index 2d80aafcdbc6..630567f8e930 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> @@ -624,7 +624,7 @@ static int vega10_ih_set_clockgating_state(void *handle,
>
> }
>
> -static int vega10_ih_set_powergating_state(void *handle,
> +static int vega10_ih_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
> index c2461211aefb..a083ae3e28ac 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
> @@ -687,7 +687,7 @@ static int vega20_ih_set_clockgating_state(void *handle,
>
> }
>
> -static int vega20_ih_set_powergating_state(void *handle,
> +static int vega20_ih_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
> index e832dd50a628..87942af88eec 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vi.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vi.c
> @@ -2007,7 +2007,7 @@ static int vi_common_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int vi_common_set_powergating_state(void *handle,
> +static int vi_common_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 87429766c70f..3aab1b9e07ac 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -961,7 +961,7 @@ static int dm_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int dm_set_powergating_state(void *handle,
> +static int dm_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
> index 6601d3e0f5dd..8e10ffa3d34a 100644
> --- a/drivers/gpu/drm/amd/include/amd_shared.h
> +++ b/drivers/gpu/drm/amd/include/amd_shared.h
> @@ -398,7 +398,7 @@ struct amd_ip_funcs {
> int (*post_soft_reset)(struct amdgpu_ip_block *ip_block);
> int (*set_clockgating_state)(void *handle,
> enum amd_clockgating_state state);
> - int (*set_powergating_state)(void *handle,
> + int (*set_powergating_state)(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state);
> void (*get_clockgating_state)(void *handle, u64 *flags);
> void (*dump_ip_state)(struct amdgpu_ip_block *ip_block);
> diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
> index 92c7e45c64b2..358d066fac56 100644
> --- a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
> +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
> @@ -3194,7 +3194,7 @@ static int kv_dpm_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int kv_dpm_set_powergating_state(void *handle,
> +static int kv_dpm_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
> index 157777db75c7..8e2d243d055d 100644
> --- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
> +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
> @@ -7860,7 +7860,7 @@ static int si_dpm_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int si_dpm_set_powergating_state(void *handle,
> +static int si_dpm_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
> index 334f03c04257..750a7c0fb898 100644
> --- a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
> +++ b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
> @@ -255,7 +255,7 @@ static int pp_sw_reset(struct amdgpu_ip_block *ip_block)
> return 0;
> }
>
> -static int pp_set_powergating_state(void *handle,
> +static int pp_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> index 86001682e13e..5b3d0cf7bb99 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> @@ -2263,7 +2263,7 @@ static int smu_set_clockgating_state(void *handle,
> return 0;
> }
>
> -static int smu_set_powergating_state(void *handle,
> +static int smu_set_powergating_state(struct amdgpu_ip_block *ip_block,
> enum amd_powergating_state state)
> {
> return 0;
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH 09/18] drm/amdgpu: pass ip_block in set_powergating_state
2024-10-02 11:41 ` Christian König
@ 2024-10-04 19:34 ` Boyuan Zhang
0 siblings, 0 replies; 29+ messages in thread
From: Boyuan Zhang @ 2024-10-04 19:34 UTC (permalink / raw)
To: Christian König, amd-gfx, leo.liu, alexander.deucher,
sunil.khatri
On 2024-10-02 07:41, Christian König wrote:
> Am 02.10.24 um 06:36 schrieb boyuan.zhang@amd.com:
>> From: Boyuan Zhang <boyuan.zhang@amd.com>
>>
>> Pass ip_block instead of adev in set_powergating_state callback
>> function.
>> Modify set_powergating_state ip functions for all correspoding ip
>> blocks.
>>
>> Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
>> ---
>> drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 4 ++--
>> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++--
>> drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c | 4 ++--
>> drivers/gpu/drm/amd/amdgpu/cik.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/cik_ih.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/cz_ih.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 6 +++---
>> drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 4 ++--
>> drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 4 ++--
>> drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 4 ++--
>> drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 4 ++--
>> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 4 ++--
>> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++--
>> drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/ih_v6_0.c | 4 ++--
>> drivers/gpu/drm/amd/amdgpu/ih_v6_1.c | 4 ++--
>> drivers/gpu/drm/amd/amdgpu/ih_v7_0.c | 4 ++--
>> drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 8 ++++----
>> drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c | 8 ++++----
>> drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c | 8 ++++----
>> drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c | 8 ++++----
>> drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 8 ++++----
>> drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c | 8 ++++----
>> drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c | 8 ++++----
>> drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/nv.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 4 ++--
>> drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/si.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/si_dma.c | 4 ++--
>> drivers/gpu/drm/amd/amdgpu/si_ih.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/soc15.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/soc21.c | 4 ++--
>> drivers/gpu/drm/amd/amdgpu/soc24.c | 4 ++--
>> drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 4 ++--
>> drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 4 ++--
>> drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 4 ++--
>> drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 4 ++--
>> drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 4 ++--
>> drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 4 ++--
>> drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 9 +++++----
>> drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 8 ++++----
>> drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 8 ++++----
>> drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 8 ++++----
>> drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 9 +++++----
>> drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 8 ++++----
>> drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 9 +++++----
>> drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 9 +++++----
>> drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/vega20_ih.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/vi.c | 2 +-
>> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
>> drivers/gpu/drm/amd/include/amd_shared.h | 2 +-
>> drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c | 2 +-
>> drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 2 +-
>> drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c | 2 +-
>> drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 2 +-
>> 82 files changed, 155 insertions(+), 151 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
>> index 436f24d6bd83..192c5c0926a1 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
>> @@ -606,10 +606,10 @@ static int acp_set_clockgating_state(void *handle,
>> return 0;
>> }
>> -static int acp_set_powergating_state(void *handle,
>> +static int acp_set_powergating_state(struct amdgpu_ip_block *ip_block,
>> enum amd_powergating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> bool enable = (state == AMD_PG_STATE_GATE);
>> amdgpu_dpm_set_powergating_by_smu(adev,
>> AMD_IP_BLOCK_TYPE_ACP, enable);
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
>> index b545940e512b..c074db65f196 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
>> @@ -724,7 +724,7 @@ void amdgpu_amdkfd_set_compute_idle(struct
>> amdgpu_device *adev, bool idle)
>> /* Disable GFXOFF and PG. Temporary workaround
>> * to fix some compute applications issue on GFX9.
>> */
>> -
>> adev->ip_blocks[AMD_IP_BLOCK_TYPE_GFX].version->funcs->set_powergating_state((void
>> *)adev, state);
>> +
>> adev->ip_blocks[AMD_IP_BLOCK_TYPE_GFX].version->funcs->set_powergating_state((void
>> *)&adev->ip_blocks[AMD_IP_BLOCK_TYPE_GFX], state);
>
> That's completely wrong the ip_blocks can't be indexed by
> AMD_IP_BLOCK_TYPE_.
>
> We missed this during Sunil's review as well.
>
> Regards,
> Christian.
Nice catch! Fixed in the v2 patch set.
Regards,
Boyuan
>
>> }
>> amdgpu_dpm_switch_power_profile(adev,
>> PP_SMC_POWER_PROFILE_COMPUTE,
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> index 1e47655e02c6..263f25ac2d63 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> @@ -2154,7 +2154,7 @@ int amdgpu_device_ip_set_powergating_state(void
>> *dev,
>> if (!adev->ip_blocks[i].version->funcs->set_powergating_state)
>> continue;
>> r = adev->ip_blocks[i].version->funcs->set_powergating_state(
>> - (void *)adev, state);
>> + (void *)&adev->ip_blocks[i], state);
>> if (r)
>> DRM_ERROR("set_powergating_state of IP block <%s>
>> failed %d\n",
>> adev->ip_blocks[i].version->funcs->name, r);
>> @@ -3128,7 +3128,7 @@ int amdgpu_device_set_pg_state(struct
>> amdgpu_device *adev,
>> adev->ip_blocks[i].version->type !=
>> AMD_IP_BLOCK_TYPE_JPEG &&
>> adev->ip_blocks[i].version->funcs->set_powergating_state) {
>> /* enable powergating to save power */
>> - r =
>> adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev,
>> + r =
>> adev->ip_blocks[i].version->funcs->set_powergating_state((void
>> *)&adev->ip_blocks[i],
>> state);
>> if (r) {
>> DRM_ERROR("set_powergating_state(gate) of IP block
>> <%s> failed %d\n",
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c
>> index e90b5f807440..38f9a5a5d6ca 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c
>> @@ -171,7 +171,7 @@ static int isp_set_clockgating_state(void *handle,
>> return 0;
>> }
>> -static int isp_set_powergating_state(void *handle,
>> +static int isp_set_powergating_state(struct amdgpu_ip_block *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
>> index 02fad4dad7c1..0fa2fe6e5487 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
>> @@ -3793,7 +3793,7 @@ static int psp_set_clockgating_state(void *handle,
>> return 0;
>> }
>> -static int psp_set_powergating_state(void *handle,
>> +static int psp_set_powergating_state(struct amdgpu_ip_block *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
>> index af274e6b8422..bef7636228f6 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
>> @@ -648,7 +648,7 @@ static int amdgpu_vkms_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int amdgpu_vkms_set_powergating_state(void *handle,
>> +static int amdgpu_vkms_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c
>> index 1b4c60231596..d2700025a6b1 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c
>> @@ -646,10 +646,10 @@ static int vpe_set_clockgating_state(void *handle,
>> return 0;
>> }
>> -static int vpe_set_powergating_state(void *handle,
>> +static int vpe_set_powergating_state(struct amdgpu_ip_block *ip_block,
>> enum amd_powergating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> struct amdgpu_vpe *vpe = &adev->vpe;
>> if (!adev->pm.dpm_enabled)
>> diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c
>> b/drivers/gpu/drm/amd/amdgpu/cik.c
>> index b39944e3ac68..3c62f0b55897 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/cik.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/cik.c
>> @@ -2189,7 +2189,7 @@ static int
>> cik_common_set_clockgating_state(void *handle,
>> return 0;
>> }
>> -static int cik_common_set_powergating_state(void *handle,
>> +static int cik_common_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
>> b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
>> index 612330f40447..22ba98087a66 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
>> @@ -414,7 +414,7 @@ static int cik_ih_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int cik_ih_set_powergating_state(void *handle,
>> +static int cik_ih_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
>> b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
>> index 8706855d681b..ae91bbd83eb0 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
>> @@ -1208,7 +1208,7 @@ static int cik_sdma_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int cik_sdma_set_powergating_state(void *handle,
>> +static int cik_sdma_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
>> b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
>> index 12a55f1e0e1f..155429900d28 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
>> @@ -411,7 +411,7 @@ static int cz_ih_set_clockgating_state(void *handle,
>> return 0;
>> }
>> -static int cz_ih_set_powergating_state(void *handle,
>> +static int cz_ih_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> // TODO
>> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
>> b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
>> index 6f81621649d6..4b8763bfa5f5 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
>> @@ -3313,7 +3313,7 @@ static int dce_v10_0_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int dce_v10_0_set_powergating_state(void *handle,
>> +static int dce_v10_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
>> b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
>> index b1afe4b837a7..55b66882c4dd 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
>> @@ -3445,7 +3445,7 @@ static int dce_v11_0_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int dce_v11_0_set_powergating_state(void *handle,
>> +static int dce_v11_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
>> b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
>> index a6bbeb3bde3b..efcfdceba72c 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
>> @@ -3135,7 +3135,7 @@ static int dce_v6_0_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int dce_v6_0_set_powergating_state(void *handle,
>> +static int dce_v6_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
>> b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
>> index 0b57e22a7c95..38d2ac9aac8d 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
>> @@ -3223,7 +3223,7 @@ static int dce_v8_0_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int dce_v8_0_set_powergating_state(void *handle,
>> +static int dce_v8_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>> index c544ea2aea6e..7c4b8ff7ae2e 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>> @@ -3673,7 +3673,7 @@ static void
>> gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
>> static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device
>> *adev,
>> unsigned int vmid);
>> -static int gfx_v10_0_set_powergating_state(void *handle,
>> +static int gfx_v10_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state);
>> static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring,
>> uint64_t queue_mask)
>> {
>> @@ -8319,10 +8319,10 @@ static const struct amdgpu_rlc_funcs
>> gfx_v10_0_rlc_funcs_sriov = {
>> .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range,
>> };
>> -static int gfx_v10_0_set_powergating_state(void *handle,
>> +static int gfx_v10_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> bool enable = (state == AMD_PG_STATE_GATE);
>> if (amdgpu_sriov_vf(adev))
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
>> index a0f80cc993cf..a7d5343dba2a 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
>> @@ -5402,10 +5402,10 @@ static void gfx_v11_cntl_pg(struct
>> amdgpu_device *adev, bool enable)
>> amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
>> }
>> -static int gfx_v11_0_set_powergating_state(void *handle,
>> +static int gfx_v11_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> bool enable = (state == AMD_PG_STATE_GATE);
>> if (amdgpu_sriov_vf(adev))
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
>> index 63e1a2803503..0b88f41523d5 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
>> @@ -3846,10 +3846,10 @@ static void gfx_v12_cntl_pg(struct
>> amdgpu_device *adev, bool enable)
>> }
>> #endif
>> -static int gfx_v12_0_set_powergating_state(void *handle,
>> +static int gfx_v12_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> bool enable = (state == AMD_PG_STATE_GATE);
>> if (amdgpu_sriov_vf(adev))
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
>> index 60579b3029b4..e644ec23252f 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
>> @@ -3404,11 +3404,11 @@ static int
>> gfx_v6_0_set_clockgating_state(void *handle,
>> return 0;
>> }
>> -static int gfx_v6_0_set_powergating_state(void *handle,
>> +static int gfx_v6_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> bool gate = false;
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> if (state == AMD_PG_STATE_GATE)
>> gate = true;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
>> index 990e7de8da25..4e1be0057e6f 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
>> @@ -4873,11 +4873,11 @@ static int
>> gfx_v7_0_set_clockgating_state(void *handle,
>> return 0;
>> }
>> -static int gfx_v7_0_set_powergating_state(void *handle,
>> +static int gfx_v7_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> bool gate = false;
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> if (state == AMD_PG_STATE_GATE)
>> gate = true;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
>> index 6864219987e9..d6a1cc898209 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
>> @@ -5359,10 +5359,10 @@ static void
>> cz_update_gfx_cg_power_gating(struct amdgpu_device *adev,
>> }
>> }
>> -static int gfx_v8_0_set_powergating_state(void *handle,
>> +static int gfx_v8_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> bool enable = (state == AMD_PG_STATE_GATE);
>> if (amdgpu_sriov_vf(adev))
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> index 99334afb7aae..5d3e7a07a81d 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> @@ -5214,10 +5214,10 @@ static const struct amdgpu_rlc_funcs
>> gfx_v9_0_rlc_funcs = {
>> .is_rlcg_access_range = gfx_v9_0_is_rlcg_access_range,
>> };
>> -static int gfx_v9_0_set_powergating_state(void *handle,
>> +static int gfx_v9_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> bool enable = (state == AMD_PG_STATE_GATE);
>> switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
>> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
>> index 81bd4ca4fba5..b4d101b642b6 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
>> @@ -2760,7 +2760,7 @@ static const struct amdgpu_rlc_funcs
>> gfx_v9_4_3_rlc_funcs = {
>> .is_rlcg_access_range = gfx_v9_4_3_is_rlcg_access_range,
>> };
>> -static int gfx_v9_4_3_set_powergating_state(void *handle,
>> +static int gfx_v9_4_3_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
>> index 8e51c7e4e8c8..d7af95de9703 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
>> @@ -1136,7 +1136,7 @@ static void
>> gmc_v10_0_get_clockgating_state(void *handle, u64 *flags)
>> athub_v2_0_get_clockgating(adev, flags);
>> }
>> -static int gmc_v10_0_set_powergating_state(void *handle,
>> +static int gmc_v10_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
>> index 2fc69cdf8843..53841d7287b7 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
>> @@ -1023,7 +1023,7 @@ static void
>> gmc_v11_0_get_clockgating_state(void *handle, u64 *flags)
>> athub_v3_0_get_clockgating(adev, flags);
>> }
>> -static int gmc_v11_0_set_powergating_state(void *handle,
>> +static int gmc_v11_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
>> index 3cbb5824a378..ceae0cbc7919 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
>> @@ -1007,7 +1007,7 @@ static void
>> gmc_v12_0_get_clockgating_state(void *handle, u64 *flags)
>> athub_v4_1_0_get_clockgating(adev, flags);
>> }
>> -static int gmc_v12_0_set_powergating_state(void *handle,
>> +static int gmc_v12_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
>> index 82a097d32f28..1766f379fcb0 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
>> @@ -1088,7 +1088,7 @@ static int gmc_v6_0_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int gmc_v6_0_set_powergating_state(void *handle,
>> +static int gmc_v6_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
>> index ad9bad951cc6..9269bbf7b698 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
>> @@ -1330,7 +1330,7 @@ static int gmc_v7_0_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int gmc_v7_0_set_powergating_state(void *handle,
>> +static int gmc_v7_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
>> index 47ba4480b757..795cd57438de 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
>> @@ -1672,7 +1672,7 @@ static int gmc_v8_0_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int gmc_v8_0_set_powergating_state(void *handle,
>> +static int gmc_v8_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>> index 1d0eb31d7b72..c6aa236300a1 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>> @@ -2488,7 +2488,7 @@ static void gmc_v9_0_get_clockgating_state(void
>> *handle, u64 *flags)
>> athub_v1_0_get_clockgating(adev, flags);
>> }
>> -static int gmc_v9_0_set_powergating_state(void *handle,
>> +static int gmc_v9_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
>> b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
>> index 6210fa17eeca..6d0ff78d99c6 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
>> @@ -404,7 +404,7 @@ static int iceland_ih_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int iceland_ih_set_powergating_state(void *handle,
>> +static int iceland_ih_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
>> b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
>> index 80c021598b78..a6387a151137 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
>> @@ -762,10 +762,10 @@ static void
>> ih_v6_0_update_ih_mem_power_gating(struct amdgpu_device *adev,
>> WREG32_SOC15(OSSSYS, 0, regIH_MEM_POWER_CTRL, ih_mem_pwr_cntl);
>> }
>> -static int ih_v6_0_set_powergating_state(void *handle,
>> +static int ih_v6_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> bool enable = (state == AMD_PG_STATE_GATE);
>> if (adev->pg_flags & AMD_PG_SUPPORT_IH_SRAM_PG)
>> diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
>> b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
>> index be700137d5a7..09d5e28ce112 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
>> @@ -743,10 +743,10 @@ static void
>> ih_v6_1_update_ih_mem_power_gating(struct amdgpu_device *adev,
>> WREG32_SOC15(OSSSYS, 0, regIH_MEM_POWER_CTRL, ih_mem_pwr_cntl);
>> }
>> -static int ih_v6_1_set_powergating_state(void *handle,
>> +static int ih_v6_1_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> bool enable = (state == AMD_PG_STATE_GATE);
>> if (adev->pg_flags & AMD_PG_SUPPORT_IH_SRAM_PG)
>> diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
>> b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
>> index a86d12e3ab24..2f34662db179 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
>> @@ -733,10 +733,10 @@ static void
>> ih_v7_0_update_ih_mem_power_gating(struct amdgpu_device *adev,
>> WREG32_SOC15(OSSSYS, 0, regIH_MEM_POWER_CTRL, ih_mem_pwr_cntl);
>> }
>> -static int ih_v7_0_set_powergating_state(void *handle,
>> +static int ih_v7_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> bool enable = (state == AMD_PG_STATE_GATE);
>> if (adev->pg_flags & AMD_PG_SUPPORT_IH_SRAM_PG)
>> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
>> b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
>> index 1bd1e348dab7..387ed4a13bed 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
>> @@ -35,7 +35,7 @@
>> static void jpeg_v2_0_set_dec_ring_funcs(struct amdgpu_device
>> *adev);
>> static void jpeg_v2_0_set_irq_funcs(struct amdgpu_device *adev);
>> -static int jpeg_v2_0_set_powergating_state(void *handle,
>> +static int jpeg_v2_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state);
>> /**
>> @@ -154,7 +154,7 @@ static int jpeg_v2_0_hw_fini(void *handle)
>> if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
>> RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS))
>> - jpeg_v2_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
>> + jpeg_v2_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
>> return 0;
>> }
>> @@ -694,10 +694,10 @@ static int jpeg_v2_0_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int jpeg_v2_0_set_powergating_state(void *handle,
>> +static int jpeg_v2_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> int ret;
>> if (state == adev->jpeg.cur_state)
>> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
>> b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
>> index 2f397969fe0d..66d7c7c5581f 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
>> @@ -38,7 +38,7 @@
>> static void jpeg_v2_5_set_dec_ring_funcs(struct amdgpu_device
>> *adev);
>> static void jpeg_v2_5_set_irq_funcs(struct amdgpu_device *adev);
>> -static int jpeg_v2_5_set_powergating_state(void *handle,
>> +static int jpeg_v2_5_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state);
>> static void jpeg_v2_5_set_ras_funcs(struct amdgpu_device *adev);
>> @@ -219,7 +219,7 @@ static int jpeg_v2_5_hw_fini(void *handle)
>> if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
>> RREG32_SOC15(JPEG, i, mmUVD_JRBC_STATUS))
>> - jpeg_v2_5_set_powergating_state(adev, AMD_PG_STATE_GATE);
>> + jpeg_v2_5_set_powergating_state(ip_block,
>> AMD_PG_STATE_GATE);
>> if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG))
>> amdgpu_irq_put(adev,
>> &adev->jpeg.inst[i].ras_poison_irq, 0);
>> @@ -543,10 +543,10 @@ static int jpeg_v2_5_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int jpeg_v2_5_set_powergating_state(void *handle,
>> +static int jpeg_v2_5_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> int ret;
>> if (state == adev->jpeg.cur_state)
>> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
>> b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
>> index 3b8c42516ba8..52a52b39d567 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
>> @@ -36,7 +36,7 @@
>> static void jpeg_v3_0_set_dec_ring_funcs(struct amdgpu_device
>> *adev);
>> static void jpeg_v3_0_set_irq_funcs(struct amdgpu_device *adev);
>> -static int jpeg_v3_0_set_powergating_state(void *handle,
>> +static int jpeg_v3_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state);
>> /**
>> @@ -168,7 +168,7 @@ static int jpeg_v3_0_hw_fini(void *handle)
>> if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
>> RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS))
>> - jpeg_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
>> + jpeg_v3_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
>> return 0;
>> }
>> @@ -485,10 +485,10 @@ static int jpeg_v3_0_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int jpeg_v3_0_set_powergating_state(void *handle,
>> +static int jpeg_v3_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> int ret;
>> if(state == adev->jpeg.cur_state)
>> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
>> b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
>> index 774cfcbaa628..65d050bdffc9 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c
>> @@ -39,7 +39,7 @@
>> static int jpeg_v4_0_start_sriov(struct amdgpu_device *adev);
>> static void jpeg_v4_0_set_dec_ring_funcs(struct amdgpu_device *adev);
>> static void jpeg_v4_0_set_irq_funcs(struct amdgpu_device *adev);
>> -static int jpeg_v4_0_set_powergating_state(void *handle,
>> +static int jpeg_v4_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state);
>> static void jpeg_v4_0_set_ras_funcs(struct amdgpu_device *adev);
>> @@ -199,7 +199,7 @@ static int jpeg_v4_0_hw_fini(void *handle)
>> if (!amdgpu_sriov_vf(adev)) {
>> if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
>> RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS))
>> - jpeg_v4_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
>> + jpeg_v4_0_set_powergating_state(ip_block,
>> AMD_PG_STATE_GATE);
>> }
>> if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG))
>> amdgpu_irq_put(adev, &adev->jpeg.inst->ras_poison_irq, 0);
>> @@ -647,10 +647,10 @@ static int jpeg_v4_0_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int jpeg_v4_0_set_powergating_state(void *handle,
>> +static int jpeg_v4_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> int ret;
>> if (amdgpu_sriov_vf(adev)) {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
>> b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
>> index 74b3700052ad..a1b933be8217 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c
>> @@ -43,7 +43,7 @@ enum jpeg_engin_status {
>> static void jpeg_v4_0_3_set_dec_ring_funcs(struct amdgpu_device
>> *adev);
>> static void jpeg_v4_0_3_set_irq_funcs(struct amdgpu_device *adev);
>> -static int jpeg_v4_0_3_set_powergating_state(void *handle,
>> +static int jpeg_v4_0_3_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state);
>> static void jpeg_v4_0_3_set_ras_funcs(struct amdgpu_device *adev);
>> static void jpeg_v4_0_3_dec_ring_set_wptr(struct amdgpu_ring *ring);
>> @@ -371,7 +371,7 @@ static int jpeg_v4_0_3_hw_fini(void *handle)
>> if (!amdgpu_sriov_vf(adev)) {
>> if (adev->jpeg.cur_state != AMD_PG_STATE_GATE)
>> - ret = jpeg_v4_0_3_set_powergating_state(adev,
>> AMD_PG_STATE_GATE);
>> + ret = jpeg_v4_0_3_set_powergating_state(ip_block,
>> AMD_PG_STATE_GATE);
>> }
>> return ret;
>> @@ -962,10 +962,10 @@ static int
>> jpeg_v4_0_3_set_clockgating_state(void *handle,
>> return 0;
>> }
>> -static int jpeg_v4_0_3_set_powergating_state(void *handle,
>> +static int jpeg_v4_0_3_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> int ret;
>> if (amdgpu_sriov_vf(adev)) {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
>> b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
>> index 13128bdd45a9..399035a92795 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c
>> @@ -48,7 +48,7 @@
>> static void jpeg_v4_0_5_set_dec_ring_funcs(struct amdgpu_device
>> *adev);
>> static void jpeg_v4_0_5_set_irq_funcs(struct amdgpu_device *adev);
>> -static int jpeg_v4_0_5_set_powergating_state(void *handle,
>> +static int jpeg_v4_0_5_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state);
>> static void jpeg_v4_0_5_dec_ring_set_wptr(struct amdgpu_ring *ring);
>> @@ -228,7 +228,7 @@ static int jpeg_v4_0_5_hw_fini(void *handle)
>> if (!amdgpu_sriov_vf(adev)) {
>> if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
>> RREG32_SOC15(JPEG, i, regUVD_JRBC_STATUS))
>> - jpeg_v4_0_5_set_powergating_state(adev,
>> AMD_PG_STATE_GATE);
>> + jpeg_v4_0_5_set_powergating_state(ip_block,
>> AMD_PG_STATE_GATE);
>> }
>> }
>> return 0;
>> @@ -678,10 +678,10 @@ static int
>> jpeg_v4_0_5_set_clockgating_state(void *handle,
>> return 0;
>> }
>> -static int jpeg_v4_0_5_set_powergating_state(void *handle,
>> +static int jpeg_v4_0_5_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> int ret;
>> if (amdgpu_sriov_vf(adev)) {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
>> b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
>> index e2450f3b1eb4..08afad812728 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
>> @@ -36,7 +36,7 @@
>> static void jpeg_v5_0_0_set_dec_ring_funcs(struct amdgpu_device
>> *adev);
>> static void jpeg_v5_0_0_set_irq_funcs(struct amdgpu_device *adev);
>> -static int jpeg_v5_0_0_set_powergating_state(void *handle,
>> +static int jpeg_v5_0_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state);
>> /**
>> @@ -165,7 +165,7 @@ static int jpeg_v5_0_0_hw_fini(void *handle)
>> if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
>> RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS))
>> - jpeg_v5_0_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
>> + jpeg_v5_0_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
>> return 0;
>> }
>> @@ -572,10 +572,10 @@ static int
>> jpeg_v5_0_0_set_clockgating_state(void *handle,
>> return 0;
>> }
>> -static int jpeg_v5_0_0_set_powergating_state(void *handle,
>> +static int jpeg_v5_0_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> int ret;
>> if (state == adev->jpeg.cur_state)
>> diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
>> b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
>> index 85361dcb4b4c..02106ae3ca9a 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
>> @@ -683,7 +683,7 @@ static int navi10_ih_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int navi10_ih_set_powergating_state(void *handle,
>> +static int navi10_ih_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c
>> b/drivers/gpu/drm/amd/amdgpu/nv.c
>> index 7fdd5739b608..75cb8556c8bc 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/nv.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/nv.c
>> @@ -1089,7 +1089,7 @@ static int nv_common_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int nv_common_set_powergating_state(void *handle,
>> +static int nv_common_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> /* TODO */
>> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
>> b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
>> index a77977478ebe..895230ed4db4 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
>> @@ -1093,7 +1093,7 @@ static int sdma_v2_4_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int sdma_v2_4_set_powergating_state(void *handle,
>> +static int sdma_v2_4_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
>> b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
>> index 18bc1463238f..6a5edcafd3ec 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
>> @@ -1510,7 +1510,7 @@ static int sdma_v3_0_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int sdma_v3_0_set_powergating_state(void *handle,
>> +static int sdma_v3_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>> b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>> index 10887eeb50af..6b2783e0d125 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>> @@ -2312,10 +2312,10 @@ static int
>> sdma_v4_0_set_clockgating_state(void *handle,
>> return 0;
>> }
>> -static int sdma_v4_0_set_powergating_state(void *handle,
>> +static int sdma_v4_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) {
>> case IP_VERSION(4, 1, 0):
>> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
>> b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
>> index a8c5e30c83c8..cdb0ad4ee574 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
>> @@ -1832,7 +1832,7 @@ static int
>> sdma_v4_4_2_set_clockgating_state(void *handle,
>> return 0;
>> }
>> -static int sdma_v4_4_2_set_powergating_state(void *handle,
>> +static int sdma_v4_4_2_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
>> b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
>> index c67ccb541127..24604fd63dd0 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
>> @@ -1863,7 +1863,7 @@ static int sdma_v5_0_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int sdma_v5_0_set_powergating_state(void *handle,
>> +static int sdma_v5_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
>> b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
>> index b136621e5549..ab687e6ed36a 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
>> @@ -1822,7 +1822,7 @@ static int sdma_v5_2_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int sdma_v5_2_set_powergating_state(void *handle,
>> +static int sdma_v5_2_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
>> b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
>> index f18e3a40ceeb..438be23cdcae 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
>> @@ -1593,7 +1593,7 @@ static int sdma_v6_0_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int sdma_v6_0_set_powergating_state(void *handle,
>> +static int sdma_v6_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
>> b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
>> index 670529e16289..25a6cc68d008 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
>> @@ -1528,7 +1528,7 @@ static int sdma_v7_0_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int sdma_v7_0_set_powergating_state(void *handle,
>> +static int sdma_v7_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/si.c
>> b/drivers/gpu/drm/amd/amdgpu/si.c
>> index 096cf2deeb40..603b48533c0e 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/si.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/si.c
>> @@ -2685,7 +2685,7 @@ static int si_common_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int si_common_set_powergating_state(void *handle,
>> +static int si_common_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c
>> b/drivers/gpu/drm/amd/amdgpu/si_dma.c
>> index 93f80ab50626..b75c7a4fb727 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/si_dma.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c
>> @@ -677,12 +677,12 @@ static int si_dma_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int si_dma_set_powergating_state(void *handle,
>> +static int si_dma_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> u32 tmp;
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> WREG32(DMA_PGFSM_WRITE, 0x00002000);
>> WREG32(DMA_PGFSM_CONFIG, 0x100010ff);
>> diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c
>> b/drivers/gpu/drm/amd/amdgpu/si_ih.c
>> index 089921417ec5..854ae444d608 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/si_ih.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c
>> @@ -275,7 +275,7 @@ static int si_ih_set_clockgating_state(void *handle,
>> return 0;
>> }
>> -static int si_ih_set_powergating_state(void *handle,
>> +static int si_ih_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
>> b/drivers/gpu/drm/amd/amdgpu/soc15.c
>> index 2f9f7e3fa833..8e5e21835235 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
>> @@ -1483,7 +1483,7 @@ static void
>> soc15_common_get_clockgating_state(void *handle, u64 *flags)
>> adev->df.funcs->get_clockgating_state(adev, flags);
>> }
>> -static int soc15_common_set_powergating_state(void *handle,
>> +static int soc15_common_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> /* todo */
>> diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c
>> b/drivers/gpu/drm/amd/amdgpu/soc21.c
>> index 5946911a4191..80655a80a666 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/soc21.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
>> @@ -970,10 +970,10 @@ static int
>> soc21_common_set_clockgating_state(void *handle,
>> return 0;
>> }
>> -static int soc21_common_set_powergating_state(void *handle,
>> +static int soc21_common_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) {
>> case IP_VERSION(6, 0, 0):
>> diff --git a/drivers/gpu/drm/amd/amdgpu/soc24.c
>> b/drivers/gpu/drm/amd/amdgpu/soc24.c
>> index 64d2f8ce548d..b6d71c7eafed 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/soc24.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/soc24.c
>> @@ -561,10 +561,10 @@ static int
>> soc24_common_set_clockgating_state(void *handle,
>> return 0;
>> }
>> -static int soc24_common_set_powergating_state(void *handle,
>> +static int soc24_common_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) {
>> case IP_VERSION(7, 0, 0):
>> diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
>> b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
>> index d76c528d08f1..21211c4de20c 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
>> @@ -462,7 +462,7 @@ static int tonga_ih_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int tonga_ih_set_powergating_state(void *handle,
>> +static int tonga_ih_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
>> b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
>> index 0fd864247a48..8ef76e1f77af 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
>> @@ -797,7 +797,7 @@ static int uvd_v3_1_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int uvd_v3_1_set_powergating_state(void *handle,
>> +static int uvd_v3_1_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
>> b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
>> index 853af18fcc43..581f503bfd69 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
>> @@ -715,7 +715,7 @@ static int uvd_v4_2_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int uvd_v4_2_set_powergating_state(void *handle,
>> +static int uvd_v4_2_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> /* This doesn't actually powergate the UVD block.
>> @@ -725,7 +725,7 @@ static int uvd_v4_2_set_powergating_state(void
>> *handle,
>> * revisit this when there is a cleaner line between
>> * the smc and the hw blocks
>> */
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> if (state == AMD_PG_STATE_GATE) {
>> uvd_v4_2_stop(adev);
>> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
>> b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
>> index 7b6128660294..9ba5c64bb776 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
>> @@ -813,7 +813,7 @@ static int uvd_v5_0_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int uvd_v5_0_set_powergating_state(void *handle,
>> +static int uvd_v5_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> /* This doesn't actually powergate the UVD block.
>> @@ -823,7 +823,7 @@ static int uvd_v5_0_set_powergating_state(void
>> *handle,
>> * revisit this when there is a cleaner line between
>> * the smc and the hw blocks
>> */
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> int ret = 0;
>> if (state == AMD_PG_STATE_GATE) {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
>> b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
>> index 0c334d90e4f3..e6c3f9237321 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
>> @@ -1472,7 +1472,7 @@ static int uvd_v6_0_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int uvd_v6_0_set_powergating_state(void *handle,
>> +static int uvd_v6_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> /* This doesn't actually powergate the UVD block.
>> @@ -1482,7 +1482,7 @@ static int uvd_v6_0_set_powergating_state(void
>> *handle,
>> * revisit this when there is a cleaner line between
>> * the smc and the hw blocks
>> */
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> int ret = 0;
>> WREG32(mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
>> b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
>> index 71ca9966711e..bf10e23272a0 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
>> @@ -593,7 +593,7 @@ static int vce_v2_0_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int vce_v2_0_set_powergating_state(void *handle,
>> +static int vce_v2_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> /* This doesn't actually powergate the VCE block.
>> @@ -603,7 +603,7 @@ static int vce_v2_0_set_powergating_state(void
>> *handle,
>> * revisit this when there is a cleaner line between
>> * the smc and the hw blocks
>> */
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> if (state == AMD_PG_STATE_GATE)
>> return vce_v2_0_stop(adev);
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
>> b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
>> index 92ffd3fa5b00..079139c23bfc 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
>> @@ -802,7 +802,7 @@ static int vce_v3_0_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int vce_v3_0_set_powergating_state(void *handle,
>> +static int vce_v3_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> /* This doesn't actually powergate the VCE block.
>> @@ -812,7 +812,7 @@ static int vce_v3_0_set_powergating_state(void
>> *handle,
>> * revisit this when there is a cleaner line between
>> * the smc and the hw blocks
>> */
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> int ret = 0;
>> if (state == AMD_PG_STATE_GATE) {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
>> b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
>> index b17aabaf220a..b046e2430b8e 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
>> @@ -958,7 +958,7 @@ static int vce_v4_0_set_clockgating_state(void
>> *handle,
>> }
>> #endif
>> -static int vce_v4_0_set_powergating_state(void *handle,
>> +static int vce_v4_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> /* This doesn't actually powergate the VCE block.
>> @@ -968,7 +968,7 @@ static int vce_v4_0_set_powergating_state(void
>> *handle,
>> * revisit this when there is a cleaner line between
>> * the smc and the hw blocks
>> */
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> if (state == AMD_PG_STATE_GATE)
>> return vce_v4_0_stop(adev);
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
>> b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
>> index 38497ba60292..734f7cf259b1 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
>> @@ -85,7 +85,8 @@ static int vcn_v1_0_stop(struct amdgpu_device *adev);
>> static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev);
>> static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev);
>> static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev);
>> -static int vcn_v1_0_set_powergating_state(void *handle, enum
>> amd_powergating_state state);
>> +static int vcn_v1_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> + enum amd_powergating_state state);
>> static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev,
>> int inst_idx, struct dpg_pause_state *new_state);
>> @@ -281,7 +282,7 @@ static int vcn_v1_0_hw_fini(void *handle)
>> if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
>> (adev->vcn.cur_state[0] != AMD_PG_STATE_GATE &&
>> RREG32_SOC15(VCN, 0, mmUVD_STATUS))) {
>> - vcn_v1_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
>> + vcn_v1_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
>> }
>> return 0;
>> @@ -1800,7 +1801,7 @@ static void vcn_v1_0_dec_ring_insert_nop(struct
>> amdgpu_ring *ring, uint32_t coun
>> }
>> }
>> -static int vcn_v1_0_set_powergating_state(void *handle,
>> +static int vcn_v1_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> /* This doesn't actually powergate the VCN block.
>> @@ -1811,7 +1812,7 @@ static int vcn_v1_0_set_powergating_state(void
>> *handle,
>> * the smc and the hw blocks
>> */
>> int ret;
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> if (state == adev->vcn.cur_state[0])
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
>> b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
>> index 37ace062788b..df4b85e1a4d7 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
>> @@ -92,7 +92,7 @@ static const struct amdgpu_hwip_reg_entry
>> vcn_reg_list_2_0[] = {
>> static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev);
>> static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev);
>> static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev);
>> -static int vcn_v2_0_set_powergating_state(void *handle,
>> +static int vcn_v2_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state);
>> static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev,
>> int inst_idx, struct dpg_pause_state *new_state);
>> @@ -318,7 +318,7 @@ static int vcn_v2_0_hw_fini(void *handle)
>> if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
>> (adev->vcn.cur_state[0] != AMD_PG_STATE_GATE &&
>> RREG32_SOC15(VCN, 0, mmUVD_STATUS)))
>> - vcn_v2_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
>> + vcn_v2_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE);
>> return 0;
>> }
>> @@ -1798,7 +1798,7 @@ int vcn_v2_0_dec_ring_test_ring(struct
>> amdgpu_ring *ring)
>> }
>> -static int vcn_v2_0_set_powergating_state(void *handle,
>> +static int vcn_v2_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> /* This doesn't actually powergate the VCN block.
>> @@ -1809,7 +1809,7 @@ static int vcn_v2_0_set_powergating_state(void
>> *handle,
>> * the smc and the hw blocks
>> */
>> int ret;
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> if (amdgpu_sriov_vf(adev)) {
>> adev->vcn.cur_state[0] = AMD_PG_STATE_UNGATE;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
>> b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
>> index aa1c96571a21..c69cd7f62f09 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
>> @@ -95,7 +95,7 @@ static const struct amdgpu_hwip_reg_entry
>> vcn_reg_list_2_5[] = {
>> static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev);
>> static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev);
>> static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev);
>> -static int vcn_v2_5_set_powergating_state(void *handle,
>> +static int vcn_v2_5_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state);
>> static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev,
>> int inst_idx, struct dpg_pause_state *new_state);
>> @@ -400,7 +400,7 @@ static int vcn_v2_5_hw_fini(void *handle)
>> if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
>> (adev->vcn.cur_state[i] != AMD_PG_STATE_GATE &&
>> RREG32_SOC15(VCN, i, mmUVD_STATUS))) {
>> - vcn_v2_5_set_powergating_state(adev, AMD_PG_STATE_GATE);
>> + vcn_v2_5_set_powergating_state(ip_block,
>> AMD_PG_STATE_GATE);
>> }
>> if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN))
>> @@ -1825,10 +1825,10 @@ static int
>> vcn_v2_5_set_clockgating_state(void *handle,
>> return 0;
>> }
>> -static int vcn_v2_5_set_powergating_state(void *handle,
>> +static int vcn_v2_5_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> int ret;
>> if (amdgpu_sriov_vf(adev))
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
>> b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
>> index 52c8e7767a6a..65d648429825 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
>> @@ -105,7 +105,7 @@ static int vcn_v3_0_start_sriov(struct
>> amdgpu_device *adev);
>> static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev);
>> static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev);
>> static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev);
>> -static int vcn_v3_0_set_powergating_state(void *handle,
>> +static int vcn_v3_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state);
>> static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev,
>> int inst_idx, struct dpg_pause_state *new_state);
>> @@ -433,7 +433,7 @@ static int vcn_v3_0_hw_fini(void *handle)
>> if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
>> (adev->vcn.cur_state[i] != AMD_PG_STATE_GATE &&
>> RREG32_SOC15(VCN, i, mmUVD_STATUS))) {
>> - vcn_v3_0_set_powergating_state(adev,
>> AMD_PG_STATE_GATE);
>> + vcn_v3_0_set_powergating_state(ip_block,
>> AMD_PG_STATE_GATE);
>> }
>> }
>> }
>> @@ -2158,10 +2158,10 @@ static int
>> vcn_v3_0_set_clockgating_state(void *handle,
>> return 0;
>> }
>> -static int vcn_v3_0_set_powergating_state(void *handle,
>> +static int vcn_v3_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> int ret;
>> for (int i = 0; i < adev->vcn.num_vcn_inst; ++i) {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
>> b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
>> index 9b18810f00e6..50198b72e579 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
>> @@ -96,7 +96,7 @@ static int amdgpu_ih_clientid_vcns[] = {
>> static int vcn_v4_0_start_sriov(struct amdgpu_device *adev);
>> static void vcn_v4_0_set_unified_ring_funcs(struct amdgpu_device
>> *adev);
>> static void vcn_v4_0_set_irq_funcs(struct amdgpu_device *adev);
>> -static int vcn_v4_0_set_powergating_state(void *handle,
>> +static int vcn_v4_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state);
>> static int vcn_v4_0_pause_dpg_mode(struct amdgpu_device *adev,
>> int inst_idx, struct dpg_pause_state *new_state);
>> @@ -361,7 +361,7 @@ static int vcn_v4_0_hw_fini(void *handle)
>> if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
>> (adev->vcn.cur_state[i] != AMD_PG_STATE_GATE &&
>> RREG32_SOC15(VCN, i, regUVD_STATUS))) {
>> - vcn_v4_0_set_powergating_state(adev,
>> AMD_PG_STATE_GATE);
>> + vcn_v4_0_set_powergating_state(ip_block,
>> AMD_PG_STATE_GATE);
>> }
>> }
>> if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN))
>> @@ -2037,9 +2037,10 @@ static int vcn_v4_0_set_clockgating_state(void
>> *handle, enum amd_clockgating_sta
>> *
>> * Set VCN block powergating state
>> */
>> -static int vcn_v4_0_set_powergating_state(void *handle, enum
>> amd_powergating_state state)
>> +static int vcn_v4_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> + enum amd_powergating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> int ret;
>> for (int i = 0; i < adev->vcn.num_vcn_inst; ++i) {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
>> b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
>> index fb425e27ab89..84939e92cd3a 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
>> @@ -87,7 +87,7 @@ static const struct amdgpu_hwip_reg_entry
>> vcn_reg_list_4_0_3[] = {
>> static int vcn_v4_0_3_start_sriov(struct amdgpu_device *adev);
>> static void vcn_v4_0_3_set_unified_ring_funcs(struct amdgpu_device
>> *adev);
>> static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev);
>> -static int vcn_v4_0_3_set_powergating_state(void *handle,
>> +static int vcn_v4_0_3_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state);
>> static int vcn_v4_0_3_pause_dpg_mode(struct amdgpu_device *adev,
>> int inst_idx, struct dpg_pause_state *new_state);
>> @@ -322,7 +322,7 @@ static int vcn_v4_0_3_hw_fini(void *handle)
>> for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
>> if (adev->vcn.cur_state[i] != AMD_PG_STATE_GATE) {
>> - vcn_v4_0_3_set_powergating_state(adev, AMD_PG_STATE_GATE);
>> + vcn_v4_0_3_set_powergating_state(ip_block,
>> AMD_PG_STATE_GATE);
>> }
>> }
>> @@ -1626,10 +1626,10 @@ static int
>> vcn_v4_0_3_set_clockgating_state(void *handle,
>> *
>> * Set VCN block powergating state
>> */
>> -static int vcn_v4_0_3_set_powergating_state(void *handle,
>> +static int vcn_v4_0_3_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> int ret;
>> for (int i = 0; i < adev->vcn.num_vcn_inst; ++i) {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
>> b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
>> index 0c093d23a73f..a3bb42893803 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
>> @@ -95,7 +95,7 @@ static int amdgpu_ih_clientid_vcns[] = {
>> static void vcn_v4_0_5_set_unified_ring_funcs(struct
>> amdgpu_device *adev);
>> static void vcn_v4_0_5_set_irq_funcs(struct amdgpu_device *adev);
>> -static int vcn_v4_0_5_set_powergating_state(void *handle,
>> +static int vcn_v4_0_5_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state);
>> static int vcn_v4_0_5_pause_dpg_mode(struct amdgpu_device *adev,
>> int inst_idx, struct dpg_pause_state *new_state);
>> @@ -311,7 +311,7 @@ static int vcn_v4_0_5_hw_fini(void *handle)
>> if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
>> (adev->vcn.cur_state[i] != AMD_PG_STATE_GATE &&
>> RREG32_SOC15(VCN, i, regUVD_STATUS))) {
>> - vcn_v4_0_5_set_powergating_state(adev,
>> AMD_PG_STATE_GATE);
>> + vcn_v4_0_5_set_powergating_state(ip_block,
>> AMD_PG_STATE_GATE);
>> }
>> }
>> }
>> @@ -1531,9 +1531,10 @@ static int
>> vcn_v4_0_5_set_clockgating_state(void *handle, enum amd_clockgating_s
>> *
>> * Set VCN block powergating state
>> */
>> -static int vcn_v4_0_5_set_powergating_state(void *handle, enum
>> amd_powergating_state state)
>> +static int vcn_v4_0_5_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> + enum amd_powergating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> int ret;
>> for (int i = 0; i < adev->vcn.num_vcn_inst; ++i) {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
>> b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
>> index b9eb12d2cd1b..65791fe2090b 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
>> @@ -78,7 +78,7 @@ static int amdgpu_ih_clientid_vcns[] = {
>> static void vcn_v5_0_0_set_unified_ring_funcs(struct
>> amdgpu_device *adev);
>> static void vcn_v5_0_0_set_irq_funcs(struct amdgpu_device *adev);
>> -static int vcn_v5_0_0_set_powergating_state(void *handle,
>> +static int vcn_v5_0_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state);
>> static int vcn_v5_0_0_pause_dpg_mode(struct amdgpu_device *adev,
>> int inst_idx, struct dpg_pause_state *new_state);
>> @@ -275,7 +275,7 @@ static int vcn_v5_0_0_hw_fini(void *handle)
>> if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
>> (adev->vcn.cur_state[i] != AMD_PG_STATE_GATE &&
>> RREG32_SOC15(VCN, i, regUVD_STATUS))) {
>> - vcn_v5_0_0_set_powergating_state(adev,
>> AMD_PG_STATE_GATE);
>> + vcn_v5_0_0_set_powergating_state(ip_block,
>> AMD_PG_STATE_GATE);
>> }
>> }
>> }
>> @@ -1258,9 +1258,10 @@ static int
>> vcn_v5_0_0_set_clockgating_state(void *handle, enum amd_clockgating_s
>> *
>> * Set VCN block powergating state
>> */
>> -static int vcn_v5_0_0_set_powergating_state(void *handle, enum
>> amd_powergating_state state)
>> +static int vcn_v5_0_0_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> + enum amd_powergating_state state)
>> {
>> - struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> + struct amdgpu_device *adev = ip_block->adev;
>> int ret;
>> for (int i = 0; i < adev->vcn.num_vcn_inst; ++i) {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
>> b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
>> index 2d80aafcdbc6..630567f8e930 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
>> @@ -624,7 +624,7 @@ static int vega10_ih_set_clockgating_state(void
>> *handle,
>> }
>> -static int vega10_ih_set_powergating_state(void *handle,
>> +static int vega10_ih_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
>> b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
>> index c2461211aefb..a083ae3e28ac 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
>> @@ -687,7 +687,7 @@ static int vega20_ih_set_clockgating_state(void
>> *handle,
>> }
>> -static int vega20_ih_set_powergating_state(void *handle,
>> +static int vega20_ih_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c
>> b/drivers/gpu/drm/amd/amdgpu/vi.c
>> index e832dd50a628..87942af88eec 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vi.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vi.c
>> @@ -2007,7 +2007,7 @@ static int vi_common_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int vi_common_set_powergating_state(void *handle,
>> +static int vi_common_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> index 87429766c70f..3aab1b9e07ac 100644
>> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> @@ -961,7 +961,7 @@ static int dm_set_clockgating_state(void *handle,
>> return 0;
>> }
>> -static int dm_set_powergating_state(void *handle,
>> +static int dm_set_powergating_state(struct amdgpu_ip_block *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/include/amd_shared.h
>> b/drivers/gpu/drm/amd/include/amd_shared.h
>> index 6601d3e0f5dd..8e10ffa3d34a 100644
>> --- a/drivers/gpu/drm/amd/include/amd_shared.h
>> +++ b/drivers/gpu/drm/amd/include/amd_shared.h
>> @@ -398,7 +398,7 @@ struct amd_ip_funcs {
>> int (*post_soft_reset)(struct amdgpu_ip_block *ip_block);
>> int (*set_clockgating_state)(void *handle,
>> enum amd_clockgating_state state);
>> - int (*set_powergating_state)(void *handle,
>> + int (*set_powergating_state)(struct amdgpu_ip_block *ip_block,
>> enum amd_powergating_state state);
>> void (*get_clockgating_state)(void *handle, u64 *flags);
>> void (*dump_ip_state)(struct amdgpu_ip_block *ip_block);
>> diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
>> b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
>> index 92c7e45c64b2..358d066fac56 100644
>> --- a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
>> +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c
>> @@ -3194,7 +3194,7 @@ static int kv_dpm_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int kv_dpm_set_powergating_state(void *handle,
>> +static int kv_dpm_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
>> b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
>> index 157777db75c7..8e2d243d055d 100644
>> --- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
>> +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
>> @@ -7860,7 +7860,7 @@ static int si_dpm_set_clockgating_state(void
>> *handle,
>> return 0;
>> }
>> -static int si_dpm_set_powergating_state(void *handle,
>> +static int si_dpm_set_powergating_state(struct amdgpu_ip_block
>> *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
>> b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
>> index 334f03c04257..750a7c0fb898 100644
>> --- a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
>> +++ b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
>> @@ -255,7 +255,7 @@ static int pp_sw_reset(struct amdgpu_ip_block
>> *ip_block)
>> return 0;
>> }
>> -static int pp_set_powergating_state(void *handle,
>> +static int pp_set_powergating_state(struct amdgpu_ip_block *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
>> b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
>> index 86001682e13e..5b3d0cf7bb99 100644
>> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
>> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
>> @@ -2263,7 +2263,7 @@ static int smu_set_clockgating_state(void *handle,
>> return 0;
>> }
>> -static int smu_set_powergating_state(void *handle,
>> +static int smu_set_powergating_state(struct amdgpu_ip_block *ip_block,
>> enum amd_powergating_state state)
>> {
>> return 0;
>
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH 10/18] drm/amdgpu: add ip block with instance
2024-10-02 4:36 [PATCH 00/18] Separating vcn power management by instance boyuan.zhang
` (8 preceding siblings ...)
2024-10-02 4:36 ` [PATCH 09/18] drm/amdgpu: pass ip_block in set_powergating_state boyuan.zhang
@ 2024-10-02 4:36 ` boyuan.zhang
2024-10-02 17:32 ` Alex Deucher
2024-10-02 4:36 ` [PATCH 11/18] drm/amdgpu: add set_powergating_state_instance boyuan.zhang
` (7 subsequent siblings)
17 siblings, 1 reply; 29+ messages in thread
From: boyuan.zhang @ 2024-10-02 4:36 UTC (permalink / raw)
To: amd-gfx, leo.liu, christian.koenig, alexander.deucher,
sunil.khatri
Cc: Boyuan Zhang
From: Boyuan Zhang <boyuan.zhang@amd.com>
Add instance number to ip block to track which instance the ip block
belongs to.
Also, add a new function to allow ip block to save the instance number
along with other ip block driver information.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 5 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 39 ++++++++++++++++++++++
2 files changed, 44 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 84a9749dcd7d..d77db73c71f7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -386,6 +386,7 @@ struct amdgpu_ip_block {
struct amdgpu_ip_block_status status;
const struct amdgpu_ip_block_version *version;
struct amdgpu_device *adev;
+ unsigned int instance;
};
int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
@@ -399,6 +400,10 @@ amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
const struct amdgpu_ip_block_version *ip_block_version);
+int amdgpu_device_ip_block_add_instance(struct amdgpu_device *adev,
+ const struct amdgpu_ip_block_version *ip_block_version,
+ unsigned int inst);
+
/*
* BIOS.
*/
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 263f25ac2d63..4bc109a0d832 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2321,6 +2321,45 @@ int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
return 0;
}
+/**
+ * amdgpu_device_ip_block_add_instance
+ *
+ * @adev: amdgpu_device pointer
+ * @ip_block_version: pointer to the IP to add
+ *
+ * Adds the IP block driver information and instance number
+ * to the collection of IPs on the asic.
+ */
+int amdgpu_device_ip_block_add_instance(struct amdgpu_device *adev,
+ const struct amdgpu_ip_block_version *ip_block_version,
+ unsigned int inst)
+{
+ if (!ip_block_version)
+ return -EINVAL;
+
+ switch (ip_block_version->type) {
+ case AMD_IP_BLOCK_TYPE_VCN:
+ if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK)
+ return 0;
+ break;
+ case AMD_IP_BLOCK_TYPE_JPEG:
+ if (adev->harvest_ip_mask & AMD_HARVEST_IP_JPEG_MASK)
+ return 0;
+ break;
+ default:
+ break;
+ }
+
+ DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks,
+ ip_block_version->funcs->name);
+
+ adev->ip_blocks[adev->num_ip_blocks].adev = adev;
+ adev->ip_blocks[adev->num_ip_blocks].instance = inst;
+ adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version;
+
+ return 0;
+}
+
/**
* amdgpu_device_enable_virtual_display - enable virtual display feature
*
--
2.34.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH 10/18] drm/amdgpu: add ip block with instance
2024-10-02 4:36 ` [PATCH 10/18] drm/amdgpu: add ip block with instance boyuan.zhang
@ 2024-10-02 17:32 ` Alex Deucher
2024-10-04 18:44 ` Boyuan Zhang
0 siblings, 1 reply; 29+ messages in thread
From: Alex Deucher @ 2024-10-02 17:32 UTC (permalink / raw)
To: boyuan.zhang
Cc: amd-gfx, leo.liu, christian.koenig, alexander.deucher,
sunil.khatri
[-- Attachment #1: Type: text/plain, Size: 3587 bytes --]
On Wed, Oct 2, 2024 at 12:39 AM <boyuan.zhang@amd.com> wrote:
>
> From: Boyuan Zhang <boyuan.zhang@amd.com>
>
> Add instance number to ip block to track which instance the ip block
> belongs to.
>
> Also, add a new function to allow ip block to save the instance number
> along with other ip block driver information.
>
> Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
I think the logic can be added to the existing
amdgpu_device_ip_block_add(). Something like the attached patch.
Alex
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 5 +++
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 39 ++++++++++++++++++++++
> 2 files changed, 44 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 84a9749dcd7d..d77db73c71f7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -386,6 +386,7 @@ struct amdgpu_ip_block {
> struct amdgpu_ip_block_status status;
> const struct amdgpu_ip_block_version *version;
> struct amdgpu_device *adev;
> + unsigned int instance;
> };
>
> int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
> @@ -399,6 +400,10 @@ amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
> int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
> const struct amdgpu_ip_block_version *ip_block_version);
>
> +int amdgpu_device_ip_block_add_instance(struct amdgpu_device *adev,
> + const struct amdgpu_ip_block_version *ip_block_version,
> + unsigned int inst);
> +
> /*
> * BIOS.
> */
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 263f25ac2d63..4bc109a0d832 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -2321,6 +2321,45 @@ int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
> return 0;
> }
>
> +/**
> + * amdgpu_device_ip_block_add_instance
> + *
> + * @adev: amdgpu_device pointer
> + * @ip_block_version: pointer to the IP to add
> + *
> + * Adds the IP block driver information and instance number
> + * to the collection of IPs on the asic.
> + */
> +int amdgpu_device_ip_block_add_instance(struct amdgpu_device *adev,
> + const struct amdgpu_ip_block_version *ip_block_version,
> + unsigned int inst)
> +{
> + if (!ip_block_version)
> + return -EINVAL;
> +
> + switch (ip_block_version->type) {
> + case AMD_IP_BLOCK_TYPE_VCN:
> + if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK)
> + return 0;
> + break;
> + case AMD_IP_BLOCK_TYPE_JPEG:
> + if (adev->harvest_ip_mask & AMD_HARVEST_IP_JPEG_MASK)
> + return 0;
> + break;
> + default:
> + break;
> + }
> +
> + DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks,
> + ip_block_version->funcs->name);
> +
> + adev->ip_blocks[adev->num_ip_blocks].adev = adev;
> + adev->ip_blocks[adev->num_ip_blocks].instance = inst;
> + adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version;
> +
> + return 0;
> +}
> +
> /**
> * amdgpu_device_enable_virtual_display - enable virtual display feature
> *
> --
> 2.34.1
>
[-- Attachment #2: 0001-drm-amdgpu-track-instances-of-the-same-IP-block.patch --]
[-- Type: text/x-patch, Size: 2320 bytes --]
From ee638fc028584f0c8f567b65fdd5e47df48ad90c Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexander.deucher@amd.com>
Date: Wed, 2 Oct 2024 13:30:31 -0400
Subject: [PATCH] drm/amdgpu: track instances of the same IP block
When we add a new IP block track the instances of the block
if there are multiple blocks of the same type.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 24 +++++++++++++++++++++-
2 files changed, 24 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index abddc20d573e..ff7704266422 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -385,6 +385,7 @@ struct amdgpu_ip_block_version {
struct amdgpu_ip_block {
struct amdgpu_ip_block_status status;
const struct amdgpu_ip_block_version *version;
+ unsigned int instance;
struct amdgpu_device *adev;
};
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index f7209683dd5c..d31525d26727 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2283,6 +2283,27 @@ int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
return 1;
}
+/**
+ * amdgpu_device_ip_get_num_instances - get number of instances of an IP block
+ *
+ * @adev: amdgpu_device pointer
+ * @type: Type of hardware IP (SMU, GFX, UVD, etc.)
+ *
+ * Returns the count of the hardware IP blocks structure for that type.
+ */
+static unsigned int
+amdgpu_device_ip_get_num_instances(struct amdgpu_device *adev,
+ enum amd_ip_block_type type)
+{
+ unsigned int i, count = 0;
+
+ for (i = 0; i < adev->num_ip_blocks; i++)
+ if (adev->ip_blocks[i].version->type == type)
+ count++;
+
+ return count;
+}
+
/**
* amdgpu_device_ip_block_add
*
@@ -2315,7 +2336,8 @@ int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
ip_block_version->funcs->name);
adev->ip_blocks[adev->num_ip_blocks].adev = adev;
-
+ adev->ip_blocks[adev->num_ip_blocks].instance =
+ amdgpu_device_ip_get_num_instances(adev, ip_block_version->type);
adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version;
return 0;
--
2.46.2
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH 10/18] drm/amdgpu: add ip block with instance
2024-10-02 17:32 ` Alex Deucher
@ 2024-10-04 18:44 ` Boyuan Zhang
0 siblings, 0 replies; 29+ messages in thread
From: Boyuan Zhang @ 2024-10-04 18:44 UTC (permalink / raw)
To: Alex Deucher
Cc: amd-gfx, leo.liu, christian.koenig, alexander.deucher,
sunil.khatri
On 2024-10-02 13:32, Alex Deucher wrote:
> On Wed, Oct 2, 2024 at 12:39 AM <boyuan.zhang@amd.com> wrote:
>> From: Boyuan Zhang <boyuan.zhang@amd.com>
>>
>> Add instance number to ip block to track which instance the ip block
>> belongs to.
>>
>> Also, add a new function to allow ip block to save the instance number
>> along with other ip block driver information.
>>
>> Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
> I think the logic can be added to the existing
> amdgpu_device_ip_block_add(). Something like the attached patch.
>
> Alex
Thanks for the suggestion. And yes, this is a much smarter way =)
Applied in the new v2 patch set.
Regards,
Boyuan
>
>
>> ---
>> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 5 +++
>> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 39 ++++++++++++++++++++++
>> 2 files changed, 44 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> index 84a9749dcd7d..d77db73c71f7 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>> @@ -386,6 +386,7 @@ struct amdgpu_ip_block {
>> struct amdgpu_ip_block_status status;
>> const struct amdgpu_ip_block_version *version;
>> struct amdgpu_device *adev;
>> + unsigned int instance;
>> };
>>
>> int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
>> @@ -399,6 +400,10 @@ amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
>> int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
>> const struct amdgpu_ip_block_version *ip_block_version);
>>
>> +int amdgpu_device_ip_block_add_instance(struct amdgpu_device *adev,
>> + const struct amdgpu_ip_block_version *ip_block_version,
>> + unsigned int inst);
>> +
>> /*
>> * BIOS.
>> */
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> index 263f25ac2d63..4bc109a0d832 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>> @@ -2321,6 +2321,45 @@ int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
>> return 0;
>> }
>>
>> +/**
>> + * amdgpu_device_ip_block_add_instance
>> + *
>> + * @adev: amdgpu_device pointer
>> + * @ip_block_version: pointer to the IP to add
>> + *
>> + * Adds the IP block driver information and instance number
>> + * to the collection of IPs on the asic.
>> + */
>> +int amdgpu_device_ip_block_add_instance(struct amdgpu_device *adev,
>> + const struct amdgpu_ip_block_version *ip_block_version,
>> + unsigned int inst)
>> +{
>> + if (!ip_block_version)
>> + return -EINVAL;
>> +
>> + switch (ip_block_version->type) {
>> + case AMD_IP_BLOCK_TYPE_VCN:
>> + if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK)
>> + return 0;
>> + break;
>> + case AMD_IP_BLOCK_TYPE_JPEG:
>> + if (adev->harvest_ip_mask & AMD_HARVEST_IP_JPEG_MASK)
>> + return 0;
>> + break;
>> + default:
>> + break;
>> + }
>> +
>> + DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks,
>> + ip_block_version->funcs->name);
>> +
>> + adev->ip_blocks[adev->num_ip_blocks].adev = adev;
>> + adev->ip_blocks[adev->num_ip_blocks].instance = inst;
>> + adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version;
>> +
>> + return 0;
>> +}
>> +
>> /**
>> * amdgpu_device_enable_virtual_display - enable virtual display feature
>> *
>> --
>> 2.34.1
>>
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH 11/18] drm/amdgpu: add set_powergating_state_instance
2024-10-02 4:36 [PATCH 00/18] Separating vcn power management by instance boyuan.zhang
` (9 preceding siblings ...)
2024-10-02 4:36 ` [PATCH 10/18] drm/amdgpu: add ip block with instance boyuan.zhang
@ 2024-10-02 4:36 ` boyuan.zhang
2024-10-02 4:36 ` [PATCH 12/18] drm/amdgpu: power vcn 2_5 by instance boyuan.zhang
` (6 subsequent siblings)
17 siblings, 0 replies; 29+ messages in thread
From: boyuan.zhang @ 2024-10-02 4:36 UTC (permalink / raw)
To: amd-gfx, leo.liu, christian.koenig, alexander.deucher,
sunil.khatri
Cc: Boyuan Zhang
From: Boyuan Zhang <boyuan.zhang@amd.com>
Add a new function to allow setting requested powergating state for the
given instance. If the instance value doesn't match with the one inside
ip_block, then do nothing since this request is for other instances with
the same block type.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 37 ++++++++++++++++++++++
2 files changed, 41 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index d77db73c71f7..a6a497844a3d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -357,6 +357,10 @@ int amdgpu_device_ip_set_clockgating_state(void *dev,
int amdgpu_device_ip_set_powergating_state(void *dev,
enum amd_ip_block_type block_type,
enum amd_powergating_state state);
+int amdgpu_device_ip_set_powergating_state_instance(void *dev,
+ enum amd_ip_block_type block_type,
+ enum amd_powergating_state state,
+ unsigned int inst);
void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
u64 *flags);
int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 4bc109a0d832..dfdb33833fc4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2162,6 +2162,43 @@ int amdgpu_device_ip_set_powergating_state(void *dev,
return r;
}
+/**
+ * amdgpu_device_ip_set_powergating_state_instance - set the PG state
+ *
+ * @dev: amdgpu_device pointer
+ * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.)
+ * @state: powergating state (gate or ungate)
+ *
+ * Sets the requested powergating state for the given instance of
+ * the hardware IP specified.
+ * Returns the error code from the last instance.
+ */
+int amdgpu_device_ip_set_powergating_state_instance(void *dev,
+ enum amd_ip_block_type block_type,
+ enum amd_powergating_state state,
+ unsigned int inst)
+{
+ struct amdgpu_device *adev = dev;
+ int i, r = 0;
+
+ for (i = 0; i < adev->num_ip_blocks; i++) {
+ if (!adev->ip_blocks[i].status.valid)
+ continue;
+ if (adev->ip_blocks[i].version->type != block_type)
+ continue;
+ if (adev->ip_blocks[i].instance != inst)
+ continue;
+ if (!adev->ip_blocks[i].version->funcs->set_powergating_state)
+ continue;
+ r = adev->ip_blocks[i].version->funcs->set_powergating_state(
+ (void *)&adev->ip_blocks[i], state);
+ if (r)
+ DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n",
+ adev->ip_blocks[i].version->funcs->name, r);
+ }
+ return r;
+}
+
/**
* amdgpu_device_ip_get_clockgating_state - get the CG state
*
--
2.34.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH 12/18] drm/amdgpu: power vcn 2_5 by instance
2024-10-02 4:36 [PATCH 00/18] Separating vcn power management by instance boyuan.zhang
` (10 preceding siblings ...)
2024-10-02 4:36 ` [PATCH 11/18] drm/amdgpu: add set_powergating_state_instance boyuan.zhang
@ 2024-10-02 4:36 ` boyuan.zhang
2024-10-02 4:36 ` [PATCH 13/18] drm/amdgpu: power vcn 3_0 " boyuan.zhang
` (5 subsequent siblings)
17 siblings, 0 replies; 29+ messages in thread
From: boyuan.zhang @ 2024-10-02 4:36 UTC (permalink / raw)
To: amd-gfx, leo.liu, christian.koenig, alexander.deucher,
sunil.khatri
Cc: Boyuan Zhang
From: Boyuan Zhang <boyuan.zhang@amd.com>
For vcn 2_5, add ip_block for each vcn instance during discovery stage.
And only powering on/off one of the vcn instance using the
instance value stored in ip_block, instead of powering on/off all
vcn instances. Modify the existing functions to use the instance value
in ip_block, and remove the original for loop for all vcn instances.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 4 +-
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 572 +++++++++---------
2 files changed, 285 insertions(+), 291 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index 9f9a1867da72..6b9c974da0c4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -2278,6 +2278,7 @@ static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev)
static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev)
{
+ int i;
if (amdgpu_ip_version(adev, VCE_HWIP, 0)) {
switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) {
case IP_VERSION(7, 0, 0):
@@ -2321,7 +2322,8 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev)
case IP_VERSION(2, 0, 3):
break;
case IP_VERSION(2, 5, 0):
- amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i)
+ amdgpu_device_ip_block_add_instance(adev, &vcn_v2_5_ip_block, i);
amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block);
break;
case IP_VERSION(2, 6, 0):
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
index c69cd7f62f09..930c60616a43 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
@@ -158,35 +158,34 @@ static int vcn_v2_5_early_init(struct amdgpu_ip_block *ip_block)
static int vcn_v2_5_sw_init(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_ring *ring;
- int i, j, r;
+ int i, r;
uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_5);
uint32_t *ptr;
struct amdgpu_device *adev = ip_block->adev;
+ int inst = ip_block->instance;
- for (j = 0; j < adev->vcn.num_vcn_inst; j++) {
- if (adev->vcn.harvest_config & (1 << j))
- continue;
- /* VCN DEC TRAP */
- r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[j],
- VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst[j].irq);
- if (r)
- return r;
-
- /* VCN ENC TRAP */
- for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
- r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[j],
- i + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[j].irq);
- if (r)
- return r;
- }
+ if (adev->vcn.harvest_config & (1 << inst))
+ goto sw_init;
+ /* VCN DEC TRAP */
+ r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[inst],
+ VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst[inst].irq);
+ if (r)
+ return r;
- /* VCN POISON TRAP */
- r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[j],
- VCN_2_6__SRCID_UVD_POISON, &adev->vcn.inst[j].ras_poison_irq);
+ /* VCN ENC TRAP */
+ for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
+ r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[inst],
+ i + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[inst].irq);
if (r)
return r;
}
+ /* VCN POISON TRAP */
+ r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[inst],
+ VCN_2_6__SRCID_UVD_POISON, &adev->vcn.inst[inst].ras_poison_irq);
+ if (r)
+ return r;
+sw_init:
r = amdgpu_vcn_sw_init(adev);
if (r)
return r;
@@ -197,76 +196,74 @@ static int vcn_v2_5_sw_init(struct amdgpu_ip_block *ip_block)
if (r)
return r;
- for (j = 0; j < adev->vcn.num_vcn_inst; j++) {
- volatile struct amdgpu_fw_shared *fw_shared;
+ volatile struct amdgpu_fw_shared *fw_shared;
- if (adev->vcn.harvest_config & (1 << j))
- continue;
- adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET;
- adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET;
- adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET;
- adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET;
- adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET;
- adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET;
-
- adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET;
- adev->vcn.inst[j].external.scratch9 = SOC15_REG_OFFSET(VCN, j, mmUVD_SCRATCH9);
- adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET;
- adev->vcn.inst[j].external.data0 = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_DATA0);
- adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET;
- adev->vcn.inst[j].external.data1 = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_DATA1);
- adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET;
- adev->vcn.inst[j].external.cmd = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_CMD);
- adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET;
- adev->vcn.inst[j].external.nop = SOC15_REG_OFFSET(VCN, j, mmUVD_NO_OP);
-
- ring = &adev->vcn.inst[j].ring_dec;
+ if (adev->vcn.harvest_config & (1 << inst))
+ goto done;
+ adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET;
+ adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET;
+ adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET;
+ adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET;
+ adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET;
+ adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET;
+
+ adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET;
+ adev->vcn.inst[inst].external.scratch9 = SOC15_REG_OFFSET(VCN, inst, mmUVD_SCRATCH9);
+ adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET;
+ adev->vcn.inst[inst].external.data0 = SOC15_REG_OFFSET(VCN, inst, mmUVD_GPCOM_VCPU_DATA0);
+ adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET;
+ adev->vcn.inst[inst].external.data1 = SOC15_REG_OFFSET(VCN, inst, mmUVD_GPCOM_VCPU_DATA1);
+ adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET;
+ adev->vcn.inst[inst].external.cmd = SOC15_REG_OFFSET(VCN, inst, mmUVD_GPCOM_VCPU_CMD);
+ adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET;
+ adev->vcn.inst[inst].external.nop = SOC15_REG_OFFSET(VCN, inst, mmUVD_NO_OP);
+
+ ring = &adev->vcn.inst[inst].ring_dec;
+ ring->use_doorbell = true;
+
+ ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
+ (amdgpu_sriov_vf(adev) ? 2*inst : 8*inst);
+
+ if (amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(2, 5, 0))
+ ring->vm_hub = AMDGPU_MMHUB1(0);
+ else
+ ring->vm_hub = AMDGPU_MMHUB0(0);
+
+ sprintf(ring->name, "vcn_dec_%d", inst);
+ r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[inst].irq,
+ 0, AMDGPU_RING_PRIO_DEFAULT, NULL);
+ if (r)
+ return r;
+
+ for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
+ enum amdgpu_ring_priority_level hw_prio = amdgpu_vcn_get_enc_ring_prio(i);
+
+ ring = &adev->vcn.inst[inst].ring_enc[i];
ring->use_doorbell = true;
ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
- (amdgpu_sriov_vf(adev) ? 2*j : 8*j);
+ (amdgpu_sriov_vf(adev) ? (1 + i + 2*inst) : (2 + i + 8*inst));
- if (amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(2, 5, 0))
+ if (amdgpu_ip_version(adev, UVD_HWIP, 0) ==
+ IP_VERSION(2, 5, 0))
ring->vm_hub = AMDGPU_MMHUB1(0);
else
ring->vm_hub = AMDGPU_MMHUB0(0);
- sprintf(ring->name, "vcn_dec_%d", j);
- r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[j].irq,
- 0, AMDGPU_RING_PRIO_DEFAULT, NULL);
+ sprintf(ring->name, "vcn_enc_%d.%d", inst, i);
+ r = amdgpu_ring_init(adev, ring, 512,
+ &adev->vcn.inst[inst].irq, 0,
+ hw_prio, NULL);
if (r)
return r;
-
- for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
- enum amdgpu_ring_priority_level hw_prio = amdgpu_vcn_get_enc_ring_prio(i);
-
- ring = &adev->vcn.inst[j].ring_enc[i];
- ring->use_doorbell = true;
-
- ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
- (amdgpu_sriov_vf(adev) ? (1 + i + 2*j) : (2 + i + 8*j));
-
- if (amdgpu_ip_version(adev, UVD_HWIP, 0) ==
- IP_VERSION(2, 5, 0))
- ring->vm_hub = AMDGPU_MMHUB1(0);
- else
- ring->vm_hub = AMDGPU_MMHUB0(0);
-
- sprintf(ring->name, "vcn_enc_%d.%d", j, i);
- r = amdgpu_ring_init(adev, ring, 512,
- &adev->vcn.inst[j].irq, 0,
- hw_prio, NULL);
- if (r)
- return r;
- }
-
- fw_shared = adev->vcn.inst[j].fw_shared.cpu_addr;
- fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG);
-
- if (amdgpu_vcnfw_log)
- amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]);
}
+ fw_shared = adev->vcn.inst[inst].fw_shared.cpu_addr;
+ fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG);
+
+ if (amdgpu_vcnfw_log)
+ amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]);
+done:
if (amdgpu_sriov_vf(adev)) {
r = amdgpu_virt_alloc_mm_table(adev);
if (r)
@@ -1010,195 +1007,192 @@ static int vcn_v2_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo
return 0;
}
-static int vcn_v2_5_start(struct amdgpu_device *adev)
+static int vcn_v2_5_start(struct amdgpu_device *adev, unsigned int inst)
{
struct amdgpu_ring *ring;
uint32_t rb_bufsz, tmp;
- int i, j, k, r;
+ int j, k, r;
if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_uvd(adev, true);
+ amdgpu_dpm_enable_vcn(adev, true, inst);
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
- if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
- r = vcn_v2_5_start_dpg_mode(adev, i, adev->vcn.indirect_sram);
- continue;
- }
-
- /* disable register anti-hang mechanism */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_POWER_STATUS), 0,
- ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
+ if (adev->vcn.harvest_config & (1 << inst))
+ return 0;
- /* set uvd status busy */
- tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
- WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp);
+ if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
+ r = vcn_v2_5_start_dpg_mode(adev, inst, adev->vcn.indirect_sram);
+ return r;
}
+ /* disable register anti-hang mechanism */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, mmUVD_POWER_STATUS), 0,
+ ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
+
+ /* set uvd status busy */
+ tmp = RREG32_SOC15(VCN, inst, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
+ WREG32_SOC15(VCN, inst, mmUVD_STATUS, tmp);
+
if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
return 0;
/*SW clock gating */
vcn_v2_5_disable_clock_gating(adev);
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
- /* enable VCPU clock */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
- UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
-
- /* disable master interrupt */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0,
- ~UVD_MASTINT_EN__VCPU_EN_MASK);
-
- /* setup mmUVD_LMI_CTRL */
- tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL);
- tmp &= ~0xff;
- WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL, tmp | 0x8|
- UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
- UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
- UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
- UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
-
- /* setup mmUVD_MPC_CNTL */
- tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL);
- tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
- tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
- WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp);
-
- /* setup UVD_MPC_SET_MUXA0 */
- WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXA0,
- ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
- (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
- (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
- (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
-
- /* setup UVD_MPC_SET_MUXB0 */
- WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXB0,
- ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
- (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
- (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
- (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
-
- /* setup mmUVD_MPC_SET_MUX */
- WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUX,
- ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
- (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
- (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
- }
+ if (adev->vcn.harvest_config & (1 << inst))
+ return 0;
+
+ /* enable VCPU clock */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, mmUVD_VCPU_CNTL),
+ UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
+
+ /* disable master interrupt */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, mmUVD_MASTINT_EN), 0,
+ ~UVD_MASTINT_EN__VCPU_EN_MASK);
+
+ /* setup mmUVD_LMI_CTRL */
+ tmp = RREG32_SOC15(VCN, inst, mmUVD_LMI_CTRL);
+ tmp &= ~0xff;
+ WREG32_SOC15(VCN, inst, mmUVD_LMI_CTRL, tmp | 0x8|
+ UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
+ UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
+ UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
+ UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
+
+ /* setup mmUVD_MPC_CNTL */
+ tmp = RREG32_SOC15(VCN, inst, mmUVD_MPC_CNTL);
+ tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
+ tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
+ WREG32_SOC15(VCN, inst, mmUVD_MPC_CNTL, tmp);
+
+ /* setup UVD_MPC_SET_MUXA0 */
+ WREG32_SOC15(VCN, inst, mmUVD_MPC_SET_MUXA0,
+ ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
+ (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
+ (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
+ (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
+
+ /* setup UVD_MPC_SET_MUXB0 */
+ WREG32_SOC15(VCN, inst, mmUVD_MPC_SET_MUXB0,
+ ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
+ (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
+ (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
+ (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
+
+ /* setup mmUVD_MPC_SET_MUX */
+ WREG32_SOC15(VCN, inst, mmUVD_MPC_SET_MUX,
+ ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
+ (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
+ (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
vcn_v2_5_mc_resume(adev);
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
- if (adev->vcn.harvest_config & (1 << i))
- continue;
- /* VCN global tiling registers */
- WREG32_SOC15(VCN, i, mmUVD_GFX8_ADDR_CONFIG,
- adev->gfx.config.gb_addr_config);
- WREG32_SOC15(VCN, i, mmUVD_GFX8_ADDR_CONFIG,
- adev->gfx.config.gb_addr_config);
+ volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst].fw_shared.cpu_addr;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return 0;
+
+ /* VCN global tiling registers */
+ WREG32_SOC15(VCN, inst, mmUVD_GFX8_ADDR_CONFIG,
+ adev->gfx.config.gb_addr_config);
+ WREG32_SOC15(VCN, inst, mmUVD_GFX8_ADDR_CONFIG,
+ adev->gfx.config.gb_addr_config);
- /* enable LMI MC and UMC channels */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0,
- ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
+ /* enable LMI MC and UMC channels */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, mmUVD_LMI_CTRL2), 0,
+ ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
- /* unblock VCPU register access */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 0,
- ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
+ /* unblock VCPU register access */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, mmUVD_RB_ARB_CTRL), 0,
+ ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
- WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
- ~UVD_VCPU_CNTL__BLK_RST_MASK);
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, mmUVD_VCPU_CNTL), 0,
+ ~UVD_VCPU_CNTL__BLK_RST_MASK);
- for (k = 0; k < 10; ++k) {
- uint32_t status;
-
- for (j = 0; j < 100; ++j) {
- status = RREG32_SOC15(VCN, i, mmUVD_STATUS);
- if (status & 2)
- break;
- if (amdgpu_emu_mode == 1)
- msleep(500);
- else
- mdelay(10);
- }
- r = 0;
+ for (k = 0; k < 10; ++k) {
+ uint32_t status;
+
+ for (j = 0; j < 100; ++j) {
+ status = RREG32_SOC15(VCN, inst, mmUVD_STATUS);
if (status & 2)
break;
+ if (amdgpu_emu_mode == 1)
+ msleep(500);
+ else
+ mdelay(10);
+ }
+ r = 0;
+ if (status & 2)
+ break;
- DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n");
- WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
- UVD_VCPU_CNTL__BLK_RST_MASK,
- ~UVD_VCPU_CNTL__BLK_RST_MASK);
- mdelay(10);
- WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
- ~UVD_VCPU_CNTL__BLK_RST_MASK);
+ DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n");
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, mmUVD_VCPU_CNTL),
+ UVD_VCPU_CNTL__BLK_RST_MASK,
+ ~UVD_VCPU_CNTL__BLK_RST_MASK);
+ mdelay(10);
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, mmUVD_VCPU_CNTL), 0,
+ ~UVD_VCPU_CNTL__BLK_RST_MASK);
- mdelay(10);
- r = -1;
- }
+ mdelay(10);
+ r = -1;
+ }
- if (r) {
- DRM_ERROR("VCN decode not responding, giving up!!!\n");
- return r;
- }
+ if (r) {
+ DRM_ERROR("VCN decode not responding, giving up!!!\n");
+ return r;
+ }
- /* enable master interrupt */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN),
- UVD_MASTINT_EN__VCPU_EN_MASK,
- ~UVD_MASTINT_EN__VCPU_EN_MASK);
+ /* enable master interrupt */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, mmUVD_MASTINT_EN),
+ UVD_MASTINT_EN__VCPU_EN_MASK,
+ ~UVD_MASTINT_EN__VCPU_EN_MASK);
- /* clear the busy bit of VCN_STATUS */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0,
- ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
+ /* clear the busy bit of VCN_STATUS */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, mmUVD_STATUS), 0,
+ ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
- WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_VMID, 0);
+ WREG32_SOC15(VCN, inst, mmUVD_LMI_RBC_RB_VMID, 0);
- ring = &adev->vcn.inst[i].ring_dec;
- /* force RBC into idle state */
- rb_bufsz = order_base_2(ring->ring_size);
- tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
- tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
- tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
- tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
- tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
- WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp);
+ ring = &adev->vcn.inst[inst].ring_dec;
+ /* force RBC into idle state */
+ rb_bufsz = order_base_2(ring->ring_size);
+ tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
+ tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
+ tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
+ tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
+ tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
+ WREG32_SOC15(VCN, inst, mmUVD_RBC_RB_CNTL, tmp);
- fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET;
- /* program the RB_BASE for ring buffer */
- WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
- lower_32_bits(ring->gpu_addr));
- WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
- upper_32_bits(ring->gpu_addr));
+ fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET;
+ /* program the RB_BASE for ring buffer */
+ WREG32_SOC15(VCN, inst, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
+ lower_32_bits(ring->gpu_addr));
+ WREG32_SOC15(VCN, inst, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
+ upper_32_bits(ring->gpu_addr));
- /* Initialize the ring buffer's read and write pointers */
- WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0);
+ /* Initialize the ring buffer's read and write pointers */
+ WREG32_SOC15(VCN, inst, mmUVD_RBC_RB_RPTR, 0);
- ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR);
- WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR,
- lower_32_bits(ring->wptr));
- fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET;
+ ring->wptr = RREG32_SOC15(VCN, inst, mmUVD_RBC_RB_RPTR);
+ WREG32_SOC15(VCN, inst, mmUVD_RBC_RB_WPTR,
+ lower_32_bits(ring->wptr));
+ fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET;
- fw_shared->multi_queue.encode_generalpurpose_queue_mode |= FW_QUEUE_RING_RESET;
- ring = &adev->vcn.inst[i].ring_enc[0];
- WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
- WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
- WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr);
- WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
- WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4);
- fw_shared->multi_queue.encode_generalpurpose_queue_mode &= ~FW_QUEUE_RING_RESET;
-
- fw_shared->multi_queue.encode_lowlatency_queue_mode |= FW_QUEUE_RING_RESET;
- ring = &adev->vcn.inst[i].ring_enc[1];
- WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
- WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
- WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring->gpu_addr);
- WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
- WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4);
- fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET;
- }
+ fw_shared->multi_queue.encode_generalpurpose_queue_mode |= FW_QUEUE_RING_RESET;
+ ring = &adev->vcn.inst[inst].ring_enc[0];
+ WREG32_SOC15(VCN, inst, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
+ WREG32_SOC15(VCN, inst, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
+ WREG32_SOC15(VCN, inst, mmUVD_RB_BASE_LO, ring->gpu_addr);
+ WREG32_SOC15(VCN, inst, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
+ WREG32_SOC15(VCN, inst, mmUVD_RB_SIZE, ring->ring_size / 4);
+ fw_shared->multi_queue.encode_generalpurpose_queue_mode &= ~FW_QUEUE_RING_RESET;
+
+ fw_shared->multi_queue.encode_lowlatency_queue_mode |= FW_QUEUE_RING_RESET;
+ ring = &adev->vcn.inst[inst].ring_enc[1];
+ WREG32_SOC15(VCN, inst, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
+ WREG32_SOC15(VCN, inst, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
+ WREG32_SOC15(VCN, inst, mmUVD_RB_BASE_LO2, ring->gpu_addr);
+ WREG32_SOC15(VCN, inst, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
+ WREG32_SOC15(VCN, inst, mmUVD_RB_SIZE2, ring->ring_size / 4);
+ fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET;
return 0;
}
@@ -1427,70 +1421,69 @@ static int vcn_v2_5_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)
return 0;
}
-static int vcn_v2_5_stop(struct amdgpu_device *adev)
+static int vcn_v2_5_stop(struct amdgpu_device *adev, unsigned int inst)
{
uint32_t tmp;
- int i, r = 0;
+ int r = 0;
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
- if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
- r = vcn_v2_5_stop_dpg_mode(adev, i);
- continue;
- }
+ if (adev->vcn.harvest_config & (1 << inst))
+ goto done;
- /* wait for vcn idle */
- r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7);
- if (r)
- return r;
+ if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
+ r = vcn_v2_5_stop_dpg_mode(adev, inst);
+ goto done;
+ }
- tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
- UVD_LMI_STATUS__READ_CLEAN_MASK |
- UVD_LMI_STATUS__WRITE_CLEAN_MASK |
- UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
- r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp);
- if (r)
- return r;
+ /* wait for vcn idle */
+ r = SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7);
+ if (r)
+ return r;
- /* block LMI UMC channel */
- tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2);
- tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
- WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp);
+ tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
+ UVD_LMI_STATUS__READ_CLEAN_MASK |
+ UVD_LMI_STATUS__WRITE_CLEAN_MASK |
+ UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
+ r = SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_LMI_STATUS, tmp, tmp);
+ if (r)
+ return r;
- tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK|
- UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
- r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp);
- if (r)
- return r;
+ /* block LMI UMC channel */
+ tmp = RREG32_SOC15(VCN, inst, mmUVD_LMI_CTRL2);
+ tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
+ WREG32_SOC15(VCN, inst, mmUVD_LMI_CTRL2, tmp);
- /* block VCPU register access */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL),
- UVD_RB_ARB_CTRL__VCPU_DIS_MASK,
- ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
+ tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK|
+ UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
+ r = SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_LMI_STATUS, tmp, tmp);
+ if (r)
+ return r;
- /* reset VCPU */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
- UVD_VCPU_CNTL__BLK_RST_MASK,
- ~UVD_VCPU_CNTL__BLK_RST_MASK);
+ /* block VCPU register access */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, mmUVD_RB_ARB_CTRL),
+ UVD_RB_ARB_CTRL__VCPU_DIS_MASK,
+ ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
- /* disable VCPU clock */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
- ~(UVD_VCPU_CNTL__CLK_EN_MASK));
+ /* reset VCPU */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, mmUVD_VCPU_CNTL),
+ UVD_VCPU_CNTL__BLK_RST_MASK,
+ ~UVD_VCPU_CNTL__BLK_RST_MASK);
- /* clear status */
- WREG32_SOC15(VCN, i, mmUVD_STATUS, 0);
+ /* disable VCPU clock */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, mmUVD_VCPU_CNTL), 0,
+ ~(UVD_VCPU_CNTL__CLK_EN_MASK));
- vcn_v2_5_enable_clock_gating(adev);
+ /* clear status */
+ WREG32_SOC15(VCN, inst, mmUVD_STATUS, 0);
- /* enable register anti-hang mechanism */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_POWER_STATUS),
- UVD_POWER_STATUS__UVD_POWER_STATUS_MASK,
- ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
- }
+ vcn_v2_5_enable_clock_gating(adev);
+ /* enable register anti-hang mechanism */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, mmUVD_POWER_STATUS),
+ UVD_POWER_STATUS__UVD_POWER_STATUS_MASK,
+ ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
+done:
if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_uvd(adev, false);
+ amdgpu_dpm_enable_vcn(adev, false, inst);
return 0;
}
@@ -1829,23 +1822,22 @@ static int vcn_v2_5_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
struct amdgpu_device *adev = ip_block->adev;
+ int inst = ip_block->instance;
int ret;
if (amdgpu_sriov_vf(adev))
return 0;
- for (int i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (state == adev->vcn.cur_state[i])
- return 0;
+ if (state == adev->vcn.cur_state[inst])
+ return 0;
- if (state == AMD_PG_STATE_GATE)
- ret = vcn_v2_5_stop(adev);
- else
- ret = vcn_v2_5_start(adev);
+ if (state == AMD_PG_STATE_GATE)
+ ret = vcn_v2_5_stop(adev, inst);
+ else
+ ret = vcn_v2_5_start(adev, inst);
- if (!ret)
- adev->vcn.cur_state[i] = state;
- }
+ if (!ret)
+ adev->vcn.cur_state[inst] = state;
return ret;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH 13/18] drm/amdgpu: power vcn 3_0 by instance
2024-10-02 4:36 [PATCH 00/18] Separating vcn power management by instance boyuan.zhang
` (11 preceding siblings ...)
2024-10-02 4:36 ` [PATCH 12/18] drm/amdgpu: power vcn 2_5 by instance boyuan.zhang
@ 2024-10-02 4:36 ` boyuan.zhang
2024-10-02 4:36 ` [PATCH 14/18] drm/amdgpu: power vcn 4_0 " boyuan.zhang
` (4 subsequent siblings)
17 siblings, 0 replies; 29+ messages in thread
From: boyuan.zhang @ 2024-10-02 4:36 UTC (permalink / raw)
To: amd-gfx, leo.liu, christian.koenig, alexander.deucher,
sunil.khatri
Cc: Boyuan Zhang
From: Boyuan Zhang <boyuan.zhang@amd.com>
For vcn 3_0, add ip_block for each vcn instance during discovery stage.
And only powering on/off one of the vcn instance using the
instance value stored in ip_block, instead of powering on/off all
vcn instances. Modify the existing functions to use the instance value
in ip_block, and remove the original for loop for all vcn instances.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 3 +-
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 608 +++++++++---------
2 files changed, 303 insertions(+), 308 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index 6b9c974da0c4..78b673b3ec6f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -2335,7 +2335,8 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev)
case IP_VERSION(3, 1, 1):
case IP_VERSION(3, 1, 2):
case IP_VERSION(3, 0, 2):
- amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i)
+ amdgpu_device_ip_block_add_instance(adev, &vcn_v3_0_ip_block, i);
if (!amdgpu_sriov_vf(adev))
amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
break;
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index 65d648429825..7f3275cff240 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -160,7 +160,7 @@ static int vcn_v3_0_early_init(struct amdgpu_ip_block *ip_block)
static int vcn_v3_0_sw_init(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_ring *ring;
- int i, j, r;
+ int inst = ip_block->instance, j, r;
int vcn_doorbell_index = 0;
uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_3_0);
uint32_t *ptr;
@@ -189,93 +189,91 @@ static int vcn_v3_0_sw_init(struct amdgpu_ip_block *ip_block)
vcn_doorbell_index = vcn_doorbell_index << 1;
}
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
- volatile struct amdgpu_fw_shared *fw_shared;
+ volatile struct amdgpu_fw_shared *fw_shared;
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ goto done;
+
+ adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET;
+ adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET;
+ adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET;
+ adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET;
+ adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET;
+ adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET;
+
+ adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET;
+ adev->vcn.inst[inst].external.scratch9 = SOC15_REG_OFFSET(VCN, inst, mmUVD_SCRATCH9);
+ adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET;
+ adev->vcn.inst[inst].external.data0 = SOC15_REG_OFFSET(VCN, inst, mmUVD_GPCOM_VCPU_DATA0);
+ adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET;
+ adev->vcn.inst[inst].external.data1 = SOC15_REG_OFFSET(VCN, inst, mmUVD_GPCOM_VCPU_DATA1);
+ adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET;
+ adev->vcn.inst[inst].external.cmd = SOC15_REG_OFFSET(VCN, inst, mmUVD_GPCOM_VCPU_CMD);
+ adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET;
+ adev->vcn.inst[inst].external.nop = SOC15_REG_OFFSET(VCN, inst, mmUVD_NO_OP);
+
+ /* VCN DEC TRAP */
+ r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[inst],
+ VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst[inst].irq);
+ if (r)
+ return r;
- adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET;
- adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET;
- adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET;
- adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET;
- adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET;
- adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET;
-
- adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET;
- adev->vcn.inst[i].external.scratch9 = SOC15_REG_OFFSET(VCN, i, mmUVD_SCRATCH9);
- adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET;
- adev->vcn.inst[i].external.data0 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA0);
- adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET;
- adev->vcn.inst[i].external.data1 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA1);
- adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET;
- adev->vcn.inst[i].external.cmd = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_CMD);
- adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET;
- adev->vcn.inst[i].external.nop = SOC15_REG_OFFSET(VCN, i, mmUVD_NO_OP);
-
- /* VCN DEC TRAP */
- r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
- VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst[i].irq);
+ atomic_set(&adev->vcn.inst[inst].sched_score, 0);
+
+ ring = &adev->vcn.inst[inst].ring_dec;
+ ring->use_doorbell = true;
+ if (amdgpu_sriov_vf(adev)) {
+ ring->doorbell_index = vcn_doorbell_index + inst * (adev->vcn.num_enc_rings + 1);
+ } else {
+ ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * inst;
+ }
+ ring->vm_hub = AMDGPU_MMHUB0(0);
+ sprintf(ring->name, "vcn_dec_%d", inst);
+ r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[inst].irq, 0,
+ AMDGPU_RING_PRIO_DEFAULT,
+ &adev->vcn.inst[inst].sched_score);
+ if (r)
+ return r;
+
+ for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
+ enum amdgpu_ring_priority_level hw_prio = amdgpu_vcn_get_enc_ring_prio(j);
+
+ /* VCN ENC TRAP */
+ r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[inst],
+ j + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[inst].irq);
if (r)
return r;
- atomic_set(&adev->vcn.inst[i].sched_score, 0);
-
- ring = &adev->vcn.inst[i].ring_dec;
+ ring = &adev->vcn.inst[inst].ring_enc[j];
ring->use_doorbell = true;
if (amdgpu_sriov_vf(adev)) {
- ring->doorbell_index = vcn_doorbell_index + i * (adev->vcn.num_enc_rings + 1);
+ ring->doorbell_index = vcn_doorbell_index + inst * (adev->vcn.num_enc_rings + 1) + 1 + j;
} else {
- ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i;
+ ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + j + 8 * inst;
}
ring->vm_hub = AMDGPU_MMHUB0(0);
- sprintf(ring->name, "vcn_dec_%d", i);
- r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,
- AMDGPU_RING_PRIO_DEFAULT,
- &adev->vcn.inst[i].sched_score);
+ sprintf(ring->name, "vcn_enc_%d.%d", inst, j);
+ r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[inst].irq, 0,
+ hw_prio, &adev->vcn.inst[inst].sched_score);
if (r)
return r;
-
- for (j = 0; j < adev->vcn.num_enc_rings; ++j) {
- enum amdgpu_ring_priority_level hw_prio = amdgpu_vcn_get_enc_ring_prio(j);
-
- /* VCN ENC TRAP */
- r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
- j + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq);
- if (r)
- return r;
-
- ring = &adev->vcn.inst[i].ring_enc[j];
- ring->use_doorbell = true;
- if (amdgpu_sriov_vf(adev)) {
- ring->doorbell_index = vcn_doorbell_index + i * (adev->vcn.num_enc_rings + 1) + 1 + j;
- } else {
- ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + j + 8 * i;
- }
- ring->vm_hub = AMDGPU_MMHUB0(0);
- sprintf(ring->name, "vcn_enc_%d.%d", i, j);
- r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,
- hw_prio, &adev->vcn.inst[i].sched_score);
- if (r)
- return r;
- }
-
- fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
- fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SW_RING_FLAG) |
- cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG) |
- cpu_to_le32(AMDGPU_VCN_FW_SHARED_FLAG_0_RB);
- fw_shared->sw_ring.is_enabled = cpu_to_le32(DEC_SW_RING_ENABLED);
- fw_shared->present_flag_0 |= AMDGPU_VCN_SMU_VERSION_INFO_FLAG;
- if (amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(3, 1, 2))
- fw_shared->smu_interface_info.smu_interface_type = 2;
- else if (amdgpu_ip_version(adev, UVD_HWIP, 0) ==
- IP_VERSION(3, 1, 1))
- fw_shared->smu_interface_info.smu_interface_type = 1;
-
- if (amdgpu_vcnfw_log)
- amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]);
}
+ fw_shared = adev->vcn.inst[inst].fw_shared.cpu_addr;
+ fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SW_RING_FLAG) |
+ cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG) |
+ cpu_to_le32(AMDGPU_VCN_FW_SHARED_FLAG_0_RB);
+ fw_shared->sw_ring.is_enabled = cpu_to_le32(DEC_SW_RING_ENABLED);
+ fw_shared->present_flag_0 |= AMDGPU_VCN_SMU_VERSION_INFO_FLAG;
+ if (amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(3, 1, 2))
+ fw_shared->smu_interface_info.smu_interface_type = 2;
+ else if (amdgpu_ip_version(adev, UVD_HWIP, 0) ==
+ IP_VERSION(3, 1, 1))
+ fw_shared->smu_interface_info.smu_interface_type = 1;
+
+ if (amdgpu_vcnfw_log)
+ amdgpu_vcn_fwlog_init(&adev->vcn.inst[inst]);
+done:
if (amdgpu_sriov_vf(adev)) {
r = amdgpu_virt_alloc_mm_table(adev);
if (r)
@@ -1137,190 +1135,188 @@ static int vcn_v3_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo
return 0;
}
-static int vcn_v3_0_start(struct amdgpu_device *adev)
+static int vcn_v3_0_start(struct amdgpu_device *adev, unsigned int inst)
{
volatile struct amdgpu_fw_shared *fw_shared;
struct amdgpu_ring *ring;
uint32_t rb_bufsz, tmp;
- int i, j, k, r;
+ int j, k, r;
if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_uvd(adev, true);
+ amdgpu_dpm_enable_vcn(adev, true, inst);
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return 0;
- if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
- r = vcn_v3_0_start_dpg_mode(adev, i, adev->vcn.indirect_sram);
- continue;
- }
+ if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
+ r = vcn_v3_0_start_dpg_mode(adev, inst, adev->vcn.indirect_sram);
+ return r;
+ }
- /* disable VCN power gating */
- vcn_v3_0_disable_static_power_gating(adev, i);
-
- /* set VCN status busy */
- tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
- WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp);
-
- /*SW clock gating */
- vcn_v3_0_disable_clock_gating(adev, i);
-
- /* enable VCPU clock */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
- UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
-
- /* disable master interrupt */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0,
- ~UVD_MASTINT_EN__VCPU_EN_MASK);
-
- /* enable LMI MC and UMC channels */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0,
- ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
-
- tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET);
- tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
- tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
- WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp);
-
- /* setup mmUVD_LMI_CTRL */
- tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL);
- WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL, tmp |
- UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
- UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
- UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
- UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
-
- /* setup mmUVD_MPC_CNTL */
- tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL);
- tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
- tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
- WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp);
-
- /* setup UVD_MPC_SET_MUXA0 */
- WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXA0,
- ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
- (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
- (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
- (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
-
- /* setup UVD_MPC_SET_MUXB0 */
- WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXB0,
- ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
- (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
- (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
- (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
-
- /* setup mmUVD_MPC_SET_MUX */
- WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUX,
- ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
- (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
- (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
-
- vcn_v3_0_mc_resume(adev, i);
-
- /* VCN global tiling registers */
- WREG32_SOC15(VCN, i, mmUVD_GFX10_ADDR_CONFIG,
- adev->gfx.config.gb_addr_config);
-
- /* unblock VCPU register access */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 0,
- ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
-
- /* release VCPU reset to boot */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
- ~UVD_VCPU_CNTL__BLK_RST_MASK);
+ /* disable VCN power gating */
+ vcn_v3_0_disable_static_power_gating(adev, inst);
- for (j = 0; j < 10; ++j) {
- uint32_t status;
+ /* set VCN status busy */
+ tmp = RREG32_SOC15(VCN, inst, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
+ WREG32_SOC15(VCN, inst, mmUVD_STATUS, tmp);
- for (k = 0; k < 100; ++k) {
- status = RREG32_SOC15(VCN, i, mmUVD_STATUS);
- if (status & 2)
- break;
- mdelay(10);
- }
- r = 0;
- if (status & 2)
- break;
+ /*SW clock gating */
+ vcn_v3_0_disable_clock_gating(adev, inst);
- DRM_ERROR("VCN[%d] decode not responding, trying to reset the VCPU!!!\n", i);
- WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
- UVD_VCPU_CNTL__BLK_RST_MASK,
- ~UVD_VCPU_CNTL__BLK_RST_MASK);
- mdelay(10);
- WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
- ~UVD_VCPU_CNTL__BLK_RST_MASK);
+ /* enable VCPU clock */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, mmUVD_VCPU_CNTL),
+ UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
+
+ /* disable master interrupt */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, mmUVD_MASTINT_EN), 0,
+ ~UVD_MASTINT_EN__VCPU_EN_MASK);
+
+ /* enable LMI MC and UMC channels */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, mmUVD_LMI_CTRL2), 0,
+ ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
+
+ tmp = RREG32_SOC15(VCN, inst, mmUVD_SOFT_RESET);
+ tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
+ tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
+ WREG32_SOC15(VCN, inst, mmUVD_SOFT_RESET, tmp);
+
+ /* setup mmUVD_LMI_CTRL */
+ tmp = RREG32_SOC15(VCN, inst, mmUVD_LMI_CTRL);
+ WREG32_SOC15(VCN, inst, mmUVD_LMI_CTRL, tmp |
+ UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
+ UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
+ UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
+ UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
+
+ /* setup mmUVD_MPC_CNTL */
+ tmp = RREG32_SOC15(VCN, inst, mmUVD_MPC_CNTL);
+ tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
+ tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
+ WREG32_SOC15(VCN, inst, mmUVD_MPC_CNTL, tmp);
+
+ /* setup UVD_MPC_SET_MUXA0 */
+ WREG32_SOC15(VCN, inst, mmUVD_MPC_SET_MUXA0,
+ ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
+ (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
+ (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
+ (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
+
+ /* setup UVD_MPC_SET_MUXB0 */
+ WREG32_SOC15(VCN, inst, mmUVD_MPC_SET_MUXB0,
+ ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
+ (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
+ (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
+ (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
+
+ /* setup mmUVD_MPC_SET_MUX */
+ WREG32_SOC15(VCN, inst, mmUVD_MPC_SET_MUX,
+ ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
+ (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
+ (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
+
+ vcn_v3_0_mc_resume(adev, inst);
+
+ /* VCN global tiling registers */
+ WREG32_SOC15(VCN, inst, mmUVD_GFX10_ADDR_CONFIG,
+ adev->gfx.config.gb_addr_config);
+ /* unblock VCPU register access */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, mmUVD_RB_ARB_CTRL), 0,
+ ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
+
+ /* release VCPU reset to boot */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, mmUVD_VCPU_CNTL), 0,
+ ~UVD_VCPU_CNTL__BLK_RST_MASK);
+
+ for (j = 0; j < 10; ++j) {
+ uint32_t status;
+
+ for (k = 0; k < 100; ++k) {
+ status = RREG32_SOC15(VCN, inst, mmUVD_STATUS);
+ if (status & 2)
+ break;
mdelay(10);
- r = -1;
}
+ r = 0;
+ if (status & 2)
+ break;
- if (r) {
- DRM_ERROR("VCN[%d] decode not responding, giving up!!!\n", i);
- return r;
- }
+ DRM_ERROR("VCN[%d] decode not responding, trying to reset the VCPU!!!\n", inst);
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, mmUVD_VCPU_CNTL),
+ UVD_VCPU_CNTL__BLK_RST_MASK,
+ ~UVD_VCPU_CNTL__BLK_RST_MASK);
+ mdelay(10);
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, mmUVD_VCPU_CNTL), 0,
+ ~UVD_VCPU_CNTL__BLK_RST_MASK);
- /* enable master interrupt */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN),
- UVD_MASTINT_EN__VCPU_EN_MASK,
- ~UVD_MASTINT_EN__VCPU_EN_MASK);
+ mdelay(10);
+ r = -1;
+ }
- /* clear the busy bit of VCN_STATUS */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0,
- ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
+ if (r) {
+ DRM_ERROR("VCN[%d] decode not responding, giving up!!!\n", inst);
+ return r;
+ }
- WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_VMID, 0);
+ /* enable master interrupt */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, mmUVD_MASTINT_EN),
+ UVD_MASTINT_EN__VCPU_EN_MASK,
+ ~UVD_MASTINT_EN__VCPU_EN_MASK);
- ring = &adev->vcn.inst[i].ring_dec;
- /* force RBC into idle state */
- rb_bufsz = order_base_2(ring->ring_size);
- tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
- tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
- tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
- tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
- tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
- WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp);
+ /* clear the busy bit of VCN_STATUS */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, mmUVD_STATUS), 0,
+ ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
+
+ WREG32_SOC15(VCN, inst, mmUVD_LMI_RBC_RB_VMID, 0);
+
+ ring = &adev->vcn.inst[inst].ring_dec;
+ /* force RBC into idle state */
+ rb_bufsz = order_base_2(ring->ring_size);
+ tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
+ tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
+ tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
+ tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
+ tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
+ WREG32_SOC15(VCN, inst, mmUVD_RBC_RB_CNTL, tmp);
- fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
- fw_shared->multi_queue.decode_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);
+ fw_shared = adev->vcn.inst[inst].fw_shared.cpu_addr;
+ fw_shared->multi_queue.decode_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);
- /* programm the RB_BASE for ring buffer */
- WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
- lower_32_bits(ring->gpu_addr));
- WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
- upper_32_bits(ring->gpu_addr));
+ /* programm the RB_BASE for ring buffer */
+ WREG32_SOC15(VCN, inst, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
+ lower_32_bits(ring->gpu_addr));
+ WREG32_SOC15(VCN, inst, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
+ upper_32_bits(ring->gpu_addr));
- /* Initialize the ring buffer's read and write pointers */
- WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0);
+ /* Initialize the ring buffer's read and write pointers */
+ WREG32_SOC15(VCN, inst, mmUVD_RBC_RB_RPTR, 0);
- WREG32_SOC15(VCN, i, mmUVD_SCRATCH2, 0);
- ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR);
- WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR,
- lower_32_bits(ring->wptr));
- fw_shared->rb.wptr = lower_32_bits(ring->wptr);
- fw_shared->multi_queue.decode_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET);
-
- if (amdgpu_ip_version(adev, UVD_HWIP, 0) !=
- IP_VERSION(3, 0, 33)) {
- fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);
- ring = &adev->vcn.inst[i].ring_enc[0];
- WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
- WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
- WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr);
- WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
- WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4);
- fw_shared->multi_queue.encode_generalpurpose_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET);
-
- fw_shared->multi_queue.encode_lowlatency_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);
- ring = &adev->vcn.inst[i].ring_enc[1];
- WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
- WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
- WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring->gpu_addr);
- WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
- WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4);
- fw_shared->multi_queue.encode_lowlatency_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET);
- }
+ WREG32_SOC15(VCN, inst, mmUVD_SCRATCH2, 0);
+ ring->wptr = RREG32_SOC15(VCN, inst, mmUVD_RBC_RB_RPTR);
+ WREG32_SOC15(VCN, inst, mmUVD_RBC_RB_WPTR,
+ lower_32_bits(ring->wptr));
+ fw_shared->rb.wptr = lower_32_bits(ring->wptr);
+ fw_shared->multi_queue.decode_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET);
+
+ if (amdgpu_ip_version(adev, UVD_HWIP, 0) !=
+ IP_VERSION(3, 0, 33)) {
+ fw_shared->multi_queue.encode_generalpurpose_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);
+ ring = &adev->vcn.inst[inst].ring_enc[0];
+ WREG32_SOC15(VCN, inst, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
+ WREG32_SOC15(VCN, inst, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
+ WREG32_SOC15(VCN, inst, mmUVD_RB_BASE_LO, ring->gpu_addr);
+ WREG32_SOC15(VCN, inst, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
+ WREG32_SOC15(VCN, inst, mmUVD_RB_SIZE, ring->ring_size / 4);
+ fw_shared->multi_queue.encode_generalpurpose_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET);
+
+ fw_shared->multi_queue.encode_lowlatency_queue_mode |= cpu_to_le32(FW_QUEUE_RING_RESET);
+ ring = &adev->vcn.inst[inst].ring_enc[1];
+ WREG32_SOC15(VCN, inst, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
+ WREG32_SOC15(VCN, inst, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
+ WREG32_SOC15(VCN, inst, mmUVD_RB_BASE_LO2, ring->gpu_addr);
+ WREG32_SOC15(VCN, inst, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
+ WREG32_SOC15(VCN, inst, mmUVD_RB_SIZE2, ring->ring_size / 4);
+ fw_shared->multi_queue.encode_lowlatency_queue_mode &= cpu_to_le32(~FW_QUEUE_RING_RESET);
}
return 0;
@@ -1566,77 +1562,76 @@ static int vcn_v3_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)
return 0;
}
-static int vcn_v3_0_stop(struct amdgpu_device *adev)
+static int vcn_v3_0_stop(struct amdgpu_device *adev, unsigned int inst)
{
uint32_t tmp;
- int i, r = 0;
+ int r = 0;
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ goto done;
- if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
- r = vcn_v3_0_stop_dpg_mode(adev, i);
- continue;
- }
+ if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
+ r = vcn_v3_0_stop_dpg_mode(adev, inst);
+ goto done;
+ }
- /* wait for vcn idle */
- r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7);
- if (r)
- return r;
+ /* wait for vcn idle */
+ r = SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7);
+ if (r)
+ return r;
- tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
- UVD_LMI_STATUS__READ_CLEAN_MASK |
- UVD_LMI_STATUS__WRITE_CLEAN_MASK |
- UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
- r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp);
- if (r)
- return r;
+ tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
+ UVD_LMI_STATUS__READ_CLEAN_MASK |
+ UVD_LMI_STATUS__WRITE_CLEAN_MASK |
+ UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
+ r = SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_LMI_STATUS, tmp, tmp);
+ if (r)
+ return r;
- /* disable LMI UMC channel */
- tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2);
- tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
- WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp);
- tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK|
- UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
- r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp);
- if (r)
- return r;
+ /* disable LMI UMC channel */
+ tmp = RREG32_SOC15(VCN, inst, mmUVD_LMI_CTRL2);
+ tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
+ WREG32_SOC15(VCN, inst, mmUVD_LMI_CTRL2, tmp);
+ tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK|
+ UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
+ r = SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_LMI_STATUS, tmp, tmp);
+ if (r)
+ return r;
- /* block VCPU register access */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL),
- UVD_RB_ARB_CTRL__VCPU_DIS_MASK,
- ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
+ /* block VCPU register access */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, mmUVD_RB_ARB_CTRL),
+ UVD_RB_ARB_CTRL__VCPU_DIS_MASK,
+ ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
- /* reset VCPU */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),
- UVD_VCPU_CNTL__BLK_RST_MASK,
- ~UVD_VCPU_CNTL__BLK_RST_MASK);
+ /* reset VCPU */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, mmUVD_VCPU_CNTL),
+ UVD_VCPU_CNTL__BLK_RST_MASK,
+ ~UVD_VCPU_CNTL__BLK_RST_MASK);
- /* disable VCPU clock */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,
- ~(UVD_VCPU_CNTL__CLK_EN_MASK));
+ /* disable VCPU clock */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, mmUVD_VCPU_CNTL), 0,
+ ~(UVD_VCPU_CNTL__CLK_EN_MASK));
- /* apply soft reset */
- tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET);
- tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
- WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp);
- tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET);
- tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
- WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp);
+ /* apply soft reset */
+ tmp = RREG32_SOC15(VCN, inst, mmUVD_SOFT_RESET);
+ tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
+ WREG32_SOC15(VCN, inst, mmUVD_SOFT_RESET, tmp);
+ tmp = RREG32_SOC15(VCN, inst, mmUVD_SOFT_RESET);
+ tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
+ WREG32_SOC15(VCN, inst, mmUVD_SOFT_RESET, tmp);
- /* clear status */
- WREG32_SOC15(VCN, i, mmUVD_STATUS, 0);
+ /* clear status */
+ WREG32_SOC15(VCN, inst, mmUVD_STATUS, 0);
- /* apply HW clock gating */
- vcn_v3_0_enable_clock_gating(adev, i);
+ /* apply HW clock gating */
+ vcn_v3_0_enable_clock_gating(adev, inst);
- /* enable VCN power gating */
- vcn_v3_0_enable_static_power_gating(adev, i);
- }
+ /* enable VCN power gating */
+ vcn_v3_0_enable_static_power_gating(adev, inst);
+done:
if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_uvd(adev, false);
+ amdgpu_dpm_enable_vcn(adev, false, inst);
return 0;
}
@@ -2162,29 +2157,28 @@ static int vcn_v3_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
struct amdgpu_device *adev = ip_block->adev;
+ int i = ip_block->instance;
int ret;
- for (int i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- /* for SRIOV, guest should not control VCN Power-gating
- * MMSCH FW should control Power-gating and clock-gating
- * guest should avoid touching CGC and PG
- */
- if (amdgpu_sriov_vf(adev)) {
- adev->vcn.cur_state[i] = AMD_PG_STATE_UNGATE;
- return 0;
- }
+ /* for SRIOV, guest should not control VCN Power-gating
+ * MMSCH FW should control Power-gating and clock-gating
+ * guest should avoid touching CGC and PG
+ */
+ if (amdgpu_sriov_vf(adev)) {
+ adev->vcn.cur_state[i] = AMD_PG_STATE_UNGATE;
+ return 0;
+ }
- if (state == adev->vcn.cur_state[i])
- return 0;
+ if (state == adev->vcn.cur_state[i])
+ return 0;
- if (state == AMD_PG_STATE_GATE)
- ret = vcn_v3_0_stop(adev);
- else
- ret = vcn_v3_0_start(adev);
+ if (state == AMD_PG_STATE_GATE)
+ ret = vcn_v3_0_stop(adev, i);
+ else
+ ret = vcn_v3_0_start(adev, i);
- if (!ret)
- adev->vcn.cur_state[i] = state;
- }
+ if (!ret)
+ adev->vcn.cur_state[i] = state;
return ret;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH 14/18] drm/amdgpu: power vcn 4_0 by instance
2024-10-02 4:36 [PATCH 00/18] Separating vcn power management by instance boyuan.zhang
` (12 preceding siblings ...)
2024-10-02 4:36 ` [PATCH 13/18] drm/amdgpu: power vcn 3_0 " boyuan.zhang
@ 2024-10-02 4:36 ` boyuan.zhang
2024-10-02 4:36 ` [PATCH 15/18] drm/amdgpu: power vcn 4_0_3 " boyuan.zhang
` (3 subsequent siblings)
17 siblings, 0 replies; 29+ messages in thread
From: boyuan.zhang @ 2024-10-02 4:36 UTC (permalink / raw)
To: amd-gfx, leo.liu, christian.koenig, alexander.deucher,
sunil.khatri
Cc: Boyuan Zhang
From: Boyuan Zhang <boyuan.zhang@amd.com>
For vcn 4_0, add ip_block for each vcn instance during discovery stage.
And only powering on/off one of the vcn instance using the
instance value stored in ip_block, instead of powering on/off all
vcn instances. Modify the existing functions to use the instance value
in ip_block, and remove the original for loop for all vcn instances.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 3 +-
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 532 +++++++++---------
2 files changed, 265 insertions(+), 270 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index 78b673b3ec6f..8d8107241a5a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -2346,7 +2346,8 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev)
case IP_VERSION(4, 0, 0):
case IP_VERSION(4, 0, 2):
case IP_VERSION(4, 0, 4):
- amdgpu_device_ip_block_add(adev, &vcn_v4_0_ip_block);
+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i)
+ amdgpu_device_ip_block_add_instance(adev, &vcn_v4_0_ip_block, i);
amdgpu_device_ip_block_add(adev, &jpeg_v4_0_ip_block);
break;
case IP_VERSION(4, 0, 3):
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
index 50198b72e579..4c774255b0fd 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
@@ -172,7 +172,8 @@ static int vcn_v4_0_sw_init(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_ring *ring;
struct amdgpu_device *adev = ip_block->adev;
- int i, r;
+ int inst = ip_block->instance, r;
+
uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0);
uint32_t *ptr;
@@ -186,45 +187,43 @@ static int vcn_v4_0_sw_init(struct amdgpu_ip_block *ip_block)
if (r)
return r;
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ goto done;
- /* Init instance 0 sched_score to 1, so it's scheduled after other instances */
- if (i == 0)
- atomic_set(&adev->vcn.inst[i].sched_score, 1);
- else
- atomic_set(&adev->vcn.inst[i].sched_score, 0);
+ /* Init instance 0 sched_score to 1, so it's scheduled after other instances */
+ if (inst == 0)
+ atomic_set(&adev->vcn.inst[inst].sched_score, 1);
+ else
+ atomic_set(&adev->vcn.inst[inst].sched_score, 0);
- /* VCN UNIFIED TRAP */
- r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
- VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq);
- if (r)
- return r;
+ /* VCN UNIFIED TRAP */
+ r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[inst],
+ VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[inst].irq);
+ if (r)
+ return r;
- /* VCN POISON TRAP */
- r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
- VCN_4_0__SRCID_UVD_POISON, &adev->vcn.inst[i].ras_poison_irq);
- if (r)
- return r;
+ /* VCN POISON TRAP */
+ r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[inst],
+ VCN_4_0__SRCID_UVD_POISON, &adev->vcn.inst[inst].ras_poison_irq);
+ if (r)
+ return r;
- ring = &adev->vcn.inst[i].ring_enc[0];
- ring->use_doorbell = true;
- if (amdgpu_sriov_vf(adev))
- ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + i * (adev->vcn.num_enc_rings + 1) + 1;
- else
- ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + 8 * i;
- ring->vm_hub = AMDGPU_MMHUB0(0);
- sprintf(ring->name, "vcn_unified_%d", i);
-
- r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,
- AMDGPU_RING_PRIO_0, &adev->vcn.inst[i].sched_score);
- if (r)
- return r;
+ ring = &adev->vcn.inst[inst].ring_enc[0];
+ ring->use_doorbell = true;
+ if (amdgpu_sriov_vf(adev))
+ ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + inst * (adev->vcn.num_enc_rings + 1) + 1;
+ else
+ ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + 8 * inst;
+ ring->vm_hub = AMDGPU_MMHUB0(0);
+ sprintf(ring->name, "vcn_unified_%d", inst);
- vcn_v4_0_fw_shared_init(adev, i);
- }
+ r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[inst].irq, 0,
+ AMDGPU_RING_PRIO_0, &adev->vcn.inst[inst].sched_score);
+ if (r)
+ return r;
+ vcn_v4_0_fw_shared_init(adev, inst);
+done:
if (amdgpu_sriov_vf(adev)) {
r = amdgpu_virt_alloc_mm_table(adev);
if (r)
@@ -1085,178 +1084,176 @@ static int vcn_v4_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo
*
* Start VCN block
*/
-static int vcn_v4_0_start(struct amdgpu_device *adev)
+static int vcn_v4_0_start(struct amdgpu_device *adev, unsigned int inst)
{
volatile struct amdgpu_vcn4_fw_shared *fw_shared;
struct amdgpu_ring *ring;
uint32_t tmp;
- int i, j, k, r;
+ int j, k, r;
if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_uvd(adev, true);
+ amdgpu_dpm_enable_vcn(adev, true, 1);
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return 0;
- fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
+ fw_shared = adev->vcn.inst[inst].fw_shared.cpu_addr;
- if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
- r = vcn_v4_0_start_dpg_mode(adev, i, adev->vcn.indirect_sram);
- continue;
+ if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
+ r = vcn_v4_0_start_dpg_mode(adev, inst, adev->vcn.indirect_sram);
+ return r;
+ }
+
+ /* disable VCN power gating */
+ vcn_v4_0_disable_static_power_gating(adev, inst);
+
+ /* set VCN status busy */
+ tmp = RREG32_SOC15(VCN, inst, regUVD_STATUS) | UVD_STATUS__UVD_BUSY;
+ WREG32_SOC15(VCN, inst, regUVD_STATUS, tmp);
+
+ /*SW clock gating */
+ vcn_v4_0_disable_clock_gating(adev, inst);
+
+ /* enable VCPU clock */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_VCPU_CNTL),
+ UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
+
+ /* disable master interrupt */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_MASTINT_EN), 0,
+ ~UVD_MASTINT_EN__VCPU_EN_MASK);
+
+ /* enable LMI MC and UMC channels */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_LMI_CTRL2), 0,
+ ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
+
+ tmp = RREG32_SOC15(VCN, inst, regUVD_SOFT_RESET);
+ tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
+ tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
+ WREG32_SOC15(VCN, inst, regUVD_SOFT_RESET, tmp);
+
+ /* setup regUVD_LMI_CTRL */
+ tmp = RREG32_SOC15(VCN, inst, regUVD_LMI_CTRL);
+ WREG32_SOC15(VCN, inst, regUVD_LMI_CTRL, tmp |
+ UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
+ UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
+ UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
+ UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
+
+ /* setup regUVD_MPC_CNTL */
+ tmp = RREG32_SOC15(VCN, inst, regUVD_MPC_CNTL);
+ tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
+ tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
+ WREG32_SOC15(VCN, inst, regUVD_MPC_CNTL, tmp);
+
+ /* setup UVD_MPC_SET_MUXA0 */
+ WREG32_SOC15(VCN, inst, regUVD_MPC_SET_MUXA0,
+ ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
+ (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
+ (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
+ (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
+
+ /* setup UVD_MPC_SET_MUXB0 */
+ WREG32_SOC15(VCN, inst, regUVD_MPC_SET_MUXB0,
+ ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
+ (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
+ (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
+ (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
+
+ /* setup UVD_MPC_SET_MUX */
+ WREG32_SOC15(VCN, inst, regUVD_MPC_SET_MUX,
+ ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
+ (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
+ (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
+
+ vcn_v4_0_mc_resume(adev, inst);
+
+ /* VCN global tiling registers */
+ WREG32_SOC15(VCN, inst, regUVD_GFX10_ADDR_CONFIG,
+ adev->gfx.config.gb_addr_config);
+
+ /* unblock VCPU register access */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_RB_ARB_CTRL), 0,
+ ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
+
+ /* release VCPU reset to boot */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_VCPU_CNTL), 0,
+ ~UVD_VCPU_CNTL__BLK_RST_MASK);
+
+ for (j = 0; j < 10; ++j) {
+ uint32_t status;
+
+ for (k = 0; k < 100; ++k) {
+ status = RREG32_SOC15(VCN, inst, regUVD_STATUS);
+ if (status & 2)
+ break;
+ mdelay(10);
+ if (amdgpu_emu_mode == 1)
+ msleep(1);
}
- /* disable VCN power gating */
- vcn_v4_0_disable_static_power_gating(adev, i);
-
- /* set VCN status busy */
- tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY;
- WREG32_SOC15(VCN, i, regUVD_STATUS, tmp);
-
- /*SW clock gating */
- vcn_v4_0_disable_clock_gating(adev, i);
-
- /* enable VCPU clock */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
- UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
-
- /* disable master interrupt */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 0,
- ~UVD_MASTINT_EN__VCPU_EN_MASK);
-
- /* enable LMI MC and UMC channels */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_LMI_CTRL2), 0,
- ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
-
- tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);
- tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
- tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
- WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);
-
- /* setup regUVD_LMI_CTRL */
- tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL);
- WREG32_SOC15(VCN, i, regUVD_LMI_CTRL, tmp |
- UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
- UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
- UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
- UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
-
- /* setup regUVD_MPC_CNTL */
- tmp = RREG32_SOC15(VCN, i, regUVD_MPC_CNTL);
- tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
- tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
- WREG32_SOC15(VCN, i, regUVD_MPC_CNTL, tmp);
-
- /* setup UVD_MPC_SET_MUXA0 */
- WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXA0,
- ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
- (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
- (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
- (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
-
- /* setup UVD_MPC_SET_MUXB0 */
- WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXB0,
- ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
- (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
- (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
- (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
-
- /* setup UVD_MPC_SET_MUX */
- WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUX,
- ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
- (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
- (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
-
- vcn_v4_0_mc_resume(adev, i);
-
- /* VCN global tiling registers */
- WREG32_SOC15(VCN, i, regUVD_GFX10_ADDR_CONFIG,
- adev->gfx.config.gb_addr_config);
-
- /* unblock VCPU register access */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 0,
- ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
-
- /* release VCPU reset to boot */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,
- ~UVD_VCPU_CNTL__BLK_RST_MASK);
-
- for (j = 0; j < 10; ++j) {
- uint32_t status;
-
- for (k = 0; k < 100; ++k) {
- status = RREG32_SOC15(VCN, i, regUVD_STATUS);
- if (status & 2)
- break;
- mdelay(10);
- if (amdgpu_emu_mode == 1)
- msleep(1);
+ if (amdgpu_emu_mode == 1) {
+ r = -1;
+ if (status & 2) {
+ r = 0;
+ break;
}
+ } else {
+ r = 0;
+ if (status & 2)
+ break;
- if (amdgpu_emu_mode == 1) {
- r = -1;
- if (status & 2) {
- r = 0;
- break;
- }
- } else {
- r = 0;
- if (status & 2)
- break;
-
- dev_err(adev->dev, "VCN[%d] is not responding, trying to reset the VCPU!!!\n", i);
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
- UVD_VCPU_CNTL__BLK_RST_MASK,
- ~UVD_VCPU_CNTL__BLK_RST_MASK);
- mdelay(10);
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,
+ dev_err(adev->dev, "VCN[%d] is not responding, trying to reset the VCPU!!!\n", inst);
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_VCPU_CNTL),
+ UVD_VCPU_CNTL__BLK_RST_MASK,
~UVD_VCPU_CNTL__BLK_RST_MASK);
+ mdelay(10);
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_VCPU_CNTL), 0,
+ ~UVD_VCPU_CNTL__BLK_RST_MASK);
- mdelay(10);
- r = -1;
- }
- }
-
- if (r) {
- dev_err(adev->dev, "VCN[%d] is not responding, giving up!!!\n", i);
- return r;
+ mdelay(10);
+ r = -1;
}
+ }
- /* enable master interrupt */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN),
- UVD_MASTINT_EN__VCPU_EN_MASK,
- ~UVD_MASTINT_EN__VCPU_EN_MASK);
-
- /* clear the busy bit of VCN_STATUS */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_STATUS), 0,
- ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
-
- ring = &adev->vcn.inst[i].ring_enc[0];
- WREG32_SOC15(VCN, i, regVCN_RB1_DB_CTRL,
- ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT |
- VCN_RB1_DB_CTRL__EN_MASK);
-
- WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring->gpu_addr);
- WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
- WREG32_SOC15(VCN, i, regUVD_RB_SIZE, ring->ring_size / 4);
-
- tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);
- tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK);
- WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);
- fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET;
- WREG32_SOC15(VCN, i, regUVD_RB_RPTR, 0);
- WREG32_SOC15(VCN, i, regUVD_RB_WPTR, 0);
-
- tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR);
- WREG32_SOC15(VCN, i, regUVD_RB_WPTR, tmp);
- ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR);
-
- tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);
- tmp |= VCN_RB_ENABLE__RB1_EN_MASK;
- WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);
- fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);
+ if (r) {
+ dev_err(adev->dev, "VCN[%d] is not responding, giving up!!!\n", inst);
+ return r;
}
+ /* enable master interrupt */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_MASTINT_EN),
+ UVD_MASTINT_EN__VCPU_EN_MASK,
+ ~UVD_MASTINT_EN__VCPU_EN_MASK);
+
+ /* clear the busy bit of VCN_STATUS */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_STATUS), 0,
+ ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
+
+ ring = &adev->vcn.inst[inst].ring_enc[0];
+ WREG32_SOC15(VCN, inst, regVCN_RB1_DB_CTRL,
+ ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT |
+ VCN_RB1_DB_CTRL__EN_MASK);
+
+ WREG32_SOC15(VCN, inst, regUVD_RB_BASE_LO, ring->gpu_addr);
+ WREG32_SOC15(VCN, inst, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
+ WREG32_SOC15(VCN, inst, regUVD_RB_SIZE, ring->ring_size / 4);
+
+ tmp = RREG32_SOC15(VCN, inst, regVCN_RB_ENABLE);
+ tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK);
+ WREG32_SOC15(VCN, inst, regVCN_RB_ENABLE, tmp);
+ fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET;
+ WREG32_SOC15(VCN, inst, regUVD_RB_RPTR, 0);
+ WREG32_SOC15(VCN, inst, regUVD_RB_WPTR, 0);
+
+ tmp = RREG32_SOC15(VCN, inst, regUVD_RB_RPTR);
+ WREG32_SOC15(VCN, inst, regUVD_RB_WPTR, tmp);
+ ring->wptr = RREG32_SOC15(VCN, inst, regUVD_RB_WPTR);
+
+ tmp = RREG32_SOC15(VCN, inst, regVCN_RB_ENABLE);
+ tmp |= VCN_RB_ENABLE__RB1_EN_MASK;
+ WREG32_SOC15(VCN, inst, regVCN_RB_ENABLE, tmp);
+ fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);
+
return 0;
}
@@ -1545,81 +1542,79 @@ static void vcn_v4_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)
*
* Stop VCN block
*/
-static int vcn_v4_0_stop(struct amdgpu_device *adev)
+static int vcn_v4_0_stop(struct amdgpu_device *adev, unsigned int inst)
{
volatile struct amdgpu_vcn4_fw_shared *fw_shared;
uint32_t tmp;
- int i, r = 0;
+ int r = 0;
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ goto done;
- fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
- fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF;
+ fw_shared = adev->vcn.inst[inst].fw_shared.cpu_addr;
+ fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF;
- if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
- vcn_v4_0_stop_dpg_mode(adev, i);
- continue;
- }
-
- /* wait for vcn idle */
- r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 0x7);
- if (r)
- return r;
-
- tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
- UVD_LMI_STATUS__READ_CLEAN_MASK |
- UVD_LMI_STATUS__WRITE_CLEAN_MASK |
- UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
- r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp);
- if (r)
- return r;
-
- /* disable LMI UMC channel */
- tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL2);
- tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
- WREG32_SOC15(VCN, i, regUVD_LMI_CTRL2, tmp);
- tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |
- UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
- r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp);
- if (r)
- return r;
-
- /* block VCPU register access */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL),
- UVD_RB_ARB_CTRL__VCPU_DIS_MASK,
- ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
-
- /* reset VCPU */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
- UVD_VCPU_CNTL__BLK_RST_MASK,
- ~UVD_VCPU_CNTL__BLK_RST_MASK);
-
- /* disable VCPU clock */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,
- ~(UVD_VCPU_CNTL__CLK_EN_MASK));
-
- /* apply soft reset */
- tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);
- tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
- WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);
- tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);
- tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
- WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);
+ if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
+ vcn_v4_0_stop_dpg_mode(adev, inst);
+ goto done;
+ }
- /* clear status */
- WREG32_SOC15(VCN, i, regUVD_STATUS, 0);
+ /* wait for vcn idle */
+ r = SOC15_WAIT_ON_RREG(VCN, inst, regUVD_STATUS, UVD_STATUS__IDLE, 0x7);
+ if (r)
+ return r;
- /* apply HW clock gating */
- vcn_v4_0_enable_clock_gating(adev, i);
+ tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
+ UVD_LMI_STATUS__READ_CLEAN_MASK |
+ UVD_LMI_STATUS__WRITE_CLEAN_MASK |
+ UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
+ r = SOC15_WAIT_ON_RREG(VCN, inst, regUVD_LMI_STATUS, tmp, tmp);
+ if (r)
+ return r;
- /* enable VCN power gating */
- vcn_v4_0_enable_static_power_gating(adev, i);
- }
+ /* disable LMI UMC channel */
+ tmp = RREG32_SOC15(VCN, inst, regUVD_LMI_CTRL2);
+ tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
+ WREG32_SOC15(VCN, inst, regUVD_LMI_CTRL2, tmp);
+ tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |
+ UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
+ r = SOC15_WAIT_ON_RREG(VCN, inst, regUVD_LMI_STATUS, tmp, tmp);
+ if (r)
+ return r;
+ /* block VCPU register access */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_RB_ARB_CTRL),
+ UVD_RB_ARB_CTRL__VCPU_DIS_MASK,
+ ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
+
+ /* reset VCPU */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_VCPU_CNTL),
+ UVD_VCPU_CNTL__BLK_RST_MASK,
+ ~UVD_VCPU_CNTL__BLK_RST_MASK);
+
+ /* disable VCPU clock */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_VCPU_CNTL), 0,
+ ~(UVD_VCPU_CNTL__CLK_EN_MASK));
+
+ /* apply soft reset */
+ tmp = RREG32_SOC15(VCN, inst, regUVD_SOFT_RESET);
+ tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
+ WREG32_SOC15(VCN, inst, regUVD_SOFT_RESET, tmp);
+ tmp = RREG32_SOC15(VCN, inst, regUVD_SOFT_RESET);
+ tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
+ WREG32_SOC15(VCN, inst, regUVD_SOFT_RESET, tmp);
+
+ /* clear status */
+ WREG32_SOC15(VCN, inst, regUVD_STATUS, 0);
+
+ /* apply HW clock gating */
+ vcn_v4_0_enable_clock_gating(adev, inst);
+
+ /* enable VCN power gating */
+ vcn_v4_0_enable_static_power_gating(adev, inst);
+done:
if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_uvd(adev, false);
+ amdgpu_dpm_enable_vcn(adev, false, inst);
return 0;
}
@@ -2041,29 +2036,28 @@ static int vcn_v4_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
struct amdgpu_device *adev = ip_block->adev;
+ int i = ip_block->instance;
int ret;
- for (int i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- /* for SRIOV, guest should not control VCN Power-gating
- * MMSCH FW should control Power-gating and clock-gating
- * guest should avoid touching CGC and PG
- */
- if (amdgpu_sriov_vf(adev)) {
- adev->vcn.cur_state[i] = AMD_PG_STATE_UNGATE;
- return 0;
- }
+ /* for SRIOV, guest should not control VCN Power-gating
+ * MMSCH FW should control Power-gating and clock-gating
+ * guest should avoid touching CGC and PG
+ */
+ if (amdgpu_sriov_vf(adev)) {
+ adev->vcn.cur_state[i] = AMD_PG_STATE_UNGATE;
+ return 0;
+ }
- if (state == adev->vcn.cur_state[i])
- return 0;
+ if (state == adev->vcn.cur_state[i])
+ return 0;
- if (state == AMD_PG_STATE_GATE)
- ret = vcn_v4_0_stop(adev);
- else
- ret = vcn_v4_0_start(adev);
+ if (state == AMD_PG_STATE_GATE)
+ ret = vcn_v4_0_stop(adev, i);
+ else
+ ret = vcn_v4_0_start(adev, i);
- if (!ret)
- adev->vcn.cur_state[i] = state;
- }
+ if (!ret)
+ adev->vcn.cur_state[i] = state;
return ret;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH 15/18] drm/amdgpu: power vcn 4_0_3 by instance
2024-10-02 4:36 [PATCH 00/18] Separating vcn power management by instance boyuan.zhang
` (13 preceding siblings ...)
2024-10-02 4:36 ` [PATCH 14/18] drm/amdgpu: power vcn 4_0 " boyuan.zhang
@ 2024-10-02 4:36 ` boyuan.zhang
2024-10-02 4:36 ` [PATCH 16/18] drm/amdgpu: power vcn 4_0_5 " boyuan.zhang
` (2 subsequent siblings)
17 siblings, 0 replies; 29+ messages in thread
From: boyuan.zhang @ 2024-10-02 4:36 UTC (permalink / raw)
To: amd-gfx, leo.liu, christian.koenig, alexander.deucher,
sunil.khatri
Cc: Boyuan Zhang
From: Boyuan Zhang <boyuan.zhang@amd.com>
For vcn 4_0_3, add ip_block for each vcn instance during discovery stage.
And only powering on/off one of the vcn instance using the
instance value stored in ip_block, instead of powering on/off all
vcn instances. Modify the existing functions to use the instance value
in ip_block, and remove the original for loop for all vcn instances.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 3 +-
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 487 +++++++++---------
2 files changed, 242 insertions(+), 248 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index 8d8107241a5a..909a97b502d5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -2351,7 +2351,8 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &jpeg_v4_0_ip_block);
break;
case IP_VERSION(4, 0, 3):
- amdgpu_device_ip_block_add(adev, &vcn_v4_0_3_ip_block);
+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i)
+ amdgpu_device_ip_block_add_instance(adev, &vcn_v4_0_3_ip_block, i);
amdgpu_device_ip_block_add(adev, &jpeg_v4_0_3_ip_block);
break;
case IP_VERSION(4, 0, 5):
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
index 84939e92cd3a..aee8e1ee37ff 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
@@ -127,7 +127,7 @@ static int vcn_v4_0_3_sw_init(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
struct amdgpu_ring *ring;
- int i, r, vcn_inst;
+ int inst = ip_block->instance, r, vcn_inst;
uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3);
uint32_t *ptr;
@@ -147,38 +147,36 @@ static int vcn_v4_0_3_sw_init(struct amdgpu_ip_block *ip_block)
if (r)
return r;
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
- volatile struct amdgpu_vcn4_fw_shared *fw_shared;
+ volatile struct amdgpu_vcn4_fw_shared *fw_shared;
- vcn_inst = GET_INST(VCN, i);
+ vcn_inst = GET_INST(VCN, inst);
- ring = &adev->vcn.inst[i].ring_enc[0];
- ring->use_doorbell = true;
-
- if (!amdgpu_sriov_vf(adev))
- ring->doorbell_index =
- (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
- 9 * vcn_inst;
- else
- ring->doorbell_index =
- (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
- 32 * vcn_inst;
-
- ring->vm_hub = AMDGPU_MMHUB0(adev->vcn.inst[i].aid_id);
- sprintf(ring->name, "vcn_unified_%d", adev->vcn.inst[i].aid_id);
- r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0,
- AMDGPU_RING_PRIO_DEFAULT,
- &adev->vcn.inst[i].sched_score);
- if (r)
- return r;
+ ring = &adev->vcn.inst[inst].ring_enc[0];
+ ring->use_doorbell = true;
- fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
- fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE);
- fw_shared->sq.is_enabled = true;
+ if (!amdgpu_sriov_vf(adev))
+ ring->doorbell_index =
+ (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
+ 9 * vcn_inst;
+ else
+ ring->doorbell_index =
+ (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
+ 32 * vcn_inst;
+
+ ring->vm_hub = AMDGPU_MMHUB0(adev->vcn.inst[inst].aid_id);
+ sprintf(ring->name, "vcn_unified_%d", adev->vcn.inst[inst].aid_id);
+ r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0,
+ AMDGPU_RING_PRIO_DEFAULT,
+ &adev->vcn.inst[inst].sched_score);
+ if (r)
+ return r;
- if (amdgpu_vcnfw_log)
- amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]);
- }
+ fw_shared = adev->vcn.inst[inst].fw_shared.cpu_addr;
+ fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE);
+ fw_shared->sq.is_enabled = true;
+
+ if (amdgpu_vcnfw_log)
+ amdgpu_vcn_fwlog_init(&adev->vcn.inst[inst]);
if (amdgpu_sriov_vf(adev)) {
r = amdgpu_virt_alloc_mm_table(adev);
@@ -1091,172 +1089,170 @@ static int vcn_v4_0_3_start_sriov(struct amdgpu_device *adev)
*
* Start VCN block
*/
-static int vcn_v4_0_3_start(struct amdgpu_device *adev)
+static int vcn_v4_0_3_start(struct amdgpu_device *adev, unsigned int inst)
{
volatile struct amdgpu_vcn4_fw_shared *fw_shared;
struct amdgpu_ring *ring;
- int i, j, k, r, vcn_inst;
+ int j, k, r, vcn_inst;
uint32_t tmp;
if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_uvd(adev, true);
+ amdgpu_dpm_enable_vcn(adev, true, inst);
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
- r = vcn_v4_0_3_start_dpg_mode(adev, i, adev->vcn.indirect_sram);
- continue;
- }
+ if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
+ r = vcn_v4_0_3_start_dpg_mode(adev, inst, adev->vcn.indirect_sram);
+ return r;
+ }
- vcn_inst = GET_INST(VCN, i);
- /* set VCN status busy */
- tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS) |
- UVD_STATUS__UVD_BUSY;
- WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, tmp);
-
- /*SW clock gating */
- vcn_v4_0_3_disable_clock_gating(adev, i);
-
- /* enable VCPU clock */
- WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL),
- UVD_VCPU_CNTL__CLK_EN_MASK,
- ~UVD_VCPU_CNTL__CLK_EN_MASK);
-
- /* disable master interrupt */
- WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN), 0,
- ~UVD_MASTINT_EN__VCPU_EN_MASK);
-
- /* enable LMI MC and UMC channels */
- WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_LMI_CTRL2), 0,
- ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
-
- tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET);
- tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
- tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
- WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp);
-
- /* setup regUVD_LMI_CTRL */
- tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL);
- WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL,
- tmp | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
- UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
- UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
- UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
-
- /* setup regUVD_MPC_CNTL */
- tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_MPC_CNTL);
- tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
- tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
- WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_CNTL, tmp);
-
- /* setup UVD_MPC_SET_MUXA0 */
- WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUXA0,
- ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
- (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
- (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
- (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
-
- /* setup UVD_MPC_SET_MUXB0 */
- WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUXB0,
- ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
- (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
- (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
- (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
-
- /* setup UVD_MPC_SET_MUX */
- WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUX,
- ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
- (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
- (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
-
- vcn_v4_0_3_mc_resume(adev, i);
-
- /* VCN global tiling registers */
- WREG32_SOC15(VCN, vcn_inst, regUVD_GFX8_ADDR_CONFIG,
- adev->gfx.config.gb_addr_config);
- WREG32_SOC15(VCN, vcn_inst, regUVD_GFX10_ADDR_CONFIG,
- adev->gfx.config.gb_addr_config);
-
- /* unblock VCPU register access */
- WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL), 0,
- ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
-
- /* release VCPU reset to boot */
- WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0,
- ~UVD_VCPU_CNTL__BLK_RST_MASK);
+ vcn_inst = GET_INST(VCN, inst);
+ /* set VCN status busy */
+ tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS) |
+ UVD_STATUS__UVD_BUSY;
+ WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, tmp);
- for (j = 0; j < 10; ++j) {
- uint32_t status;
+ /*SW clock gating */
+ vcn_v4_0_3_disable_clock_gating(adev, inst);
- for (k = 0; k < 100; ++k) {
- status = RREG32_SOC15(VCN, vcn_inst,
- regUVD_STATUS);
- if (status & 2)
- break;
- mdelay(10);
- }
- r = 0;
- if (status & 2)
- break;
+ /* enable VCPU clock */
+ WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL),
+ UVD_VCPU_CNTL__CLK_EN_MASK,
+ ~UVD_VCPU_CNTL__CLK_EN_MASK);
- DRM_DEV_ERROR(adev->dev,
- "VCN decode not responding, trying to reset the VCPU!!!\n");
- WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst,
- regUVD_VCPU_CNTL),
- UVD_VCPU_CNTL__BLK_RST_MASK,
- ~UVD_VCPU_CNTL__BLK_RST_MASK);
- mdelay(10);
- WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst,
- regUVD_VCPU_CNTL),
- 0, ~UVD_VCPU_CNTL__BLK_RST_MASK);
+ /* disable master interrupt */
+ WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN), 0,
+ ~UVD_MASTINT_EN__VCPU_EN_MASK);
+
+ /* enable LMI MC and UMC channels */
+ WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_LMI_CTRL2), 0,
+ ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
+
+ tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET);
+ tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
+ tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
+ WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp);
+
+ /* setup regUVD_LMI_CTRL */
+ tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL);
+ WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL,
+ tmp | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
+ UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
+ UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
+ UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
+
+ /* setup regUVD_MPC_CNTL */
+ tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_MPC_CNTL);
+ tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
+ tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
+ WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_CNTL, tmp);
+
+ /* setup UVD_MPC_SET_MUXA0 */
+ WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUXA0,
+ ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
+ (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
+ (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
+ (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
+
+ /* setup UVD_MPC_SET_MUXB0 */
+ WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUXB0,
+ ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
+ (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
+ (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
+ (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
+
+ /* setup UVD_MPC_SET_MUX */
+ WREG32_SOC15(VCN, vcn_inst, regUVD_MPC_SET_MUX,
+ ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
+ (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
+ (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
+
+ vcn_v4_0_3_mc_resume(adev, inst);
+
+ /* VCN global tiling registers */
+ WREG32_SOC15(VCN, vcn_inst, regUVD_GFX8_ADDR_CONFIG,
+ adev->gfx.config.gb_addr_config);
+ WREG32_SOC15(VCN, vcn_inst, regUVD_GFX10_ADDR_CONFIG,
+ adev->gfx.config.gb_addr_config);
+
+ /* unblock VCPU register access */
+ WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL), 0,
+ ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
+
+ /* release VCPU reset to boot */
+ WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0,
+ ~UVD_VCPU_CNTL__BLK_RST_MASK);
+ for (j = 0; j < 10; ++j) {
+ uint32_t status;
+
+ for (k = 0; k < 100; ++k) {
+ status = RREG32_SOC15(VCN, vcn_inst,
+ regUVD_STATUS);
+ if (status & 2)
+ break;
mdelay(10);
- r = -1;
}
+ r = 0;
+ if (status & 2)
+ break;
- if (r) {
- DRM_DEV_ERROR(adev->dev, "VCN decode not responding, giving up!!!\n");
- return r;
- }
+ DRM_DEV_ERROR(adev->dev,
+ "VCN decode not responding, trying to reset the VCPU!!!\n");
+ WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst,
+ regUVD_VCPU_CNTL),
+ UVD_VCPU_CNTL__BLK_RST_MASK,
+ ~UVD_VCPU_CNTL__BLK_RST_MASK);
+ mdelay(10);
+ WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst,
+ regUVD_VCPU_CNTL),
+ 0, ~UVD_VCPU_CNTL__BLK_RST_MASK);
- /* enable master interrupt */
- WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN),
- UVD_MASTINT_EN__VCPU_EN_MASK,
- ~UVD_MASTINT_EN__VCPU_EN_MASK);
+ mdelay(10);
+ r = -1;
+ }
- /* clear the busy bit of VCN_STATUS */
- WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_STATUS), 0,
- ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
+ if (r) {
+ DRM_DEV_ERROR(adev->dev, "VCN decode not responding, giving up!!!\n");
+ return r;
+ }
- ring = &adev->vcn.inst[i].ring_enc[0];
- fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
+ /* enable master interrupt */
+ WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN),
+ UVD_MASTINT_EN__VCPU_EN_MASK,
+ ~UVD_MASTINT_EN__VCPU_EN_MASK);
- /* program the RB_BASE for ring buffer */
- WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO,
- lower_32_bits(ring->gpu_addr));
- WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_HI,
- upper_32_bits(ring->gpu_addr));
+ /* clear the busy bit of VCN_STATUS */
+ WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_STATUS), 0,
+ ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
- WREG32_SOC15(VCN, vcn_inst, regUVD_RB_SIZE,
- ring->ring_size / sizeof(uint32_t));
+ ring = &adev->vcn.inst[inst].ring_enc[0];
+ fw_shared = adev->vcn.inst[inst].fw_shared.cpu_addr;
- /* resetting ring, fw should not check RB ring */
- tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);
- tmp &= ~(VCN_RB_ENABLE__RB_EN_MASK);
- WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp);
+ /* program the RB_BASE for ring buffer */
+ WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO,
+ lower_32_bits(ring->gpu_addr));
+ WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_HI,
+ upper_32_bits(ring->gpu_addr));
- /* Initialize the ring buffer's read and write pointers */
- WREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR, 0);
- WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0);
+ WREG32_SOC15(VCN, vcn_inst, regUVD_RB_SIZE,
+ ring->ring_size / sizeof(uint32_t));
- tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);
- tmp |= VCN_RB_ENABLE__RB_EN_MASK;
- WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp);
+ /* resetting ring, fw should not check RB ring */
+ tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);
+ tmp &= ~(VCN_RB_ENABLE__RB_EN_MASK);
+ WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp);
- ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR);
- fw_shared->sq.queue_mode &=
- cpu_to_le32(~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF));
+ /* Initialize the ring buffer's read and write pointers */
+ WREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR, 0);
+ WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0);
+
+ tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE);
+ tmp |= VCN_RB_ENABLE__RB_EN_MASK;
+ WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp);
+
+ ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR);
+ fw_shared->sq.queue_mode &=
+ cpu_to_le32(~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF));
- }
return 0;
}
@@ -1299,81 +1295,79 @@ static int vcn_v4_0_3_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)
*
* Stop VCN block
*/
-static int vcn_v4_0_3_stop(struct amdgpu_device *adev)
+static int vcn_v4_0_3_stop(struct amdgpu_device *adev, unsigned int inst)
{
volatile struct amdgpu_vcn4_fw_shared *fw_shared;
- int i, r = 0, vcn_inst;
+ int r = 0, vcn_inst;
uint32_t tmp;
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- vcn_inst = GET_INST(VCN, i);
+ vcn_inst = GET_INST(VCN, inst);
- fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
- fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF;
+ fw_shared = adev->vcn.inst[inst].fw_shared.cpu_addr;
+ fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF;
- if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
- vcn_v4_0_3_stop_dpg_mode(adev, i);
- continue;
- }
+ if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
+ vcn_v4_0_3_stop_dpg_mode(adev, inst);
+ goto Done;
+ }
- /* wait for vcn idle */
- r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_STATUS,
- UVD_STATUS__IDLE, 0x7);
- if (r)
- goto Done;
-
- tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
- UVD_LMI_STATUS__READ_CLEAN_MASK |
- UVD_LMI_STATUS__WRITE_CLEAN_MASK |
- UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
- r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp,
- tmp);
- if (r)
- goto Done;
-
- /* stall UMC channel */
- tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2);
- tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
- WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2, tmp);
- tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |
- UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
- r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp,
- tmp);
- if (r)
- goto Done;
+ /* wait for vcn idle */
+ r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_STATUS,
+ UVD_STATUS__IDLE, 0x7);
+ if (r)
+ goto Done;
+
+ tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
+ UVD_LMI_STATUS__READ_CLEAN_MASK |
+ UVD_LMI_STATUS__WRITE_CLEAN_MASK |
+ UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
+ r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp,
+ tmp);
+ if (r)
+ goto Done;
+
+ /* stall UMC channel */
+ tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2);
+ tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
+ WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2, tmp);
+ tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |
+ UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
+ r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp,
+ tmp);
+ if (r)
+ goto Done;
- /* Unblock VCPU Register access */
- WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL),
- UVD_RB_ARB_CTRL__VCPU_DIS_MASK,
- ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
+ /* Unblock VCPU Register access */
+ WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL),
+ UVD_RB_ARB_CTRL__VCPU_DIS_MASK,
+ ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
- /* release VCPU reset to boot */
- WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL),
- UVD_VCPU_CNTL__BLK_RST_MASK,
- ~UVD_VCPU_CNTL__BLK_RST_MASK);
+ /* release VCPU reset to boot */
+ WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL),
+ UVD_VCPU_CNTL__BLK_RST_MASK,
+ ~UVD_VCPU_CNTL__BLK_RST_MASK);
- /* disable VCPU clock */
- WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0,
- ~(UVD_VCPU_CNTL__CLK_EN_MASK));
+ /* disable VCPU clock */
+ WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0,
+ ~(UVD_VCPU_CNTL__CLK_EN_MASK));
- /* reset LMI UMC/LMI/VCPU */
- tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET);
- tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
- WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp);
+ /* reset LMI UMC/LMI/VCPU */
+ tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET);
+ tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
+ WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp);
- tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET);
- tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
- WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp);
+ tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET);
+ tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
+ WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp);
- /* clear VCN status */
- WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, 0);
+ /* clear VCN status */
+ WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, 0);
- /* apply HW clock gating */
- vcn_v4_0_3_enable_clock_gating(adev, i);
- }
+ /* apply HW clock gating */
+ vcn_v4_0_3_enable_clock_gating(adev, inst);
Done:
if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_uvd(adev, false);
+ amdgpu_dpm_enable_vcn(adev, false, inst);
return 0;
}
@@ -1630,29 +1624,28 @@ static int vcn_v4_0_3_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
struct amdgpu_device *adev = ip_block->adev;
+ int i = ip_block->instance;
int ret;
- for (int i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- /* for SRIOV, guest should not control VCN Power-gating
- * MMSCH FW should control Power-gating and clock-gating
- * guest should avoid touching CGC and PG
- */
- if (amdgpu_sriov_vf(adev)) {
- adev->vcn.cur_state[i] = AMD_PG_STATE_UNGATE;
- return 0;
- }
+ /* for SRIOV, guest should not control VCN Power-gating
+ * MMSCH FW should control Power-gating and clock-gating
+ * guest should avoid touching CGC and PG
+ */
+ if (amdgpu_sriov_vf(adev)) {
+ adev->vcn.cur_state[i] = AMD_PG_STATE_UNGATE;
+ return 0;
+ }
- if (state == adev->vcn.cur_state[i])
- return 0;
+ if (state == adev->vcn.cur_state[i])
+ return 0;
- if (state == AMD_PG_STATE_GATE)
- ret = vcn_v4_0_3_stop(adev);
- else
- ret = vcn_v4_0_3_start(adev);
+ if (state == AMD_PG_STATE_GATE)
+ ret = vcn_v4_0_3_stop(adev, i);
+ else
+ ret = vcn_v4_0_3_start(adev, i);
- if (!ret)
- adev->vcn.cur_state[i] = state;
- }
+ if (!ret)
+ adev->vcn.cur_state[i] = state;
return ret;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH 16/18] drm/amdgpu: power vcn 4_0_5 by instance
2024-10-02 4:36 [PATCH 00/18] Separating vcn power management by instance boyuan.zhang
` (14 preceding siblings ...)
2024-10-02 4:36 ` [PATCH 15/18] drm/amdgpu: power vcn 4_0_3 " boyuan.zhang
@ 2024-10-02 4:36 ` boyuan.zhang
2024-10-02 4:36 ` [PATCH 17/18] drm/amdgpu: power vcn 5_0_0 " boyuan.zhang
2024-10-02 4:36 ` [PATCH 18/18] drm/amdgpu: set powergating state by vcn instance boyuan.zhang
17 siblings, 0 replies; 29+ messages in thread
From: boyuan.zhang @ 2024-10-02 4:36 UTC (permalink / raw)
To: amd-gfx, leo.liu, christian.koenig, alexander.deucher,
sunil.khatri
Cc: Boyuan Zhang
From: Boyuan Zhang <boyuan.zhang@amd.com>
For vcn 4_0_5, add ip_block for each vcn instance during discovery stage.
And only powering on/off one of the vcn instance using the
instance value stored in ip_block, instead of powering on/off all
vcn instances. Modify the existing functions to use the instance value
in ip_block, and remove the original for loop for all vcn instances.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 3 +-
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 531 +++++++++---------
2 files changed, 264 insertions(+), 270 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index 909a97b502d5..2f177bd39ed8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -2357,7 +2357,8 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev)
break;
case IP_VERSION(4, 0, 5):
case IP_VERSION(4, 0, 6):
- amdgpu_device_ip_block_add(adev, &vcn_v4_0_5_ip_block);
+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i)
+ amdgpu_device_ip_block_add_instance(adev, &vcn_v4_0_5_ip_block, i);
amdgpu_device_ip_block_add(adev, &jpeg_v4_0_5_ip_block);
break;
case IP_VERSION(5, 0, 0):
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
index a3bb42893803..1eae0a84e908 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
@@ -132,7 +132,7 @@ static int vcn_v4_0_5_sw_init(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_ring *ring;
struct amdgpu_device *adev = ip_block->adev;
- int i, r;
+ int inst = ip_block->instance, r;
uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_5);
uint32_t *ptr;
@@ -146,57 +146,55 @@ static int vcn_v4_0_5_sw_init(struct amdgpu_ip_block *ip_block)
if (r)
return r;
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
- volatile struct amdgpu_vcn4_fw_shared *fw_shared;
+ volatile struct amdgpu_vcn4_fw_shared *fw_shared;
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ goto done;
- atomic_set(&adev->vcn.inst[i].sched_score, 0);
+ atomic_set(&adev->vcn.inst[inst].sched_score, 0);
- /* VCN UNIFIED TRAP */
- r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
- VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq);
- if (r)
- return r;
+ /* VCN UNIFIED TRAP */
+ r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[inst],
+ VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[inst].irq);
+ if (r)
+ return r;
- /* VCN POISON TRAP */
- r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
- VCN_4_0__SRCID_UVD_POISON, &adev->vcn.inst[i].irq);
- if (r)
- return r;
+ /* VCN POISON TRAP */
+ r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[inst],
+ VCN_4_0__SRCID_UVD_POISON, &adev->vcn.inst[inst].irq);
+ if (r)
+ return r;
- ring = &adev->vcn.inst[i].ring_enc[0];
- ring->use_doorbell = true;
- if (amdgpu_sriov_vf(adev))
- ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
- i * (adev->vcn.num_enc_rings + 1) + 1;
- else
- ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
- 2 + 8 * i;
- ring->vm_hub = AMDGPU_MMHUB0(0);
- sprintf(ring->name, "vcn_unified_%d", i);
-
- r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,
- AMDGPU_RING_PRIO_0, &adev->vcn.inst[i].sched_score);
- if (r)
- return r;
+ ring = &adev->vcn.inst[inst].ring_enc[0];
+ ring->use_doorbell = true;
+ if (amdgpu_sriov_vf(adev))
+ ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
+ inst * (adev->vcn.num_enc_rings + 1) + 1;
+ else
+ ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
+ 2 + 8 * inst;
+ ring->vm_hub = AMDGPU_MMHUB0(0);
+ sprintf(ring->name, "vcn_unified_%d", inst);
- fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
- fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE);
- fw_shared->sq.is_enabled = 1;
+ r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[inst].irq, 0,
+ AMDGPU_RING_PRIO_0, &adev->vcn.inst[inst].sched_score);
+ if (r)
+ return r;
- fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SMU_DPM_INTERFACE_FLAG);
- fw_shared->smu_dpm_interface.smu_interface_type = (adev->flags & AMD_IS_APU) ?
- AMDGPU_VCN_SMU_DPM_INTERFACE_APU : AMDGPU_VCN_SMU_DPM_INTERFACE_DGPU;
+ fw_shared = adev->vcn.inst[inst].fw_shared.cpu_addr;
+ fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE);
+ fw_shared->sq.is_enabled = 1;
- if (amdgpu_sriov_vf(adev))
- fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG);
+ fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SMU_DPM_INTERFACE_FLAG);
+ fw_shared->smu_dpm_interface.smu_interface_type = (adev->flags & AMD_IS_APU) ?
+ AMDGPU_VCN_SMU_DPM_INTERFACE_APU : AMDGPU_VCN_SMU_DPM_INTERFACE_DGPU;
- if (amdgpu_vcnfw_log)
- amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]);
- }
+ if (amdgpu_sriov_vf(adev))
+ fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG);
+ if (amdgpu_vcnfw_log)
+ amdgpu_vcn_fwlog_init(&adev->vcn.inst[inst]);
+done:
if (amdgpu_sriov_vf(adev)) {
r = amdgpu_virt_alloc_mm_table(adev);
if (r)
@@ -997,178 +995,176 @@ static int vcn_v4_0_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, b
*
* Start VCN block
*/
-static int vcn_v4_0_5_start(struct amdgpu_device *adev)
+static int vcn_v4_0_5_start(struct amdgpu_device *adev, unsigned int inst)
{
volatile struct amdgpu_vcn4_fw_shared *fw_shared;
struct amdgpu_ring *ring;
uint32_t tmp;
- int i, j, k, r;
+ int j, k, r;
if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_uvd(adev, true);
+ amdgpu_dpm_enable_vcn(adev, true, 1);
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return 0;
- fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
+ fw_shared = adev->vcn.inst[inst].fw_shared.cpu_addr;
- if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
- r = vcn_v4_0_5_start_dpg_mode(adev, i, adev->vcn.indirect_sram);
- continue;
- }
+ if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
+ r = vcn_v4_0_5_start_dpg_mode(adev, inst, adev->vcn.indirect_sram);
+ return r;
+ }
- /* disable VCN power gating */
- vcn_v4_0_5_disable_static_power_gating(adev, i);
-
- /* set VCN status busy */
- tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY;
- WREG32_SOC15(VCN, i, regUVD_STATUS, tmp);
-
- /*SW clock gating */
- vcn_v4_0_5_disable_clock_gating(adev, i);
-
- /* enable VCPU clock */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
- UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
-
- /* disable master interrupt */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 0,
- ~UVD_MASTINT_EN__VCPU_EN_MASK);
-
- /* enable LMI MC and UMC channels */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_LMI_CTRL2), 0,
- ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
-
- tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);
- tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
- tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
- WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);
-
- /* setup regUVD_LMI_CTRL */
- tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL);
- WREG32_SOC15(VCN, i, regUVD_LMI_CTRL, tmp |
- UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
- UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
- UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
- UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
-
- /* setup regUVD_MPC_CNTL */
- tmp = RREG32_SOC15(VCN, i, regUVD_MPC_CNTL);
- tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
- tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
- WREG32_SOC15(VCN, i, regUVD_MPC_CNTL, tmp);
-
- /* setup UVD_MPC_SET_MUXA0 */
- WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXA0,
- ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
- (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
- (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
- (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
-
- /* setup UVD_MPC_SET_MUXB0 */
- WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXB0,
- ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
- (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
- (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
- (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
-
- /* setup UVD_MPC_SET_MUX */
- WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUX,
- ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
- (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
- (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
-
- vcn_v4_0_5_mc_resume(adev, i);
-
- /* VCN global tiling registers */
- WREG32_SOC15(VCN, i, regUVD_GFX10_ADDR_CONFIG,
- adev->gfx.config.gb_addr_config);
-
- /* unblock VCPU register access */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 0,
- ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
-
- /* release VCPU reset to boot */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,
- ~UVD_VCPU_CNTL__BLK_RST_MASK);
-
- for (j = 0; j < 10; ++j) {
- uint32_t status;
-
- for (k = 0; k < 100; ++k) {
- status = RREG32_SOC15(VCN, i, regUVD_STATUS);
- if (status & 2)
- break;
- mdelay(10);
- if (amdgpu_emu_mode == 1)
- msleep(1);
- }
+ /* disable VCN power gating */
+ vcn_v4_0_5_disable_static_power_gating(adev, inst);
+
+ /* set VCN status busy */
+ tmp = RREG32_SOC15(VCN, inst, regUVD_STATUS) | UVD_STATUS__UVD_BUSY;
+ WREG32_SOC15(VCN, inst, regUVD_STATUS, tmp);
+
+ /*SW clock gating */
+ vcn_v4_0_5_disable_clock_gating(adev, inst);
+
+ /* enable VCPU clock */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_VCPU_CNTL),
+ UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
+
+ /* disable master interrupt */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_MASTINT_EN), 0,
+ ~UVD_MASTINT_EN__VCPU_EN_MASK);
+
+ /* enable LMI MC and UMC channels */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_LMI_CTRL2), 0,
+ ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
+
+ tmp = RREG32_SOC15(VCN, inst, regUVD_SOFT_RESET);
+ tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
+ tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
+ WREG32_SOC15(VCN, inst, regUVD_SOFT_RESET, tmp);
+
+ /* setup regUVD_LMI_CTRL */
+ tmp = RREG32_SOC15(VCN, inst, regUVD_LMI_CTRL);
+ WREG32_SOC15(VCN, inst, regUVD_LMI_CTRL, tmp |
+ UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
+ UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
+ UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
+ UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
+
+ /* setup regUVD_MPC_CNTL */
+ tmp = RREG32_SOC15(VCN, inst, regUVD_MPC_CNTL);
+ tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
+ tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
+ WREG32_SOC15(VCN, inst, regUVD_MPC_CNTL, tmp);
+
+ /* setup UVD_MPC_SET_MUXA0 */
+ WREG32_SOC15(VCN, inst, regUVD_MPC_SET_MUXA0,
+ ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
+ (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
+ (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
+ (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
+
+ /* setup UVD_MPC_SET_MUXB0 */
+ WREG32_SOC15(VCN, inst, regUVD_MPC_SET_MUXB0,
+ ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
+ (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
+ (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
+ (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
+
+ /* setup UVD_MPC_SET_MUX */
+ WREG32_SOC15(VCN, inst, regUVD_MPC_SET_MUX,
+ ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
+ (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
+ (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
+
+ vcn_v4_0_5_mc_resume(adev, inst);
- if (amdgpu_emu_mode == 1) {
- r = -1;
- if (status & 2) {
- r = 0;
- break;
- }
- } else {
+ /* VCN global tiling registers */
+ WREG32_SOC15(VCN, inst, regUVD_GFX10_ADDR_CONFIG,
+ adev->gfx.config.gb_addr_config);
+
+ /* unblock VCPU register access */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_RB_ARB_CTRL), 0,
+ ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
+
+ /* release VCPU reset to boot */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_VCPU_CNTL), 0,
+ ~UVD_VCPU_CNTL__BLK_RST_MASK);
+
+ for (j = 0; j < 10; ++j) {
+ uint32_t status;
+
+ for (k = 0; k < 100; ++k) {
+ status = RREG32_SOC15(VCN, inst, regUVD_STATUS);
+ if (status & 2)
+ break;
+ mdelay(10);
+ if (amdgpu_emu_mode == 1)
+ msleep(1);
+ }
+
+ if (amdgpu_emu_mode == 1) {
+ r = -1;
+ if (status & 2) {
r = 0;
- if (status & 2)
- break;
-
- dev_err(adev->dev,
- "VCN[%d] is not responding, trying to reset VCPU!!!\n", i);
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
- UVD_VCPU_CNTL__BLK_RST_MASK,
- ~UVD_VCPU_CNTL__BLK_RST_MASK);
- mdelay(10);
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,
+ break;
+ }
+ } else {
+ r = 0;
+ if (status & 2)
+ break;
+
+ dev_err(adev->dev,
+ "VCN[%d] is not responding, trying to reset VCPU!!!\n", inst);
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_VCPU_CNTL),
+ UVD_VCPU_CNTL__BLK_RST_MASK,
~UVD_VCPU_CNTL__BLK_RST_MASK);
+ mdelay(10);
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_VCPU_CNTL), 0,
+ ~UVD_VCPU_CNTL__BLK_RST_MASK);
- mdelay(10);
- r = -1;
- }
+ mdelay(10);
+ r = -1;
}
+ }
- if (r) {
- dev_err(adev->dev, "VCN[%d] is not responding, giving up!!!\n", i);
- return r;
- }
+ if (r) {
+ dev_err(adev->dev, "VCN[%d] is not responding, giving up!!!\n", inst);
+ return r;
+ }
+
+ /* enable master interrupt */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_MASTINT_EN),
+ UVD_MASTINT_EN__VCPU_EN_MASK,
+ ~UVD_MASTINT_EN__VCPU_EN_MASK);
+
+ /* clear the busy bit of VCN_STATUS */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_STATUS), 0,
+ ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
- /* enable master interrupt */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN),
- UVD_MASTINT_EN__VCPU_EN_MASK,
- ~UVD_MASTINT_EN__VCPU_EN_MASK);
+ ring = &adev->vcn.inst[inst].ring_enc[0];
+ WREG32_SOC15(VCN, inst, regVCN_RB1_DB_CTRL,
+ ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT |
+ VCN_RB1_DB_CTRL__EN_MASK);
- /* clear the busy bit of VCN_STATUS */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_STATUS), 0,
- ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
+ WREG32_SOC15(VCN, inst, regUVD_RB_BASE_LO, ring->gpu_addr);
+ WREG32_SOC15(VCN, inst, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
+ WREG32_SOC15(VCN, inst, regUVD_RB_SIZE, ring->ring_size / 4);
- ring = &adev->vcn.inst[i].ring_enc[0];
- WREG32_SOC15(VCN, i, regVCN_RB1_DB_CTRL,
- ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT |
- VCN_RB1_DB_CTRL__EN_MASK);
-
- WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring->gpu_addr);
- WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
- WREG32_SOC15(VCN, i, regUVD_RB_SIZE, ring->ring_size / 4);
-
- tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);
- tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK);
- WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);
- fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET;
- WREG32_SOC15(VCN, i, regUVD_RB_RPTR, 0);
- WREG32_SOC15(VCN, i, regUVD_RB_WPTR, 0);
-
- tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR);
- WREG32_SOC15(VCN, i, regUVD_RB_WPTR, tmp);
- ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR);
-
- tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);
- tmp |= VCN_RB_ENABLE__RB1_EN_MASK;
- WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);
- fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);
- }
+ tmp = RREG32_SOC15(VCN, inst, regVCN_RB_ENABLE);
+ tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK);
+ WREG32_SOC15(VCN, inst, regVCN_RB_ENABLE, tmp);
+ fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET;
+ WREG32_SOC15(VCN, inst, regUVD_RB_RPTR, 0);
+ WREG32_SOC15(VCN, inst, regUVD_RB_WPTR, 0);
+
+ tmp = RREG32_SOC15(VCN, inst, regUVD_RB_RPTR);
+ WREG32_SOC15(VCN, inst, regUVD_RB_WPTR, tmp);
+ ring->wptr = RREG32_SOC15(VCN, inst, regUVD_RB_WPTR);
+
+ tmp = RREG32_SOC15(VCN, inst, regVCN_RB_ENABLE);
+ tmp |= VCN_RB_ENABLE__RB1_EN_MASK;
+ WREG32_SOC15(VCN, inst, regVCN_RB_ENABLE, tmp);
+ fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);
return 0;
}
@@ -1208,81 +1204,79 @@ static void vcn_v4_0_5_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)
*
* Stop VCN block
*/
-static int vcn_v4_0_5_stop(struct amdgpu_device *adev)
+static int vcn_v4_0_5_stop(struct amdgpu_device *adev, unsigned int inst)
{
volatile struct amdgpu_vcn4_fw_shared *fw_shared;
uint32_t tmp;
- int i, r = 0;
+ int r = 0;
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ goto done;
- fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
- fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF;
-
- if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
- vcn_v4_0_5_stop_dpg_mode(adev, i);
- continue;
- }
+ fw_shared = adev->vcn.inst[inst].fw_shared.cpu_addr;
+ fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF;
- /* wait for vcn idle */
- r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 0x7);
- if (r)
- return r;
-
- tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
- UVD_LMI_STATUS__READ_CLEAN_MASK |
- UVD_LMI_STATUS__WRITE_CLEAN_MASK |
- UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
- r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp);
- if (r)
- return r;
-
- /* disable LMI UMC channel */
- tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL2);
- tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
- WREG32_SOC15(VCN, i, regUVD_LMI_CTRL2, tmp);
- tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |
- UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
- r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp);
- if (r)
- return r;
-
- /* block VCPU register access */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL),
- UVD_RB_ARB_CTRL__VCPU_DIS_MASK,
- ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
-
- /* reset VCPU */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
- UVD_VCPU_CNTL__BLK_RST_MASK,
- ~UVD_VCPU_CNTL__BLK_RST_MASK);
-
- /* disable VCPU clock */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,
- ~(UVD_VCPU_CNTL__CLK_EN_MASK));
-
- /* apply soft reset */
- tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);
- tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
- WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);
- tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);
- tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
- WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);
+ if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
+ vcn_v4_0_5_stop_dpg_mode(adev, inst);
+ goto done;
+ }
- /* clear status */
- WREG32_SOC15(VCN, i, regUVD_STATUS, 0);
+ /* wait for vcn idle */
+ r = SOC15_WAIT_ON_RREG(VCN, inst, regUVD_STATUS, UVD_STATUS__IDLE, 0x7);
+ if (r)
+ return r;
- /* apply HW clock gating */
- vcn_v4_0_5_enable_clock_gating(adev, i);
+ tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
+ UVD_LMI_STATUS__READ_CLEAN_MASK |
+ UVD_LMI_STATUS__WRITE_CLEAN_MASK |
+ UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
+ r = SOC15_WAIT_ON_RREG(VCN, inst, regUVD_LMI_STATUS, tmp, tmp);
+ if (r)
+ return r;
- /* enable VCN power gating */
- vcn_v4_0_5_enable_static_power_gating(adev, i);
- }
+ /* disable LMI UMC channel */
+ tmp = RREG32_SOC15(VCN, inst, regUVD_LMI_CTRL2);
+ tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
+ WREG32_SOC15(VCN, inst, regUVD_LMI_CTRL2, tmp);
+ tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |
+ UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
+ r = SOC15_WAIT_ON_RREG(VCN, inst, regUVD_LMI_STATUS, tmp, tmp);
+ if (r)
+ return r;
+ /* block VCPU register access */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_RB_ARB_CTRL),
+ UVD_RB_ARB_CTRL__VCPU_DIS_MASK,
+ ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
+
+ /* reset VCPU */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_VCPU_CNTL),
+ UVD_VCPU_CNTL__BLK_RST_MASK,
+ ~UVD_VCPU_CNTL__BLK_RST_MASK);
+
+ /* disable VCPU clock */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_VCPU_CNTL), 0,
+ ~(UVD_VCPU_CNTL__CLK_EN_MASK));
+
+ /* apply soft reset */
+ tmp = RREG32_SOC15(VCN, inst, regUVD_SOFT_RESET);
+ tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
+ WREG32_SOC15(VCN, inst, regUVD_SOFT_RESET, tmp);
+ tmp = RREG32_SOC15(VCN, inst, regUVD_SOFT_RESET);
+ tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
+ WREG32_SOC15(VCN, inst, regUVD_SOFT_RESET, tmp);
+
+ /* clear status */
+ WREG32_SOC15(VCN, inst, regUVD_STATUS, 0);
+
+ /* apply HW clock gating */
+ vcn_v4_0_5_enable_clock_gating(adev, inst);
+
+ /* enable VCN power gating */
+ vcn_v4_0_5_enable_static_power_gating(adev, inst);
+done:
if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_uvd(adev, false);
+ amdgpu_dpm_enable_vcn(adev, false, 1);
return 0;
}
@@ -1535,20 +1529,19 @@ static int vcn_v4_0_5_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
struct amdgpu_device *adev = ip_block->adev;
+ int i = ip_block->instance;
int ret;
- for (int i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (state == adev->vcn.cur_state[i])
- return 0;
+ if (state == adev->vcn.cur_state[i])
+ return 0;
- if (state == AMD_PG_STATE_GATE)
- ret = vcn_v4_0_5_stop(adev);
- else
- ret = vcn_v4_0_5_start(adev);
+ if (state == AMD_PG_STATE_GATE)
+ ret = vcn_v4_0_5_stop(adev, i);
+ else
+ ret = vcn_v4_0_5_start(adev, i);
- if (!ret)
- adev->vcn.cur_state[i] = state;
- }
+ if (!ret)
+ adev->vcn.cur_state[i] = state;
return ret;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH 17/18] drm/amdgpu: power vcn 5_0_0 by instance
2024-10-02 4:36 [PATCH 00/18] Separating vcn power management by instance boyuan.zhang
` (15 preceding siblings ...)
2024-10-02 4:36 ` [PATCH 16/18] drm/amdgpu: power vcn 4_0_5 " boyuan.zhang
@ 2024-10-02 4:36 ` boyuan.zhang
2024-10-02 4:36 ` [PATCH 18/18] drm/amdgpu: set powergating state by vcn instance boyuan.zhang
17 siblings, 0 replies; 29+ messages in thread
From: boyuan.zhang @ 2024-10-02 4:36 UTC (permalink / raw)
To: amd-gfx, leo.liu, christian.koenig, alexander.deucher,
sunil.khatri
Cc: Boyuan Zhang
From: Boyuan Zhang <boyuan.zhang@amd.com>
For vcn 5_0_0, add ip_block for each vcn instance during discovery stage.
And only powering on/off one of the vcn instance using the
instance value stored in ip_block, instead of powering on/off all
vcn instances. Modify the existing functions to use the instance value
in ip_block, and remove the original for loop for all vcn instances.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 3 +-
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 441 +++++++++---------
2 files changed, 219 insertions(+), 225 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index 2f177bd39ed8..dd3b19141389 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -2362,7 +2362,8 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &jpeg_v4_0_5_ip_block);
break;
case IP_VERSION(5, 0, 0):
- amdgpu_device_ip_block_add(adev, &vcn_v5_0_0_ip_block);
+ for (i = 0; i < adev->vcn.num_vcn_inst; ++i)
+ amdgpu_device_ip_block_add_instance(adev, &vcn_v5_0_0_ip_block, i);
amdgpu_device_ip_block_add(adev, &jpeg_v5_0_0_ip_block);
break;
default:
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
index 65791fe2090b..705a12d0a45b 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
@@ -116,7 +116,7 @@ static int vcn_v5_0_0_sw_init(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_ring *ring;
struct amdgpu_device *adev = ip_block->adev;
- int i, r;
+ int inst = ip_block->instance, r;
uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_5_0);
uint32_t *ptr;
@@ -130,46 +130,44 @@ static int vcn_v5_0_0_sw_init(struct amdgpu_ip_block *ip_block)
if (r)
return r;
- for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
- volatile struct amdgpu_vcn5_fw_shared *fw_shared;
+ volatile struct amdgpu_vcn5_fw_shared *fw_shared;
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ goto done;
- atomic_set(&adev->vcn.inst[i].sched_score, 0);
+ atomic_set(&adev->vcn.inst[inst].sched_score, 0);
- /* VCN UNIFIED TRAP */
- r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
- VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq);
- if (r)
- return r;
-
- /* VCN POISON TRAP */
- r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
- VCN_4_0__SRCID_UVD_POISON, &adev->vcn.inst[i].irq);
- if (r)
- return r;
+ /* VCN UNIFIED TRAP */
+ r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[inst],
+ VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[inst].irq);
+ if (r)
+ return r;
- ring = &adev->vcn.inst[i].ring_enc[0];
- ring->use_doorbell = true;
- ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + 8 * i;
+ /* VCN POISON TRAP */
+ r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[inst],
+ VCN_4_0__SRCID_UVD_POISON, &adev->vcn.inst[inst].irq);
+ if (r)
+ return r;
- ring->vm_hub = AMDGPU_MMHUB0(0);
- sprintf(ring->name, "vcn_unified_%d", i);
+ ring = &adev->vcn.inst[inst].ring_enc[0];
+ ring->use_doorbell = true;
+ ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + 8 * inst;
- r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,
- AMDGPU_RING_PRIO_0, &adev->vcn.inst[i].sched_score);
- if (r)
- return r;
+ ring->vm_hub = AMDGPU_MMHUB0(0);
+ sprintf(ring->name, "vcn_unified_%d", inst);
- fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
- fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE);
- fw_shared->sq.is_enabled = 1;
+ r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[inst].irq, 0,
+ AMDGPU_RING_PRIO_0, &adev->vcn.inst[inst].sched_score);
+ if (r)
+ return r;
- if (amdgpu_vcnfw_log)
- amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]);
- }
+ fw_shared = adev->vcn.inst[inst].fw_shared.cpu_addr;
+ fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE);
+ fw_shared->sq.is_enabled = 1;
+ if (amdgpu_vcnfw_log)
+ amdgpu_vcn_fwlog_init(&adev->vcn.inst[inst]);
+done:
if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
adev->vcn.pause_dpg_mode = vcn_v5_0_0_pause_dpg_mode;
@@ -758,149 +756,147 @@ static int vcn_v5_0_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, b
*
* Start VCN block
*/
-static int vcn_v5_0_0_start(struct amdgpu_device *adev)
+static int vcn_v5_0_0_start(struct amdgpu_device *adev, unsigned int inst)
{
volatile struct amdgpu_vcn5_fw_shared *fw_shared;
struct amdgpu_ring *ring;
uint32_t tmp;
- int i, j, k, r;
+ int j, k, r;
if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_uvd(adev, true);
+ amdgpu_dpm_enable_vcn(adev, true, inst);
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ if (adev->vcn.harvest_config & (1 << inst))
+ return 0;
- fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
+ fw_shared = adev->vcn.inst[inst].fw_shared.cpu_addr;
- if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
- r = vcn_v5_0_0_start_dpg_mode(adev, i, adev->vcn.indirect_sram);
- continue;
- }
+ if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
+ r = vcn_v5_0_0_start_dpg_mode(adev, inst, adev->vcn.indirect_sram);
+ return r;
+ }
- /* disable VCN power gating */
- vcn_v5_0_0_disable_static_power_gating(adev, i);
+ /* disable VCN power gating */
+ vcn_v5_0_0_disable_static_power_gating(adev, inst);
- /* set VCN status busy */
- tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY;
- WREG32_SOC15(VCN, i, regUVD_STATUS, tmp);
+ /* set VCN status busy */
+ tmp = RREG32_SOC15(VCN, inst, regUVD_STATUS) | UVD_STATUS__UVD_BUSY;
+ WREG32_SOC15(VCN, inst, regUVD_STATUS, tmp);
- /* enable VCPU clock */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
- UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
+ /* enable VCPU clock */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_VCPU_CNTL),
+ UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
- /* disable master interrupt */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 0,
- ~UVD_MASTINT_EN__VCPU_EN_MASK);
+ /* disable master interrupt */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_MASTINT_EN), 0,
+ ~UVD_MASTINT_EN__VCPU_EN_MASK);
- /* enable LMI MC and UMC channels */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_LMI_CTRL2), 0,
- ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
-
- tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);
- tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
- tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
- WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);
-
- /* setup regUVD_LMI_CTRL */
- tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL);
- WREG32_SOC15(VCN, i, regUVD_LMI_CTRL, tmp |
- UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
- UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
- UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
- UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
-
- vcn_v5_0_0_mc_resume(adev, i);
-
- /* VCN global tiling registers */
- WREG32_SOC15(VCN, i, regUVD_GFX10_ADDR_CONFIG,
- adev->gfx.config.gb_addr_config);
-
- /* unblock VCPU register access */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 0,
- ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
-
- /* release VCPU reset to boot */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,
- ~UVD_VCPU_CNTL__BLK_RST_MASK);
-
- for (j = 0; j < 10; ++j) {
- uint32_t status;
-
- for (k = 0; k < 100; ++k) {
- status = RREG32_SOC15(VCN, i, regUVD_STATUS);
- if (status & 2)
- break;
- mdelay(10);
- if (amdgpu_emu_mode == 1)
- msleep(1);
- }
+ /* enable LMI MC and UMC channels */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_LMI_CTRL2), 0,
+ ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
- if (amdgpu_emu_mode == 1) {
- r = -1;
- if (status & 2) {
- r = 0;
- break;
- }
- } else {
+ tmp = RREG32_SOC15(VCN, inst, regUVD_SOFT_RESET);
+ tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
+ tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
+ WREG32_SOC15(VCN, inst, regUVD_SOFT_RESET, tmp);
+
+ /* setup regUVD_LMI_CTRL */
+ tmp = RREG32_SOC15(VCN, inst, regUVD_LMI_CTRL);
+ WREG32_SOC15(VCN, inst, regUVD_LMI_CTRL, tmp |
+ UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
+ UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
+ UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
+ UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
+
+ vcn_v5_0_0_mc_resume(adev, inst);
+
+ /* VCN global tiling registers */
+ WREG32_SOC15(VCN, inst, regUVD_GFX10_ADDR_CONFIG,
+ adev->gfx.config.gb_addr_config);
+
+ /* unblock VCPU register access */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_RB_ARB_CTRL), 0,
+ ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
+
+ /* release VCPU reset to boot */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_VCPU_CNTL), 0,
+ ~UVD_VCPU_CNTL__BLK_RST_MASK);
+
+ for (j = 0; j < 10; ++j) {
+ uint32_t status;
+
+ for (k = 0; k < 100; ++k) {
+ status = RREG32_SOC15(VCN, inst, regUVD_STATUS);
+ if (status & 2)
+ break;
+ mdelay(10);
+ if (amdgpu_emu_mode == 1)
+ msleep(1);
+ }
+
+ if (amdgpu_emu_mode == 1) {
+ r = -1;
+ if (status & 2) {
r = 0;
- if (status & 2)
- break;
-
- dev_err(adev->dev,
- "VCN[%d] is not responding, trying to reset the VCPU!!!\n", i);
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
- UVD_VCPU_CNTL__BLK_RST_MASK,
- ~UVD_VCPU_CNTL__BLK_RST_MASK);
- mdelay(10);
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,
- ~UVD_VCPU_CNTL__BLK_RST_MASK);
-
- mdelay(10);
- r = -1;
+ break;
}
+ } else {
+ r = 0;
+ if (status & 2)
+ break;
+
+ dev_err(adev->dev,
+ "VCN[%d] is not responding, trying to reset the VCPU!!!\n", inst);
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_VCPU_CNTL),
+ UVD_VCPU_CNTL__BLK_RST_MASK,
+ ~UVD_VCPU_CNTL__BLK_RST_MASK);
+ mdelay(10);
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_VCPU_CNTL), 0,
+ ~UVD_VCPU_CNTL__BLK_RST_MASK);
+
+ mdelay(10);
+ r = -1;
}
+ }
- if (r) {
- dev_err(adev->dev, "VCN[%d] is not responding, giving up!!!\n", i);
- return r;
- }
+ if (r) {
+ dev_err(adev->dev, "VCN[%d] is not responding, giving up!!!\n", inst);
+ return r;
+ }
- /* enable master interrupt */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN),
- UVD_MASTINT_EN__VCPU_EN_MASK,
- ~UVD_MASTINT_EN__VCPU_EN_MASK);
+ /* enable master interrupt */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_MASTINT_EN),
+ UVD_MASTINT_EN__VCPU_EN_MASK,
+ ~UVD_MASTINT_EN__VCPU_EN_MASK);
- /* clear the busy bit of VCN_STATUS */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_STATUS), 0,
- ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
+ /* clear the busy bit of VCN_STATUS */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_STATUS), 0,
+ ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
- ring = &adev->vcn.inst[i].ring_enc[0];
- WREG32_SOC15(VCN, i, regVCN_RB1_DB_CTRL,
- ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT |
- VCN_RB1_DB_CTRL__EN_MASK);
-
- WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring->gpu_addr);
- WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
- WREG32_SOC15(VCN, i, regUVD_RB_SIZE, ring->ring_size / 4);
-
- tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);
- tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK);
- WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);
- fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET;
- WREG32_SOC15(VCN, i, regUVD_RB_RPTR, 0);
- WREG32_SOC15(VCN, i, regUVD_RB_WPTR, 0);
-
- tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR);
- WREG32_SOC15(VCN, i, regUVD_RB_WPTR, tmp);
- ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR);
-
- tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);
- tmp |= VCN_RB_ENABLE__RB1_EN_MASK;
- WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);
- fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);
- }
+ ring = &adev->vcn.inst[inst].ring_enc[0];
+ WREG32_SOC15(VCN, inst, regVCN_RB1_DB_CTRL,
+ ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT |
+ VCN_RB1_DB_CTRL__EN_MASK);
+
+ WREG32_SOC15(VCN, inst, regUVD_RB_BASE_LO, ring->gpu_addr);
+ WREG32_SOC15(VCN, inst, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
+ WREG32_SOC15(VCN, inst, regUVD_RB_SIZE, ring->ring_size / 4);
+
+ tmp = RREG32_SOC15(VCN, inst, regVCN_RB_ENABLE);
+ tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK);
+ WREG32_SOC15(VCN, inst, regVCN_RB_ENABLE, tmp);
+ fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET;
+ WREG32_SOC15(VCN, inst, regUVD_RB_RPTR, 0);
+ WREG32_SOC15(VCN, inst, regUVD_RB_WPTR, 0);
+
+ tmp = RREG32_SOC15(VCN, inst, regUVD_RB_RPTR);
+ WREG32_SOC15(VCN, inst, regUVD_RB_WPTR, tmp);
+ ring->wptr = RREG32_SOC15(VCN, inst, regUVD_RB_WPTR);
+
+ tmp = RREG32_SOC15(VCN, inst, regVCN_RB_ENABLE);
+ tmp |= VCN_RB_ENABLE__RB1_EN_MASK;
+ WREG32_SOC15(VCN, inst, regVCN_RB_ENABLE, tmp);
+ fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);
return 0;
}
@@ -942,78 +938,76 @@ static void vcn_v5_0_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)
*
* Stop VCN block
*/
-static int vcn_v5_0_0_stop(struct amdgpu_device *adev)
+static int vcn_v5_0_0_stop(struct amdgpu_device *adev, unsigned int inst)
{
volatile struct amdgpu_vcn5_fw_shared *fw_shared;
uint32_t tmp;
- int i, r = 0;
-
- for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (adev->vcn.harvest_config & (1 << i))
- continue;
+ int r = 0;
- fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
- fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF;
+ if (adev->vcn.harvest_config & (1 << inst))
+ goto done;
- if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
- vcn_v5_0_0_stop_dpg_mode(adev, i);
- continue;
- }
+ fw_shared = adev->vcn.inst[inst].fw_shared.cpu_addr;
+ fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF;
- /* wait for vcn idle */
- r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 0x7);
- if (r)
- return r;
+ if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
+ vcn_v5_0_0_stop_dpg_mode(adev, inst);
+ goto done;
+ }
- tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
- UVD_LMI_STATUS__READ_CLEAN_MASK |
- UVD_LMI_STATUS__WRITE_CLEAN_MASK |
- UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
- r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp);
- if (r)
- return r;
+ /* wait for vcn idle */
+ r = SOC15_WAIT_ON_RREG(VCN, inst, regUVD_STATUS, UVD_STATUS__IDLE, 0x7);
+ if (r)
+ return r;
- /* disable LMI UMC channel */
- tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL2);
- tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
- WREG32_SOC15(VCN, i, regUVD_LMI_CTRL2, tmp);
- tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |
- UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
- r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp);
- if (r)
- return r;
+ tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
+ UVD_LMI_STATUS__READ_CLEAN_MASK |
+ UVD_LMI_STATUS__WRITE_CLEAN_MASK |
+ UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
+ r = SOC15_WAIT_ON_RREG(VCN, inst, regUVD_LMI_STATUS, tmp, tmp);
+ if (r)
+ return r;
- /* block VCPU register access */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL),
- UVD_RB_ARB_CTRL__VCPU_DIS_MASK,
- ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
-
- /* reset VCPU */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
- UVD_VCPU_CNTL__BLK_RST_MASK,
- ~UVD_VCPU_CNTL__BLK_RST_MASK);
-
- /* disable VCPU clock */
- WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,
- ~(UVD_VCPU_CNTL__CLK_EN_MASK));
-
- /* apply soft reset */
- tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);
- tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
- WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);
- tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);
- tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
- WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);
-
- /* clear status */
- WREG32_SOC15(VCN, i, regUVD_STATUS, 0);
-
- /* enable VCN power gating */
- vcn_v5_0_0_enable_static_power_gating(adev, i);
- }
+ /* disable LMI UMC channel */
+ tmp = RREG32_SOC15(VCN, inst, regUVD_LMI_CTRL2);
+ tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
+ WREG32_SOC15(VCN, inst, regUVD_LMI_CTRL2, tmp);
+ tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |
+ UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
+ r = SOC15_WAIT_ON_RREG(VCN, inst, regUVD_LMI_STATUS, tmp, tmp);
+ if (r)
+ return r;
+ /* block VCPU register access */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_RB_ARB_CTRL),
+ UVD_RB_ARB_CTRL__VCPU_DIS_MASK,
+ ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
+
+ /* reset VCPU */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_VCPU_CNTL),
+ UVD_VCPU_CNTL__BLK_RST_MASK,
+ ~UVD_VCPU_CNTL__BLK_RST_MASK);
+
+ /* disable VCPU clock */
+ WREG32_P(SOC15_REG_OFFSET(VCN, inst, regUVD_VCPU_CNTL), 0,
+ ~(UVD_VCPU_CNTL__CLK_EN_MASK));
+
+ /* apply soft reset */
+ tmp = RREG32_SOC15(VCN, inst, regUVD_SOFT_RESET);
+ tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
+ WREG32_SOC15(VCN, inst, regUVD_SOFT_RESET, tmp);
+ tmp = RREG32_SOC15(VCN, inst, regUVD_SOFT_RESET);
+ tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
+ WREG32_SOC15(VCN, inst, regUVD_SOFT_RESET, tmp);
+
+ /* clear status */
+ WREG32_SOC15(VCN, inst, regUVD_STATUS, 0);
+
+ /* enable VCN power gating */
+ vcn_v5_0_0_enable_static_power_gating(adev, inst);
+done:
if (adev->pm.dpm_enabled)
- amdgpu_dpm_enable_uvd(adev, false);
+ amdgpu_dpm_enable_vcn(adev, false, inst);
return 0;
}
@@ -1262,20 +1256,19 @@ static int vcn_v5_0_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state)
{
struct amdgpu_device *adev = ip_block->adev;
+ int i = ip_block->instance;
int ret;
- for (int i = 0; i < adev->vcn.num_vcn_inst; ++i) {
- if (state == adev->vcn.cur_state[i])
- return 0;
+ if (state == adev->vcn.cur_state[i])
+ return 0;
- if (state == AMD_PG_STATE_GATE)
- ret = vcn_v5_0_0_stop(adev);
- else
- ret = vcn_v5_0_0_start(adev);
+ if (state == AMD_PG_STATE_GATE)
+ ret = vcn_v5_0_0_stop(adev, i);
+ else
+ ret = vcn_v5_0_0_start(adev, i);
- if (!ret)
- adev->vcn.cur_state[i] = state;
- }
+ if (!ret)
+ adev->vcn.cur_state[i] = state;
return ret;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH 18/18] drm/amdgpu: set powergating state by vcn instance
2024-10-02 4:36 [PATCH 00/18] Separating vcn power management by instance boyuan.zhang
` (16 preceding siblings ...)
2024-10-02 4:36 ` [PATCH 17/18] drm/amdgpu: power vcn 5_0_0 " boyuan.zhang
@ 2024-10-02 4:36 ` boyuan.zhang
17 siblings, 0 replies; 29+ messages in thread
From: boyuan.zhang @ 2024-10-02 4:36 UTC (permalink / raw)
To: amd-gfx, leo.liu, christian.koenig, alexander.deucher,
sunil.khatri
Cc: Boyuan Zhang
From: Boyuan Zhang <boyuan.zhang@amd.com>
Set powergating state by vcn instance in idle_work_handler() and
ring_begin_use() functions for vcn with multiple instances.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 16 ++++++++++++----
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 28c5e15d166d..9a8e8f88e1ad 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -410,8 +410,12 @@ static void amdgpu_vcn_idle_work_handler(struct work_struct *work)
fence += amdgpu_fence_count_emitted(&adev->vcn.inst[inst].ring_dec);
if (!fence && !atomic_read(&adev->vcn.total_submission_cnt)) {
- amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
- AMD_PG_STATE_GATE);
+ if (adev->vcn.num_vcn_inst > 1)
+ amdgpu_device_ip_set_powergating_state_instance(adev,
+ AMD_IP_BLOCK_TYPE_VCN, AMD_PG_STATE_GATE, inst);
+ else
+ amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
+ AMD_PG_STATE_GATE);
r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO,
false);
if (r)
@@ -436,8 +440,12 @@ void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
}
mutex_lock(&adev->vcn.vcn_pg_lock);
- amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
- AMD_PG_STATE_UNGATE);
+ if (adev->vcn.num_vcn_inst > 1)
+ amdgpu_device_ip_set_powergating_state_instance(adev,
+ AMD_IP_BLOCK_TYPE_VCN, AMD_PG_STATE_UNGATE, ring->me);
+ else
+ amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
+ AMD_PG_STATE_UNGATE);
/* Only set DPG pause for VCN3 or below, VCN4 and above will be handled by FW */
if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG &&
--
2.34.1
^ permalink raw reply related [flat|nested] 29+ messages in thread