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From: Parag Warudkar <kernel-stuff@comcast.net>
To: Dave Jones <davej@redhat.com>
Cc: linux-kernel@vger.kernel.org, ak@suse.de
Subject: Re: pci cacheline size / latency oddness.
Date: Mon, 01 Aug 2005 20:41:49 -0400	[thread overview]
Message-ID: <1122943309.26405.7.camel@localhost> (raw)
In-Reply-To: <20050801233517.GA23172@redhat.com>

On Mon, 2005-08-01 at 19:35 -0400, Dave Jones wrote:
> This means we will do the wrong thing on AMD machines which have
> 64 byte cachelines.

pcibios_init (in i386/pci/common.c, which is linked in by X86_64 PCI
code) seems to do this 
 
if (c->x86 >= 6 && c->x86_vendor == X86_VENDOR_AMD)
                pci_cache_line_size = 64 >> 2;  /* K7 & K8 */

Is it correct to expect all AMD k7/8 machines to have 16 as cache line
size - I thought 64 was more appropriate?

On my Athlon64 laptop, all PCI devices end up having 0 latency. 

> x86-64 doesn't have an arch override for pci_cache_line_size

I am trying to fix it up - What's the right way to override it in x86_64
code?  Just initialize it to 64 may be?

Parag



  parent reply	other threads:[~2005-08-02  0:41 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2005-08-01 23:35 pci cacheline size / latency oddness Dave Jones
2005-08-02  0:05 ` Jeff Garzik
2005-08-02  0:41 ` Parag Warudkar [this message]
2005-08-03 13:20   ` Andi Kleen
2005-08-03 10:58 ` Andi Kleen

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