From: Dave Jones <davej@redhat.com>
To: linux-kernel@vger.kernel.org
Cc: ak@suse.de
Subject: pci cacheline size / latency oddness.
Date: Mon, 1 Aug 2005 19:35:17 -0400 [thread overview]
Message-ID: <20050801233517.GA23172@redhat.com> (raw)
During boot of todays -git, I noticed this..
PCI: Setting latency timer of device 0000:00:1d.7 to 64
after boot, lspci shows..
00:1d.7 USB Controller: Intel Corporation 82801EB/ER (ICH5/ICH5R) USB2 EHCI Controller (rev 02) (prog-if 20 [EHCI])
Subsystem: Dell: Unknown device 0169
Flags: bus master, medium devsel, latency 0, IRQ 201
^^
It also complains about..
PCI: cache line size of 128 is not supported by device 0000:00:1d.7
x86-64 doesn't have an arch override for pci_cache_line_size, so
it ends up at L1_CACHE_BYTES >> 2, which is 128 if you build
x86-64 kernels with CONFIG_GENERIC_CPU or CONFIG_MPSC
This means we will do the wrong thing on AMD machines which have
64 byte cachelines. I saw this problem however on an em64t box.
Would it make sense to shift >> once more if it fails, and retry
with a smaller size perhaps ?
Dave
next reply other threads:[~2005-08-01 23:35 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2005-08-01 23:35 Dave Jones [this message]
2005-08-02 0:05 ` pci cacheline size / latency oddness Jeff Garzik
2005-08-02 0:41 ` Parag Warudkar
2005-08-03 13:20 ` Andi Kleen
2005-08-03 10:58 ` Andi Kleen
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