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From: Sergio Monteiro Basto <sergio@sergiomb.no-ip.org>
To: Kimball Murray <kimball.murray@gmail.com>
Cc: linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org
Subject: Re: [git Patch 1/1] avoid IRQ0 ioapic pin collision
Date: Sun, 23 Apr 2006 06:02:24 +0100	[thread overview]
Message-ID: <1145768544.2858.8.camel@localhost.portugal> (raw)
In-Reply-To: <20060420230931.10317.38083.sendpatchset@dhcp83-97.boston.redhat.com>

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On Thu, 2006-04-20 at 19:14 -0400, Kimball Murray wrote:
> Our system uses an ACPI Interrupt Source Override to inform the OS
> that the
> 8254 timer (IRQ0) is on pin 1 of the ioapic.  On that same ioapic, pin
> 0
> handles an interrupt from a PCI device.  The work-around for the VIA
> chipset
> now causes pin 0 to get IRQ0 on our platform, which the timer also
> claims.
> The sad result is both pins 0 and 1 drive IRQ0, but pins 0 and 1 have
> different triggering characterists (and polarity), so time learches
> forward
> in an IRQ0 interrupt storm. 

And how I now if my via motherboard suffers this problem ?

Could be something like this messages :
Losing some ticks... checking if CPU frequency changed.

Thanks,
-- 
Sérgio M. B.

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      parent reply	other threads:[~2006-04-23  4:59 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2006-04-20 23:14 [git Patch 1/1] avoid IRQ0 ioapic pin collision Kimball Murray
2006-04-20 23:14 ` Kimball Murray
2006-04-21  2:17 ` Andi Kleen
2006-04-23  5:02 ` Sergio Monteiro Basto [this message]

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