* [PATCH] ARM: OMAP: Use write/read_reg functions for SDRAM controller on OMAP2.
@ 2006-06-13 10:28 Komal Shah
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From: Komal Shah @ 2006-06-13 10:28 UTC (permalink / raw)
To: linux-omap-open-source
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From nobody Mon Sep 17 00:00:00 2001
From: Komal Shah <komal_shah802003@yahoo.com>
Date: Tue, 13 Jun 2006 21:26:06 +0530
Subject: [PATCH] ARM: OMAP: Use write/read_reg functions for SDRAM controller on OMAP2.
Signed-off-by: Komal Shah <komal_shah802003@yahoo.com>
---
arch/arm/mach-omap2/clock.c | 14 -------
arch/arm/mach-omap2/memory.c | 64 +++++++++++++++++++++++++++++-----
arch/arm/mach-omap2/memory.h | 1 +
arch/arm/mach-omap2/prcm-regs.h | 8 ----
arch/arm/mach-omap2/sram-fn.S | 4 +-
include/asm-arm/arch-omap/omap24xx.h | 2 +
6 files changed, 58 insertions(+), 35 deletions(-)
28cdb9184a69b10ed2eb7fc282fc3d3d7dcd1e83
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 6789dd4..719a5e2 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -373,20 +373,6 @@ static long omap2_clk_round_rate(struct
return clk->rate;
}
-/*
- * Check the DLL lock state, and return tue if running in unlock mode.
- * This is needed to compenste for the shifted DLL value in unlock mode.
- */
-static u32 omap2_dll_force_needed(void)
-{
- u32 dll_state = SDRC_DLLA_CTRL; /* dlla and dllb are a set */
-
- if ((dll_state & (1 << 2)) == (1 << 2))
- return 1;
- else
- return 0;
-}
-
static u32 omap2_reprogram_sdrc(u32 level, u32 force)
{
u32 slow_dll_ctrl, fast_dll_ctrl, m_type;
diff --git a/arch/arm/mach-omap2/memory.c b/arch/arm/mach-omap2/memory.c
index 1d925d6..e53ba00 100644
--- a/arch/arm/mach-omap2/memory.c
+++ b/arch/arm/mach-omap2/memory.c
@@ -28,11 +28,31 @@ #include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/sram.h>
-#include "prcm-regs.h"
#include "memory.h"
+#define SDRC_SYSCONFIG 0x010
+#define SDRC_DLLA_CTRL 0x060
+#define DLLPHASE_90 (1 << 1)
+#define UNLOCK_DLL (1 << 2)
+#define SDRC_DLLA_STATUS 0x064
+#define SDRC_DLLB_CTRL 0x068
+#define SDRC_DLLB_STATUS 0x06C
+#define SDRC_POWER 0x070
+#define SDRC_MR_0 0x084
+
+static void __iomem *sdrc_base;
static struct memory_timings mem_timings;
+static inline void sdrc_write_reg(int idx, u32 val)
+{
+ __raw_writel(val, sdrc_base + idx);
+}
+
+static inline u32 sdrc_read_reg(int idx)
+{
+ return __raw_readl(sdrc_base + idx);
+}
+
u32 omap2_memory_get_slow_dll_ctrl(void)
{
return mem_timings.slow_dll_ctrl;
@@ -48,13 +68,27 @@ u32 omap2_memory_get_type(void)
return mem_timings.m_type;
}
+/*
+ * Check the DLL lock state, and return tue if running in unlock mode.
+ * This is needed to compenste for the shifted DLL value in unlock mode.
+ */
+u32 omap2_dll_force_needed(void)
+{
+ /* dlla and dllb are a set */
+ u32 dll_state = sdrc_read_reg(SDRC_DLLA_CTRL);
+ if ((dll_state & (1 << 2)) == (1 << 2))
+ return 1;
+ else
+ return 0;
+}
+
void omap2_init_memory_params(u32 force_lock_to_unlock_mode)
{
unsigned long dll_cnt;
u32 fast_dll = 0;
- mem_timings.m_type = !((SDRC_MR_0 & 0x3) == 0x1); /* DDR = 1, SDR = 0 */
-
+ /* DDR = 1, SDR = 0 */
+ mem_timings.m_type = !((sdrc_read_reg(SDRC_MR_0) & 0x3) == 0x1);
/* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others.
* In the case of 2422, its ok to use CS1 instead of CS0.
*/
@@ -67,17 +101,17 @@ void omap2_init_memory_params(u32 force_
return;
/* With DDR we need to determine the low frequency DLL value */
- if (((mem_timings.fast_dll_ctrl & (1 << 2)) == M_LOCK_CTRL))
+ if (((mem_timings.fast_dll_ctrl & UNLOCK_DLL) == M_LOCK_CTRL))
mem_timings.dll_mode = M_UNLOCK;
else
mem_timings.dll_mode = M_LOCK;
if (mem_timings.base_cs == 0) {
- fast_dll = SDRC_DLLA_CTRL;
- dll_cnt = SDRC_DLLA_STATUS & 0xff00;
+ fast_dll = sdrc_read_reg(SDRC_DLLA_CTRL);
+ dll_cnt = sdrc_read_reg(SDRC_DLLA_STATUS) & 0xff00;
} else {
- fast_dll = SDRC_DLLB_CTRL;
- dll_cnt = SDRC_DLLB_STATUS & 0xff00;
+ fast_dll = sdrc_read_reg(SDRC_DLLB_CTRL);
+ dll_cnt = sdrc_read_reg(SDRC_DLLB_STATUS) & 0xff00;
}
if (force_lock_to_unlock_mode) {
fast_dll &= ~0xff00;
@@ -95,8 +129,18 @@ void omap2_init_memory_params(u32 force_
/* Turn status into unlock ctrl */
mem_timings.slow_dll_ctrl |=
- ((mem_timings.fast_dll_ctrl & 0xF) | (1 << 2));
+ ((mem_timings.fast_dll_ctrl & 0xF) | UNLOCK_DLL);
/* 90 degree phase for anything below 133Mhz + disable DLL filter */
- mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8));
+ mem_timings.slow_dll_ctrl |= (DLLPHASE_90 | (3 << 8));
+}
+
+
+static int __init omap2_memory_init(void)
+{
+ if (cpu_is_omap2420())
+ sdrc_base = (void __iomem *)io_p2v(OMAP242X_SDRC_BASE);
+
+ return 0;
}
+arch_initcall(omap2_memory_init);
diff --git a/arch/arm/mach-omap2/memory.h b/arch/arm/mach-omap2/memory.h
index d212eea..3e84d39 100644
--- a/arch/arm/mach-omap2/memory.h
+++ b/arch/arm/mach-omap2/memory.h
@@ -32,3 +32,4 @@ extern void omap2_init_memory_params(u32
extern u32 omap2_memory_get_slow_dll_ctrl(void);
extern u32 omap2_memory_get_fast_dll_ctrl(void);
extern u32 omap2_memory_get_type(void);
+extern u32 omap2_dll_force_needed(void);
diff --git a/arch/arm/mach-omap2/prcm-regs.h b/arch/arm/mach-omap2/prcm-regs.h
index 22ac7be..db63dd2 100644
--- a/arch/arm/mach-omap2/prcm-regs.h
+++ b/arch/arm/mach-omap2/prcm-regs.h
@@ -262,14 +262,6 @@ #define GPTIMER1_TCAR2 GPT1_REG32(0x044
/* rkw -- base fix up please... */
#define GPTIMER3_TISR __REG32(OMAP24XX_L4_IO_BASE + 0x78018)
-/* SDRC */
-#define SDRC_DLLA_CTRL __REG32(OMAP24XX_SDRC_BASE + 0x060)
-#define SDRC_DLLA_STATUS __REG32(OMAP24XX_SDRC_BASE + 0x064)
-#define SDRC_DLLB_CTRL __REG32(OMAP24XX_SDRC_BASE + 0x068)
-#define SDRC_DLLB_STATUS __REG32(OMAP24XX_SDRC_BASE + 0x06C)
-#define SDRC_POWER __REG32(OMAP24XX_SDRC_BASE + 0x070)
-#define SDRC_MR_0 __REG32(OMAP24XX_SDRC_BASE + 0x084)
-
/* GPIO 1 */
#define GPIO1_BASE GPIOX_BASE(1)
#define GPIO1_REG32(offset) __REG32(GPIO1_BASE + (offset))
diff --git a/arch/arm/mach-omap2/sram-fn.S b/arch/arm/mach-omap2/sram-fn.S
index d261e4f..e559bb0 100644
--- a/arch/arm/mach-omap2/sram-fn.S
+++ b/arch/arm/mach-omap2/sram-fn.S
@@ -39,8 +39,8 @@ #define CM_CLKEN_PLL_V IO_ADDRESS(OMAP2
#define CM_IDLEST_CKGEN_V IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x520)
#define CM_CLKSEL1_PLL_V IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x540)
-#define SDRC_DLLA_CTRL_V IO_ADDRESS(OMAP24XX_SDRC_BASE + 0x060)
-#define SDRC_RFR_CTRL_V IO_ADDRESS(OMAP24XX_SDRC_BASE + 0x0a4)
+#define SDRC_DLLA_CTRL_V IO_ADDRESS(OMAP242X_SDRC_BASE + 0x060)
+#define SDRC_RFR_CTRL_V IO_ADDRESS(OMAP242X_SDRC_BASE + 0x0a4)
.text
diff --git a/include/asm-arm/arch-omap/omap24xx.h b/include/asm-arm/arch-omap/omap24xx.h
index 6e59805..fa43502 100644
--- a/include/asm-arm/arch-omap/omap24xx.h
+++ b/include/asm-arm/arch-omap/omap24xx.h
@@ -18,7 +18,7 @@ #define IRQ_SIR_IRQ 0x0040
#define OMAP24XX_32KSYNCT_BASE (L4_24XX_BASE + 0x4000)
#define OMAP24XX_PRCM_BASE (L4_24XX_BASE + 0x8000)
-#define OMAP24XX_SDRC_BASE (L3_24XX_BASE + 0x9000)
+#define OMAP242X_SDRC_BASE (L3_24XX_BASE + 0x9000)
#endif /* __ASM_ARCH_OMAP24XX_H */
--
1.3.3
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2006-06-13 10:28 [PATCH] ARM: OMAP: Use write/read_reg functions for SDRAM controller on OMAP2 Komal Shah
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