From: Thomas Gleixner <tglx@linutronix.de>
To: "Vladimir A. Barinov" <vbarinov@ru.mvista.com>
Cc: Todd Poynor <tpoynor@mvista.com>,
linux-mtd@lists.infradead.org, linux-mips@linux-mips.org
Subject: Re: [PATCH] PNX8550 NAND flash driver
Date: Mon, 10 Jul 2006 11:53:16 +0200 [thread overview]
Message-ID: <1152525196.30929.11.camel@localhost> (raw)
In-Reply-To: <43F1D439.60205@ru.mvista.com>
On Tue, 2006-02-14 at 15:59 +0300, Vladimir A. Barinov wrote:
> >> + }
> >> +
> >> + if (((bytes & 3) || (bytes < 16)) || ((u32) to & 3) || ((u32)
> >> from & 3)) {
> >> + if (((bytes & 1) == 0) &&
> >> + (((u32) to & 1) == 0) && (((u32) from & 1) == 0)) {
> >> + int words = bytes / 2;
> >> +
> >> + local_irq_disable();
> >> + for (i = 0; i < words; i++) {
> >> + to16[i] = from16[i];
> >> + }
> >> + local_irq_enable();
> >
> >
> > Really necessary to disable all irqs around this transfer? How long
> > can interrupts be off during that time?
>
> That is needed since the NAND device is binded to the external XIO bus
> that could be used by another devices.
Err, you have to protect the whole access sequence then. What protects
the chip against access between the command write and data read ?
If this really is a bus conflict problem, then you need some more
protection than this.
Can you please describe in detail why you think this is necessary.
tglx
WARNING: multiple messages have this Message-ID (diff)
From: Thomas Gleixner <tglx@linutronix.de>
To: "Vladimir A. Barinov" <vbarinov@ru.mvista.com>
Cc: linux-mtd@lists.infradead.org, Todd Poynor <tpoynor@mvista.com>,
linux-mips@linux-mips.org
Subject: Re: [PATCH] PNX8550 NAND flash driver
Date: Mon, 10 Jul 2006 11:53:16 +0200 [thread overview]
Message-ID: <1152525196.30929.11.camel@localhost> (raw)
In-Reply-To: <43F1D439.60205@ru.mvista.com>
On Tue, 2006-02-14 at 15:59 +0300, Vladimir A. Barinov wrote:
> >> + }
> >> +
> >> + if (((bytes & 3) || (bytes < 16)) || ((u32) to & 3) || ((u32)
> >> from & 3)) {
> >> + if (((bytes & 1) == 0) &&
> >> + (((u32) to & 1) == 0) && (((u32) from & 1) == 0)) {
> >> + int words = bytes / 2;
> >> +
> >> + local_irq_disable();
> >> + for (i = 0; i < words; i++) {
> >> + to16[i] = from16[i];
> >> + }
> >> + local_irq_enable();
> >
> >
> > Really necessary to disable all irqs around this transfer? How long
> > can interrupts be off during that time?
>
> That is needed since the NAND device is binded to the external XIO bus
> that could be used by another devices.
Err, you have to protect the whole access sequence then. What protects
the chip against access between the command write and data read ?
If this really is a bus conflict problem, then you need some more
protection than this.
Can you please describe in detail why you think this is necessary.
tglx
next prev parent reply other threads:[~2006-07-10 9:53 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2005-12-16 17:23 [PATCH] PNX8550 NAND flash driver Vladimir A. Barinov
2005-12-16 17:23 ` Vladimir A. Barinov
2005-12-20 14:27 ` Vladimir A. Barinov
2005-12-20 14:28 ` Vladimir A. Barinov
2006-01-12 18:24 ` Todd Poynor
2006-01-12 18:24 ` Todd Poynor
2006-02-14 12:59 ` Vladimir A. Barinov
2006-02-14 13:00 ` Vladimir A. Barinov
2006-02-22 0:57 ` Todd Poynor
2006-02-22 0:57 ` Todd Poynor
2006-07-10 9:53 ` Thomas Gleixner [this message]
2006-07-10 9:53 ` Thomas Gleixner
2006-07-25 18:34 ` Jurgen
2006-07-25 18:34 ` Jurgen
2006-07-26 7:02 ` Thomas Gleixner
2006-07-26 7:02 ` Thomas Gleixner
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