PPC405EP errata CPU 213 (Incorrect data may be flushed from the data cache)

PPC405EP errata CPU 213 (Incorrect data may be flushed from the data cache)

[Darcy Watkins]

Hello,

The IBM/AMCC errata document recommends setting reserved bits 1 & 3 in
CCR0 as a workaround to PPC405EP errata CPU 213 (Incorrect data may be
flushed from the data cache).  For a start, I just tried hacking in a
few lines of assembly code into...

  arch/powerpc/kernel/head_40x.S

---

Around line #839 ...

	bl	early_init	/* We have to do this with MMU on */

/*
 * Decide what sort of machine this is and initialize the MMU.
 */
	mr	r3,r31
	mr	r4,r30
	mr	r5,r29
	mr	r6,r28
	mr	r7,r27
	bl	machine_init
	bl	MMU_init
/* DLW hack!! - for PPC405EP errata CPU 213 */
	mfspr	r4,SPRN_CCR0
	oris	r4,r4,0x5000
	mtspr	SPRN_CCR0,r4
	isync

/* Go back to running unmapped so we can load up new values
 * and change to using our exception vectors.
 * On the 4xx, all we have to do is invalidate the TLB to clear
 * the old 16M byte TLB mappings.
 */
	lis	r4,2f@h
...

Since I am not a PowerPC assembler guru, does this appear right?

I think that eventually I'd want to create a cpu_setup_40x.S with the
fixup code as part of a setup_cpu_405ep function and then hook this into
cputable.c, but first I want to make sure that the errata workaround is
actually taking effect (and also not being undone by later startup
code).

-- 


Regards,

Darcy

--------------
Darcy L. Watkins - Senior Software Developer
Tranzeo Wireless Technologies, Inc.
19273 Fraser Way, Pitt Meadows, BC, Canada V3Y 2V4
T:604-460-6002 ext:410
http://www.tranzeo.com

RE: PPC405EP errata CPU 213 (Incorrect data may be flushed from thedata cache)

[Stephen Neuendorffer]

[-- Attachment #1: Type: text/plain, Size: 2843 bytes --]


arch/powerpc/boot/virtex405-head.S has:

#include "ppc_asm.h"

        .text
        .global _zimage_start
_zimage_start:

        /* PPC errata 213: needed by Virtex-4 FX */
        mfccr0  0
        oris    0,0,0x50000000@h
        mtccr0  0

So, this happens first before anything else.
Without this, the boards that I've used crash pretty quickly, so it may be obvious that the status register is set properly.
As a result, you probably need to do it in the boot loader and not in the kernel proper.

Steve

-----Original Message-----
From: linuxppc-embedded-bounces+stephen=neuendorffer.name@ozlabs.org on behalf of Darcy Watkins
Sent: Tue 8/26/2008 9:01 AM
To: linuxppc-embedded
Subject: PPC405EP errata CPU 213 (Incorrect data may be flushed from thedata cache)
 
Hello,

The IBM/AMCC errata document recommends setting reserved bits 1 & 3 in
CCR0 as a workaround to PPC405EP errata CPU 213 (Incorrect data may be
flushed from the data cache).  For a start, I just tried hacking in a
few lines of assembly code into...

  arch/powerpc/kernel/head_40x.S

---

Around line #839 ...

	bl	early_init	/* We have to do this with MMU on */

/*
 * Decide what sort of machine this is and initialize the MMU.
 */
	mr	r3,r31
	mr	r4,r30
	mr	r5,r29
	mr	r6,r28
	mr	r7,r27
	bl	machine_init
	bl	MMU_init
/* DLW hack!! - for PPC405EP errata CPU 213 */
	mfspr	r4,SPRN_CCR0
	oris	r4,r4,0x5000
	mtspr	SPRN_CCR0,r4
	isync

/* Go back to running unmapped so we can load up new values
 * and change to using our exception vectors.
 * On the 4xx, all we have to do is invalidate the TLB to clear
 * the old 16M byte TLB mappings.
 */
	lis	r4,2f@h
...

Since I am not a PowerPC assembler guru, does this appear right?

I think that eventually I'd want to create a cpu_setup_40x.S with the
fixup code as part of a setup_cpu_405ep function and then hook this into
cputable.c, but first I want to make sure that the errata workaround is
actually taking effect (and also not being undone by later startup
code).

-- 


Regards,

Darcy

--------------
Darcy L. Watkins - Senior Software Developer
Tranzeo Wireless Technologies, Inc.
19273 Fraser Way, Pitt Meadows, BC, Canada V3Y 2V4
T:604-460-6002 ext:410
http://www.tranzeo.com


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