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From: Alok Kataria <akataria@vmware.com>
To: "H. Peter Anvin" <hpa@zytor.com>
Cc: Andi Kleen <andi@firstfloor.org>, Ingo Molnar <mingo@elte.hu>,
	LKML <linux-kernel@vger.kernel.org>,
	the arch/x86 maintainers <x86@kernel.org>,
	Daniel Hecht <dhecht@vmware.com>
Subject: [PATCH 0/4] V3 Hypervisor detection and tsc_reliable feature definition
Date: Fri, 24 Oct 2008 17:21:27 -0700	[thread overview]
Message-ID: <1224894087.28224.69.camel@alok-dev1> (raw)

Hi,

These patches define a framework for hypervisor detection and setting of
hypervisor feature bits. We define a X86_FEATURE_TSC_RELIABLE bit which
is a synthetic bit. This is set when running under VMware. This  feature
bit is used to skip TSC checks which can fail on virtualization platform
due to timing differences when running on virtual cpus.

Thanks,
Alok



             reply	other threads:[~2008-10-25  0:21 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2008-10-25  0:21 Alok Kataria [this message]
2008-10-27 11:02 ` [PATCH 0/4] V3 Hypervisor detection and tsc_reliable feature definition Ingo Molnar

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