From: Ingo Molnar <mingo@elte.hu>
To: Alok Kataria <akataria@vmware.com>
Cc: "H. Peter Anvin" <hpa@zytor.com>,
Andi Kleen <andi@firstfloor.org>,
LKML <linux-kernel@vger.kernel.org>,
the arch/x86 maintainers <x86@kernel.org>,
Daniel Hecht <dhecht@vmware.com>
Subject: Re: [PATCH 0/4] V3 Hypervisor detection and tsc_reliable feature definition
Date: Mon, 27 Oct 2008 12:02:18 +0100 [thread overview]
Message-ID: <20081027110218.GD13641@elte.hu> (raw)
In-Reply-To: <1224894087.28224.69.camel@alok-dev1>
* Alok Kataria <akataria@vmware.com> wrote:
> Hi,
>
> These patches define a framework for hypervisor detection and
> setting of hypervisor feature bits. We define a
> X86_FEATURE_TSC_RELIABLE bit which is a synthetic bit. This is set
> when running under VMware. This feature bit is used to skip TSC
> checks which can fail on virtualization platform due to timing
> differences when running on virtual cpus.
okay, this looks a lot better structurally - the DMI angle and the
synthetic CPU flag, and the clocksource smarts are all a clean
approach. Peter, any objections?
Ingo
prev parent reply other threads:[~2008-10-27 11:02 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-10-25 0:21 [PATCH 0/4] V3 Hypervisor detection and tsc_reliable feature definition Alok Kataria
2008-10-27 11:02 ` Ingo Molnar [this message]
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