Re: ASOC: For SND_SOC_DAIFMT_IB_IF what is invert baseed on?

[Liam Girdwood <lrg@slimlogic.co.uk>]

On Mon, 2008-10-27 at 11:00 +0800, Richard Zhao wrote:
> 2008/10/27 Liam Girdwood <lrg@slimlogic.co.uk>:
> > On Sun, 2008-10-26 at 00:31 +0800, Richard Zhao wrote:
> >> Hi,
> >>
> >> include/sound/soc.h
> >> /*
> >>  * DAI hardware signal inversions
> >>  */
> >> #define SND_SOC_DAIFMT_NB_NF            (0 << 8)        /* normal bclk + frm */
> >> #define SND_SOC_DAIFMT_NB_IF            (1 << 8)        /* normal bclk
> >> + inv frm */
> >> #define SND_SOC_DAIFMT_IB_NF            (2 << 8)        /* invert bclk
> >> + nor frm */
> >> #define SND_SOC_DAIFMT_IB_IF            (3 << 8)        /* invert bclk + frm */
> >>
> >> What are frame cock and bit clock invert based on? I2S, PCM or some
> >> else bus protocols? Or just high level voltage or low level voltage?
> >>
> >
> > Generic logic levels (high/low voltage) that can apply to I2S and PCM
> > DAI's.
> >
> > Liam
> >
> >
> It's not bus protocol depended.

Correct, it does not depend on bus protocol. Although, it wont apply to
well defined protocols like AC97.

> For frame start, LRCLK normal  is 1, invert is 0.
> For data valid,  BCLK normal is 1, invert is 0
> Is that what you meant?

Not quite, the clock is simply inverted compared to it's normal level.

> 
> But when wm8350 in i2s mode, it take SND_SOC_DAIFMT_NB_NF as LRCLK is
> 0 for frame start.

I2S frame start is the LRC going high (from low) to indicate left
channel PCM data is available after the next bit clock.

Do you have another issue that is causing you to check clock
inversions ? Fwiw the wm8350 audio is mature and known to be working for
some time.

Liam