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From: Mans Rullgard <mans@mansr.com>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PATCH 2/2] target-sh4: implement ftrv instruction
Date: Fri, 21 Nov 2008 19:55:42 +0000	[thread overview]
Message-ID: <1227297342-5285-2-git-send-email-mans@mansr.com> (raw)
In-Reply-To: <1227297342-5285-1-git-send-email-mans@mansr.com>

This partially implements the ftrv instruction.  It gives correct
results under normal conditions.  FPU exceptions are not correctly
generated.

Signed-off-by: Mans Rullgard <mans@mansr.com>
---
 target-sh4/translate.c |   40 ++++++++++++++++++++++++++++++++++++++++
 1 files changed, 40 insertions(+), 0 deletions(-)

diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 2d6dfe6..9c2da41 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -1694,6 +1694,46 @@ static void _decode_opc(DisasContext * ctx)
 	    tcg_temp_free_i64(fp);
 	}
 	return;
+    case 0xf0fd: /* ftrv XMTRX,FVn */
+        if ((ctx->opcode & 0x300) != 0x100)
+            break;
+        if (!(ctx->fpscr & FPSCR_PR)) {
+            TCGv fv[4];
+            TCGv fp;
+            int n = B11_8 & 0xc;
+            int i;
+
+            /*
+             * NOTE: The values calculated here are likely to differ
+             * from hardware since the hardware sacrifices accuracy
+             * for speed in this instruction.
+             *
+             * FIXME: FPU exceptions are not correctly raised here.
+             */
+
+            fp = tcg_temp_new();
+
+            for (i = 0; i < 4; i++) {
+                fv[i] = tcg_temp_new();
+                tcg_gen_mov_i32(fv[i], cpu_fregs[n+i]);
+            }
+
+            for (i = 0; i < 4; i++) {
+                gen_helper_fmul_FT(cpu_fregs[n+i], cpu_fregs[16+i], fv[0]);
+                gen_helper_fmul_FT(fp,             cpu_fregs[20+i], fv[1]);
+                gen_helper_fadd_FT(cpu_fregs[n+i], cpu_fregs[n+i],  fp);
+                gen_helper_fmul_FT(fp,             cpu_fregs[24+i], fv[2]);
+                gen_helper_fadd_FT(cpu_fregs[n+i], cpu_fregs[n+i],  fp);
+                gen_helper_fmul_FT(fp,             cpu_fregs[28+i], fv[3]);
+                gen_helper_fadd_FT(cpu_fregs[n+i], cpu_fregs[n+i],  fp);
+            }
+
+            for (i = 0; i < 4; i++)
+                tcg_temp_free(fv[i]);
+            tcg_temp_free(fp);
+            return;
+        }
+        break;
     }
 
     fprintf(stderr, "unknown instruction 0x%04x at pc 0x%08x\n",
-- 
1.6.0.4

  reply	other threads:[~2008-11-21 19:55 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2008-11-21 19:55 [Qemu-devel] [PATCH 1/2] target-sh4: fix 64-bit fmov to/from memory Mans Rullgard
2008-11-21 19:55 ` Mans Rullgard [this message]
2009-02-03 20:28   ` [Qemu-devel] [PATCH 2/2] target-sh4: implement ftrv instruction Aurelien Jarno
2008-11-21 20:38 ` [Qemu-devel] [PATCH 1/2] target-sh4: fix 64-bit fmov to/from memory Aurelien Jarno
2008-11-21 21:24   ` [Qemu-devel] " Måns Rullgård
2008-11-21 21:46     ` Aurelien Jarno
2008-11-21 22:23       ` [Qemu-devel] [PATCH] " Mans Rullgard
2008-11-21 23:02         ` Aurelien Jarno
2008-11-21 23:30           ` [Qemu-devel] " Måns Rullgård
2008-11-21 23:55             ` Aurelien Jarno
2008-11-22  0:51               ` [Qemu-devel] " Mans Rullgard
2008-11-22 10:09                 ` Aurelien Jarno
2008-11-21 22:25       ` [Qemu-devel] Re: [PATCH 1/2] " Måns Rullgård
  -- strict thread matches above, loose matches on Subject: below --
2008-11-21  0:47 [Qemu-devel] [PATCH 2/2] target-sh4: implement ftrv instruction Mans Rullgard

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