From: Aurelien Jarno <aurelien@aurel32.net>
To: qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH] target-sh4: fix 64-bit fmov to/from memory
Date: Sat, 22 Nov 2008 00:02:58 +0100 [thread overview]
Message-ID: <20081121230258.GC4884@volta.aurel32.net> (raw)
In-Reply-To: <1227306234-14368-1-git-send-email-mans@mansr.com>
On Fri, Nov 21, 2008 at 10:23:54PM +0000, Mans Rullgard wrote:
> When loading/storing a register pair, the even-numbered register
> always maps to the low 32 bits of memory independently of target
> endian configuration.
>
> Signed-off-by: Mans Rullgard <mans@mansr.com>
> ---
> target-sh4/translate.c | 61 ++++++++++++++++++++++++-----------------------
> 1 files changed, 31 insertions(+), 30 deletions(-)
>
> diff --git a/target-sh4/translate.c b/target-sh4/translate.c
> index 84a3f40..74894e9 100644
> --- a/target-sh4/translate.c
> +++ b/target-sh4/translate.c
> @@ -991,31 +991,35 @@ static void _decode_opc(DisasContext * ctx)
> return;
> case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */
> if (ctx->fpscr & FPSCR_SZ) {
> - TCGv_i64 fp = tcg_temp_new_i64();
> - gen_load_fpr64(fp, XREG(B7_4));
> - tcg_gen_qemu_st64(fp, REG(B11_8), ctx->memidx);
> - tcg_temp_free_i64(fp);
> + TCGv addr_hi = tcg_temp_new();
> + int fr = XREG(B7_4);
> + tcg_gen_addi_i32(addr_hi, REG(B11_8), 4);
> + tcg_gen_qemu_st32(cpu_fregs[fr ], REG(B11_8), ctx->memidx);
> + tcg_gen_qemu_st32(cpu_fregs[fr+1], addr_hi, ctx->memidx);
> + tcg_temp_free(addr_hi);
> } else {
> tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], REG(B11_8), ctx->memidx);
> }
> return;
> case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */
> if (ctx->fpscr & FPSCR_SZ) {
> - TCGv_i64 fp = tcg_temp_new_i64();
> - tcg_gen_qemu_ld64(fp, REG(B7_4), ctx->memidx);
> - gen_store_fpr64(fp, XREG(B11_8));
> - tcg_temp_free_i64(fp);
> + TCGv addr_hi = tcg_temp_new();
> + int fr = XREG(B11_8);
> + tcg_gen_addi_i32(addr_hi, REG(B7_4), 4);
> + tcg_gen_qemu_ld32u(cpu_fregs[fr ], REG(B7_4), ctx->memidx);
> + tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr_hi, ctx->memidx);
> + tcg_temp_free(addr_hi);
> } else {
> tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], REG(B7_4), ctx->memidx);
> }
> return;
> case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */
> if (ctx->fpscr & FPSCR_SZ) {
> - TCGv_i64 fp = tcg_temp_new_i64();
> - tcg_gen_qemu_ld64(fp, REG(B7_4), ctx->memidx);
> - gen_store_fpr64(fp, XREG(B11_8));
> - tcg_temp_free_i64(fp);
> - tcg_gen_addi_i32(REG(B7_4),REG(B7_4), 8);
> + int fr = XREG(B11_8);
> + tcg_gen_qemu_ld32u(cpu_fregs[fr ], REG(B7_4), ctx->memidx);
> + tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
> + tcg_gen_qemu_ld32u(cpu_fregs[fr+1], REG(B7_4), ctx->memidx);
> + tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
This is wrong, the address register should only be incremented after the
last load instruction, so that it has the correct value in case of
exception.
> } else {
> tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], REG(B7_4), ctx->memidx);
> tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
> @@ -1023,16 +1027,13 @@ static void _decode_opc(DisasContext * ctx)
> return;
> case 0xf00b: /* fmov {F,D,X}Rm,@-Rn - FPSCR: Nothing */
> if (ctx->fpscr & FPSCR_SZ) {
> - TCGv addr;
> - TCGv_i64 fp;
> - addr = tcg_temp_new();
> - tcg_gen_subi_i32(addr, REG(B11_8), 8);
> - fp = tcg_temp_new_i64();
> - gen_load_fpr64(fp, XREG(B7_4));
> - tcg_gen_qemu_st64(fp, addr, ctx->memidx);
> - tcg_temp_free_i64(fp);
> - tcg_temp_free(addr);
> + TCGv addr = tcg_temp_new_i32();
> + int fr = XREG(B7_4);
> + tcg_gen_subi_i32(addr, REG(B11_8), 4);
> tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 8);
> + tcg_gen_qemu_st32(cpu_fregs[fr ], REG(B11_8), ctx->memidx);
> + tcg_gen_qemu_st32(cpu_fregs[fr+1], addr, ctx->memidx);
Same here.
> + tcg_temp_free(addr);
> } else {
> TCGv addr;
> addr = tcg_temp_new_i32();
> @@ -1047,10 +1048,10 @@ static void _decode_opc(DisasContext * ctx)
> TCGv addr = tcg_temp_new_i32();
> tcg_gen_add_i32(addr, REG(B7_4), REG(0));
> if (ctx->fpscr & FPSCR_SZ) {
> - TCGv_i64 fp = tcg_temp_new_i64();
> - tcg_gen_qemu_ld64(fp, addr, ctx->memidx);
> - gen_store_fpr64(fp, XREG(B11_8));
> - tcg_temp_free_i64(fp);
> + int fr = XREG(B11_8);
> + tcg_gen_qemu_ld32u(cpu_fregs[fr ], addr, ctx->memidx);
> + tcg_gen_addi_i32(addr, addr, 4);
> + tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr, ctx->memidx);
> } else {
> tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], addr, ctx->memidx);
> }
> @@ -1062,10 +1063,10 @@ static void _decode_opc(DisasContext * ctx)
> TCGv addr = tcg_temp_new();
> tcg_gen_add_i32(addr, REG(B11_8), REG(0));
> if (ctx->fpscr & FPSCR_SZ) {
> - TCGv_i64 fp = tcg_temp_new_i64();
> - gen_load_fpr64(fp, XREG(B7_4));
> - tcg_gen_qemu_st64(fp, addr, ctx->memidx);
> - tcg_temp_free_i64(fp);
> + int fr = XREG(B7_4);
> + tcg_gen_qemu_ld32u(cpu_fregs[fr ], addr, ctx->memidx);
> + tcg_gen_addi_i32(addr, addr, 4);
> + tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr, ctx->memidx);
> } else {
> tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], addr, ctx->memidx);
> }
Otherwise looks ok.
--
.''`. Aurelien Jarno | GPG: 1024D/F1BCDB73
: :' : Debian developer | Electrical Engineer
`. `' aurel32@debian.org | aurelien@aurel32.net
`- people.debian.org/~aurel32 | www.aurel32.net
next prev parent reply other threads:[~2008-11-21 23:03 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-11-21 19:55 [Qemu-devel] [PATCH 1/2] target-sh4: fix 64-bit fmov to/from memory Mans Rullgard
2008-11-21 19:55 ` [Qemu-devel] [PATCH 2/2] target-sh4: implement ftrv instruction Mans Rullgard
2009-02-03 20:28 ` Aurelien Jarno
2008-11-21 20:38 ` [Qemu-devel] [PATCH 1/2] target-sh4: fix 64-bit fmov to/from memory Aurelien Jarno
2008-11-21 21:24 ` [Qemu-devel] " Måns Rullgård
2008-11-21 21:46 ` Aurelien Jarno
2008-11-21 22:23 ` [Qemu-devel] [PATCH] " Mans Rullgard
2008-11-21 23:02 ` Aurelien Jarno [this message]
2008-11-21 23:30 ` [Qemu-devel] " Måns Rullgård
2008-11-21 23:55 ` Aurelien Jarno
2008-11-22 0:51 ` [Qemu-devel] " Mans Rullgard
2008-11-22 10:09 ` Aurelien Jarno
2008-11-21 22:25 ` [Qemu-devel] Re: [PATCH 1/2] " Måns Rullgård
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