From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
To: Trent Piepho <tpiepho@freescale.com>
Cc: linuxppc-dev@ozlabs.org
Subject: Re: [PATCH] powerpc: Fix bogus cache flushing on all 40x and BookE processors
Date: Thu, 04 Dec 2008 11:06:07 +1100 [thread overview]
Message-ID: <1228349167.7356.272.camel@pasglop> (raw)
In-Reply-To: <Pine.LNX.4.64.0812031451450.7648@t2.domain.actdsltmp>
On Wed, 2008-12-03 at 15:09 -0800, Trent Piepho wrote:
> #ifdef __powerpc64__
> #define LONG_ASM_CONST(x) ASM_CONST(x)
> #else
> #define LONG_ASM_CONST(x) 0
> #endif
>
> #define CPU_FTR_NOEXECUTE LONG_ASM_CONST(0x0000000800000000)
>
> Am I not looking at the right code? Since e200 and e500 aren't powerpc64,
> doesn't adding CPU_FTR_NOEXECUTE have no effect at all?
No, you are right, this is a case where I didn't actually verify that
the patch had the expected effect :-(
We are running out of low FTR bits, heck, I might make them 64-bit
for everybody soon.
I'll fix that up, thanks for spotting it.
Cheers,
Ben.
next prev parent reply other threads:[~2008-12-04 0:08 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-12-01 6:01 [PATCH] powerpc: Fix bogus cache flushing on all 40x and BookE processors Benjamin Herrenschmidt
2008-12-02 7:36 ` Kumar Gala
2008-12-02 9:20 ` Benjamin Herrenschmidt
2008-12-03 23:09 ` Trent Piepho
2008-12-04 0:06 ` Benjamin Herrenschmidt [this message]
2008-12-02 15:41 ` Steven A. Falco
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