From: Kenneth Johansson <kenneth@southpole.se>
To: David Jander <david.jander@protonic.nl>
Cc: linuxppc-dev@ozlabs.org, Paul Mackerras <paulus@samba.org>,
gunnar@genesi-usa.com, Wolfgang Denk <wd@denx.de>
Subject: Re: [RFC][PATCH v5] MPC5121 TLB errata workaround
Date: Mon, 16 Mar 2009 17:34:00 +0100 [thread overview]
Message-ID: <1237221240.28786.6.camel@localhost.localdomain> (raw)
In-Reply-To: <200903161652.09747.david.jander@protonic.nl>
On Mon, 2009-03-16 at 16:52 +0100, David Jander wrote:
> Complete workaround for DTLB errata in e300c2/c3/c4 processors.
>
> Due to the bug, the hardware-implemented LRU algorythm always goes to way
> 1 of the TLB. This fix implements the proposed software workaround in
> form of a LRW table for chosing the TLB-way.
>
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> Signed-off-by: David Jander <david@protonic.nl>
I think we have a winner. with one instruction slot left :)
I tried your V4 and V5 and could not see any difference in speed.
Acked-by: Kenneth Johansson <kenneth@southpole.se>
next prev parent reply other threads:[~2009-03-16 16:52 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-03-16 15:52 [RFC][PATCH v5] MPC5121 TLB errata workaround David Jander
2009-03-16 16:09 ` David Jander
2009-03-16 17:47 ` Kumar Gala
2009-03-16 16:34 ` Kenneth Johansson [this message]
2009-03-16 18:05 ` Kumar Gala
2009-03-17 10:38 ` David Jander
2009-03-17 12:43 ` Kumar Gala
2009-06-06 22:07 ` Wolfgang Denk
2009-06-06 22:42 ` Benjamin Herrenschmidt
2009-06-08 18:16 ` Kumar Gala
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