From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
To: Wolfgang Denk <wd@denx.de>
Cc: linuxppc-dev@ozlabs.org, David Jander <david.jander@protonic.nl>,
gunnar@genesi-usa.com, Paul Mackerras <paulus@samba.org>
Subject: Re: [RFC][PATCH v5] MPC5121 TLB errata workaround
Date: Sun, 07 Jun 2009 08:42:04 +1000 [thread overview]
Message-ID: <1244328124.31984.40.camel@pasglop> (raw)
In-Reply-To: <20090606220723.A38DA832E416@gemini.denx.de>
On Sun, 2009-06-07 at 00:07 +0200, Wolfgang Denk wrote:
> Dear David Jander,
>
> In message <200903161652.09747.david.jander@protonic.nl> you wrote:
> > Complete workaround for DTLB errata in e300c2/c3/c4 processors.
> >
> > Due to the bug, the hardware-implemented LRU algorythm always goes to way
> > 1 of the TLB. This fix implements the proposed software workaround in
> > form of a LRW table for chosing the TLB-way.
> >
> > Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> > Signed-off-by: David Jander <david@protonic.nl>
>
> What is the actual status of this patch?
>
> Patchwork (http://patchwork.ozlabs.org/patch/24502/) says it's
> "superseded" - but by what?
>
> I can't see such code in mainline - what happened to it?
I can see the code in mainline ... but only in the -data- TLB miss
handler, not the instruction one...
Kumar ? Shouldn't we have the workaround in both ?
Cheers,
Ben.
next prev parent reply other threads:[~2009-06-06 22:42 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-03-16 15:52 [RFC][PATCH v5] MPC5121 TLB errata workaround David Jander
2009-03-16 16:09 ` David Jander
2009-03-16 17:47 ` Kumar Gala
2009-03-16 16:34 ` Kenneth Johansson
2009-03-16 18:05 ` Kumar Gala
2009-03-17 10:38 ` David Jander
2009-03-17 12:43 ` Kumar Gala
2009-06-06 22:07 ` Wolfgang Denk
2009-06-06 22:42 ` Benjamin Herrenschmidt [this message]
2009-06-08 18:16 ` Kumar Gala
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