From: Peter Tyser <ptyser@xes-inc.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] Odd value for I2C_TIMEOUT in fsl_i2c.c
Date: Fri, 04 Sep 2009 10:28:12 -0500 [thread overview]
Message-ID: <1252078092.6005.63.camel@localhost.localdomain> (raw)
In-Reply-To: <4AA12E52.2080403@freescale.com>
On Fri, 2009-09-04 at 10:12 -0500, Timur Tabi wrote:
> Wolfgang Denk wrote:
>
> > Wrong Question. I don't know enough about the I2C protocol. Why is
> > i2c_wait4bus necessary?
>
> Ok, why is it necessary?
Freescale's I2C core supports multiple masters. I'd guess that
i2c_wait4bus() is used to ensure the bus is not in use by a different
master before initiating a read or write. Its polling the MBB status
bit, which is automatically set/cleared when the controller sees a
START/STOP which supports this.
If this is the case, the timeout should be the maximum (or reasonable
maximum) time an I2C transaction could take.
Best,
Peter
next prev parent reply other threads:[~2009-09-04 15:28 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-09-03 15:22 [U-Boot] Odd value for I2C_TIMEOUT in fsl_i2c.c Timur Tabi
2009-09-04 7:16 ` Heiko Schocher
2009-09-04 9:25 ` Wolfgang Denk
2009-09-04 14:09 ` Timur Tabi
2009-09-04 15:01 ` Wolfgang Denk
2009-09-04 15:12 ` Timur Tabi
2009-09-04 15:28 ` Peter Tyser [this message]
2009-09-04 15:30 ` Timur Tabi
2009-09-04 16:04 ` Peter Tyser
2009-09-04 18:30 ` Wolfgang Denk
2009-09-04 18:39 ` Timur Tabi
2009-09-04 19:28 ` Wolfgang Denk
2009-09-04 18:28 ` Wolfgang Denk
2009-09-04 15:29 ` Wolfgang Denk
2009-09-04 18:34 ` Scott Wood
2009-09-04 19:23 ` Wolfgang Denk
2009-09-04 19:28 ` Scott Wood
2009-09-04 8:31 ` Wolfgang Denk
2009-09-04 18:36 ` Scott Wood
2009-09-04 19:27 ` Wolfgang Denk
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